path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.848053                       # Number of seconds simulated
sim_ticks                                2848053071500                       # Number of ticks simulated
final_tick                               2848053071500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 153295                       # Simulator instruction rate (inst/s)
host_op_rate                                   185627                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3443122383                       # Simulator tick rate (ticks/s)
host_mem_usage                                 659004                       # Number of bytes of host memory used
host_seconds                                   827.17                       # Real time elapsed on the host
sim_insts                                   126801159                       # Number of instructions simulated
sim_ops                                     153545030                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1683840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1312624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8530944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           199296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           609360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       366080                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12712960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1683840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       199296                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1883136                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8845504                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8863068                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          137                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26310                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21032                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133296                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3114                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9541                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5720                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199182                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138211                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142602                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              591225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              460885                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2995360                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           360                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               69976                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              213957                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       128537                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4463737                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         591225                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          69976                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             661201                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3105807                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6153                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3111974                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3105807                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             591225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             467038                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2995360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              69976                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             213971                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       128537                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7575711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199182                       # Number of read requests accepted
system.physmem.writeReqs                       142602                       # Number of write requests accepted
system.physmem.readBursts                      199182                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     142602                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12737472                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8875904                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12712960                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8863068                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          49648                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12703                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12645                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12416                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12383                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15579                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12155                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12470                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12693                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11969                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11857                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12504                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11838                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11708                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12391                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11950                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11762                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9214                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9232                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9104                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8883                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8269                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8437                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8818                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8777                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8437                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8418                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9013                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8780                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8383                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8480                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8424                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8017                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
system.physmem.totGap                    2848052462500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  198602                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 138211                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     87578                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11612                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9452                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7822                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4675                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3805                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       696                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      208                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2725                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        89100                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.573648                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     137.731983                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     302.151175                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46893     52.63%     52.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17637     19.79%     72.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6363      7.14%     79.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3624      4.07%     83.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2948      3.31%     86.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1436      1.61%     88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          938      1.05%     89.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          975      1.09%     90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8286      9.30%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          89100                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6864                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.995047                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      543.916897                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6863     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6864                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6864                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.204837                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.711823                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.958888                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5637     82.12%     82.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             489      7.12%     89.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              82      1.19%     90.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             154      2.24%     92.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              37      0.54%     93.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             124      1.81%     95.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              47      0.68%     95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              16      0.23%     95.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              21      0.31%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              19      0.28%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.15%     96.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             153      2.23%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.01%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.07%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              30      0.44%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.06%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.16%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6864                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5502163905                       # Total ticks spent queuing
system.physmem.totMemAccLat                9233845155                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    995115000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27645.87                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46395.87                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.47                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.46                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165564                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     83044                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.87                       # Row buffer hit rate for writes
system.physmem.avgGap                      8332901.66                       # Average gap between requests
system.physmem.pageHitRate                      73.61                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  347056920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  189366375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 803743200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                458356320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186020568240                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            84074155830                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1635078931500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1906972178385                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.571882                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719967809945                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95102540000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32976648805                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  326539080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  178171125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 748628400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                440328960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186020568240                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            83156024340                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635884310000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1906754570145                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.495475                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2721316836638                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95102540000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31633548862                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               36422708                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17757542                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1699668                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20591819                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               15078708                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            73.226693                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               11344544                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            821497                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    72997                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               72997                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47155                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25842                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        72997                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          72997    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        72997                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7509                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9271.690184                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  8241.046102                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         7465     99.41%     99.41% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           36      0.48%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            7      0.09%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7509                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    581566000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      581566000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    581566000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5843     77.81%     77.81% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1666     22.19%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7509                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        72997                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        72997                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7509                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7509                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        80506                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24918355                       # DTB read hits
system.cpu0.dtb.read_misses                     66392                       # DTB read misses
system.cpu0.dtb.write_hits                   18544526                       # DTB write hits
system.cpu0.dtb.write_misses                     6605                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3803                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1293                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2019                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      636                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24984747                       # DTB read accesses
system.cpu0.dtb.write_accesses               18551131                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43462881                       # DTB hits
system.cpu0.dtb.misses                          72997                       # DTB misses
system.cpu0.dtb.accesses                     43535878                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     4165                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                4165                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3841                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         4165                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           4165    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         4165                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2676                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9686.198014                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6109.891448                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2598     97.09%     97.09% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767           50      1.87%     98.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           27      1.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2676                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    580856500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      580856500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    580856500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2357     88.08%     88.08% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          319     11.92%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2676                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4165                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4165                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2676                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2676                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    71531107                       # ITB inst hits
system.cpu0.itb.inst_misses                      4165                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2451                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     8112                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                71535272                       # ITB inst accesses
system.cpu0.itb.hits                         71531107                       # DTB hits
system.cpu0.itb.misses                           4165                       # DTB misses
system.cpu0.itb.accesses                     71535272                       # DTB accesses
system.cpu0.numCycles                       246249018                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  113090684                       # Number of instructions committed
system.cpu0.committedOps                    136745700                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8942808                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1853                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5449882320                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.177447                       # CPI: cycles per instruction
system.cpu0.ipc                              0.459253                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
system.cpu0.tickCycles                      199226503                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       47022515                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           754267                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          495.799422                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           41868735                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           754779                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            55.471516                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        600230000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.799422                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.968358                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.968358                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         86874809                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        86874809                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23308542                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23308542                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17374131                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17374131                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329905                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       329905                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374910                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374910                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371257                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       371257                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     40682673                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        40682673                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     41012578                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41012578                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       490349                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       490349                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       600389                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       600389                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141605                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       141605                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21484                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21484                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20155                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20155                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1090738                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1090738                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1232343                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1232343                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6919620500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6919620500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  11358969500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  11358969500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328836500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    328836500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    472700000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    472700000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       403000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       403000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  18278590000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  18278590000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  18278590000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  18278590000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     23798891                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23798891                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17974520                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17974520                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471510                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       471510                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396394                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396394                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391412                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391412                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     41773411                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     41773411                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     42244921                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     42244921                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020604                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.020604                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033402                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033402                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300322                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300322                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054199                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054199                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051493                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051493                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026111                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026111                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029171                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029171                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16758.002380                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16758.002380                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14832.388385                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14832.388385                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       540480                       # number of writebacks
system.cpu0.dcache.writebacks::total           540480                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        76076                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        76076                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       264589                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       264589                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14754                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14754                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       340665                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       340665                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       340665                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       340665                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       414273                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       414273                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       335800                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       335800                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107967                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       107967                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6730                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6730                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20155                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20155                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       750073                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       750073                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       858040                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       858040                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32040                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32040                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28722                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28722                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60762                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60762                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5238286000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5238286000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6456534000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6456534000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1810830000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1810830000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104761500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104761500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    452552000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    452552000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       396000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       396000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11694820000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11694820000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13505650000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13505650000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6348331500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6348331500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5156547500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5156547500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11504879000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11504879000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017407                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017407                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018682                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018682                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228981                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228981                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016978                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016978                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051493                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051493                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017956                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017956                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020311                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020311                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12644.526677                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12644.526677                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15591.575753                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15591.575753                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15740.117011                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15740.117011                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198137.687266                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198137.687266                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          2044285                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.729271                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           69477789                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          2044797                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            33.977842                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6924011000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.729271                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999471                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999471                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          230                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        145090031                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       145090031                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     69477789                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       69477789                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     69477789                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        69477789                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     69477789                       # number of overall hits
system.cpu0.icache.overall_hits::total       69477789                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      2044818                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2044818                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      2044818                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2044818                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      2044818                       # number of overall misses
system.cpu0.icache.overall_misses::total      2044818                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20517256500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  20517256500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  20517256500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  20517256500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  20517256500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  20517256500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     71522607                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     71522607                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     71522607                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     71522607                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     71522607                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     71522607                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028590                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028590                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028590                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028590                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028590                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028590                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10033.781246                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10033.781246                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10033.781246                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10033.781246                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10033.781246                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10033.781246                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2044818                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      2044818                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      2044818                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      2044818                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      2044818                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      2044818                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3915                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3915                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3915                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3915                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19494848000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  19494848000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19494848000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  19494848000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19494848000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  19494848000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557217500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557217500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557217500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    557217500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028590                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028590                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028590                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9533.781491                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9533.781491                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9533.781491                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1923323                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1923513                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          165                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       243791                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          310417                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16162.197478                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           5245257                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          326630                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           16.058712                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2827807181000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6560.031691                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    62.859334                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.055204                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5926.735945                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1926.535864                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1685.979439                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.400393                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003837                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000003                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.361739                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.117586                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.102904                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986462                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          984                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15223                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          330                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          428                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          218                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4188                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8533                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2180                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.060059                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.929138                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        93116780                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       93116780                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        86201                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4393                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         90594                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       540479                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       540479                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28758                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28758                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2008                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2008                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233257                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       233257                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1970223                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1970223                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       427246                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       427246                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        86201                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4393                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1970223                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       660503                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2721320                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        86201                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4393                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1970223                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       660503                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2721320                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          779                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           93                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          872                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26665                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26665                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18145                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18145                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        47128                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        47128                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        74595                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        74595                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101717                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101717                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          779                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           93                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        74595                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       148845                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       224312                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          779                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           93                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        74595                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       148845                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       224312                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     36149500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2302000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     38451500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    622250500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    622250500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    390027000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    390027000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       384498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       384498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3148896999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   3148896999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4603637500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4603637500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550040997                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550040997                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     36149500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2302000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4603637500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6698937996                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  11341026996                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     36149500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2302000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4603637500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6698937996                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  11341026996                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        86980                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4486                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        91466                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       540479                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       540479                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55423                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55423                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280385                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       280385                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2044818                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      2044818                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       528963                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       528963                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        86980                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4486                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2044818                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       809348                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2945632                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        86980                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4486                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2044818                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       809348                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2945632                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.009534                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.481118                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.481118                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.900362                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.900362                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.168083                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.168083                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.036480                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.036480                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.192295                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.192295                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.036480                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.183907                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.076151                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.036480                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.183907                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.076151                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44095.756881                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 23335.852241                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 23335.852241                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21495.012400                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21495.012400                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       192249                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       192249                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66815.841941                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66815.841941                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 61715.094845                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 61715.094845                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34901.157103                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34901.157103                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 61715.094845                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45006.133871                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 50559.163112                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 61715.094845                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45006.133871                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 50559.163112                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          102                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       205168                       # number of writebacks
system.cpu0.l2cache.writebacks::total          205168                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5239                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5239                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           89                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           89                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          602                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          602                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           89                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5841                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5930                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           89                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5841                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5930                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          779                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           93                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          872                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        10393                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total        10393                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       251914                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       251914                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26665                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26665                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18145                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18145                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41889                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41889                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        74506                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        74506                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101115                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101115                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          779                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           93                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        74506                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143004                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       218382                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          779                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           93                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        74506                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143004                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       251914                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       470296                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3915                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32040                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35955                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28722                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28722                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3915                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60762                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64677                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     33219500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21126531245                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21126531245                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    933301999                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    933301999                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    299858500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    299858500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       342498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       342498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2392710000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2392710000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4153675000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4153675000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2908093997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2908093997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4153675000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5300803997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   9487698497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4153675000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5300803997                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21126531245                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  30614229742                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    525897000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6091912000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6617809000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4940592000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4940592000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    525897000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11032504000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11558401000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009534                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.481118                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.481118                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.900362                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.900362                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149398                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149398                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.036436                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.191157                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.191157                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176690                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.074138                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176690                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.159659                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       171249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       171249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      5752448                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2898331                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44168                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       171817                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       171638                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          179                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        142841                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2765458                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28722                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28722                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       746343                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2333999                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       319529                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        85747                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42548                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112824                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       299375                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       296092                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2044818                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       602268                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3078                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6106044                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2739032                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12492                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       185819                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          9043387                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    131118848                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     90716354                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       347920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         222201066                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     910866                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      6693455                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.042507                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.201876                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           6409112     95.75%     95.75% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            284164      4.25%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               179      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       6693455                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3504755489                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115583734                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   3073459276                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1298870694                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      8011489                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     98861455                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                3534290                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          1990183                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           201553                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2067319                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1417438                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            68.564068                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 735878                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             53173                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    21952                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               21952                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        17656                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4296                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        21952                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          21952    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        21952                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1858                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8000.267562                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1715     92.30%     92.30% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          133      7.16%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            6      0.32%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            1      0.05%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.05%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::212992-229375            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1858                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -2099073032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -2099073032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -2099073032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1319     70.99%     70.99% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          539     29.01%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1858                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1858                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1858                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        23810                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3504265                       # DTB read hits
system.cpu1.dtb.read_misses                     20273                       # DTB read misses
system.cpu1.dtb.write_hits                    2919622                       # DTB write hits
system.cpu1.dtb.write_misses                     1679                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1723                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       86                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   239                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3524538                       # DTB read accesses
system.cpu1.dtb.write_accesses                2921301                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6423887                       # DTB hits
system.cpu1.dtb.misses                          21952                       # DTB misses
system.cpu1.dtb.accesses                      6445839                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1951                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1951                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          155                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1796                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1951                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1951    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1951                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          845                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4130.106784                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          149     17.63%     17.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          569     67.34%     84.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          107     12.66%     97.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.12%     97.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671            9      1.07%     98.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            4      0.47%     99.29% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            4      0.47%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          845                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -2099960532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -2099960532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -2099960532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          705     83.43%     83.43% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          140     16.57%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          845                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1951                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1951                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          845                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          845                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2796                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     6761340                       # ITB inst hits
system.cpu1.itb.inst_misses                      1951                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     909                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1020                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 6763291                       # ITB inst accesses
system.cpu1.itb.hits                          6761340                       # DTB hits
system.cpu1.itb.misses                           1951                       # DTB misses
system.cpu1.itb.accesses                      6763291                       # DTB accesses
system.cpu1.numCycles                        39381699                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   13710475                       # Number of instructions committed
system.cpu1.committedOps                     16799330                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1340837                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2719                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5656091241                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.872380                       # CPI: cycles per instruction
system.cpu1.ipc                              0.348143                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2719                       # number of quiesce instructions executed
system.cpu1.tickCycles                       26653258                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       12728441                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           152894                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          470.093140                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6072239                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           153243                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            39.624903                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     110033723500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   470.093140                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.918151                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.918151                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          286                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.681641                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12903758                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12903758                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3189039                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3189039                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2677291                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2677291                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41980                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        41980                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69267                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        69267                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        60867                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        60867                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5866330                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5866330                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5908310                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5908310                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       130563                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       130563                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       120040                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       120040                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24252                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24252                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16672                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16672                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23310                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23310                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       250603                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        250603                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       274855                       # number of overall misses
system.cpu1.dcache.overall_misses::total       274855                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2128187500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2128187500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4337924000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4337924000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    321753000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    321753000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    615942500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    615942500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1442500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1442500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6466111500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6466111500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6466111500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6466111500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3319602                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3319602                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2797331                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2797331                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66232                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        66232                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        85939                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        85939                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84177                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        84177                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6116933                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6116933                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6183165                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6183165                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039331                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.039331                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042912                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.042912                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.366167                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.366167                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.193998                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.193998                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.276916                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.276916                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040969                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.040969                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044452                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044452                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.081187                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16300.081187                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36137.320893                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 36137.320893                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19299.004319                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19299.004319                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26423.959674                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26423.959674                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        95329                       # number of writebacks
system.cpu1.dcache.writebacks::total            95329                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12149                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        12149                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        41106                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        41106                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11576                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11576                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        53255                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        53255                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        53255                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        53255                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118414                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       118414                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78934                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        78934                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23724                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23724                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5096                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5096                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23310                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23310                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       197348                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       197348                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       221072                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       221072                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2845                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2845                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2191                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2191                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5036                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5036                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1811744000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1811744000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2651572500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2651572500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    432946000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    432946000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     92138000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     92138000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    592646500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    592646500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1428500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1428500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4463316500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4463316500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4896262500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4896262500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    356276500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    356276500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    224816500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    224816500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    581093000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    581093000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035671                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035671                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028218                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028218                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.358195                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.358195                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059298                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.059298                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.276916                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.276916                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032263                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.032263                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035754                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035754                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15300.082760                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15300.082760                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33592.273292                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33592.273292                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18249.283426                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18249.283426                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18080.455259                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           837637                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.228366                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            5922018                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           838149                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.065591                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72771979500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.228366                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975055                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975055                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          465                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         14358483                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        14358483                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      5922018                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        5922018                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      5922018                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         5922018                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      5922018                       # number of overall hits
system.cpu1.icache.overall_hits::total        5922018                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       838149                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       838149                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       838149                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        838149                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       838149                       # number of overall misses
system.cpu1.icache.overall_misses::total       838149                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7371671000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7371671000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7371671000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7371671000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7371671000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7371671000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      6760167                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      6760167                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      6760167                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      6760167                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      6760167                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      6760167                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.123983                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.123983                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.123983                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.123983                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.123983                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.123983                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8795.179616                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8795.179616                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8795.179616                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8795.179616                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8795.179616                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8795.179616                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       838149                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       838149                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       838149                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       838149                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       838149                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       838149                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6952596500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   6952596500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6952596500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   6952596500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6952596500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   6952596500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15127000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15127000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15127000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     15127000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.123983                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.123983                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.123983                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8295.179616                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8295.179616                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8295.179616                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135062.500000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135062.500000                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       119402                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       119476                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           64                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        48156                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           37250                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15275.676235                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1897057                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           52360                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           36.231035                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  7998.087446                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    32.292792                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.074638                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4213.861593                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2174.488490                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   856.871276                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.488165                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001971                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.257194                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.132720                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.052299                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.932353                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1099                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           91                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13920                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           56                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1042                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           57                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1993                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11603                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.067078                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005554                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.849609                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        33573934                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       33573934                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23345                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2401                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         25746                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks        95329                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total        95329                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1276                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1276                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          784                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          784                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17759                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        17759                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       825014                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       825014                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        81245                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        81245                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23345                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2401                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       825014                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        99004                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         949764                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23345                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2401                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       825014                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        99004                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        949764                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          724                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          240                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          964                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        27711                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        27711                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22526                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22526                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32189                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32189                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13135                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        13135                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        65988                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        65988                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          724                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          240                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        13135                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        98177                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       112276                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          724                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          240                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        13135                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        98177                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       112276                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     16832000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4807500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     21639500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    545169500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    545169500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    480035000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    480035000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1407500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1407500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1686123500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1686123500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    733172000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    733172000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1579312997                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1579312997                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     16832000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4807500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    733172000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3265436497                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4020247997                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     16832000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4807500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    733172000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3265436497                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4020247997                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24069                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2641                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        26710                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks        95329                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total        95329                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28987                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        28987                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23310                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23310                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        49948                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        49948                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       838149                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       838149                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       147233                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       147233                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24069                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2641                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       838149                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       197181                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1062040                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24069                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2641                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       838149                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       197181                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1062040                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.036091                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.955980                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.955980                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.966366                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.966366                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.644450                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.644450                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.015671                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.015671                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.448188                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.448188                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.015671                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.497903                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.105717                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.015671                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.497903                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.105717                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22447.614108                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19673.396846                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19673.396846                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21310.263695                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21310.263695                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52381.978316                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52381.978316                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55818.195660                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55818.195660                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23933.336319                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23933.336319                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55818.195660                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33260.707671                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 35806.833134                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55818.195660                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33260.707671                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35806.833134                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           54                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           27                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        25088                       # number of writebacks
system.cpu1.l2cache.writebacks::total           25088                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          258                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          258                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           13                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           45                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           45                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           13                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          303                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          316                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           13                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          303                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          316                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          724                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          240                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          964                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         1571                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total         1571                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        18681                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        18681                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        27711                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27711                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22526                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22526                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31931                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        31931                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        13122                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        13122                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        65943                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        65943                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          724                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          240                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        13122                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        97874                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       111960                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          724                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          240                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        13122                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        97874                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        18681                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       130641                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2845                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         2957                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2191                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2191                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5036                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5148                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     15855500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1045426686                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1045426686                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    554064000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    554064000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    417044500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    417044500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1323500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1323500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1465371000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1465371000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    653754000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    653754000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1181307497                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1181307497                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    653754000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2646678497                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3316287997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    653754000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2646678497                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1045426686                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4361714683                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14231000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    333495000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    347726000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    208256000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    208256000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14231000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    541751000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    555982000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.036091                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.955980                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.955980                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.966366                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.966366                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639285                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639285                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.015656                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.447882                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.447882                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.496366                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.105420                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.496366                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.123009                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      2085429                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1050114                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18070                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       105283                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       105064                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          219                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         32952                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1055933                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2191                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2191                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       125445                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       933113                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        22957                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        71384                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41419                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84915                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            7                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57410                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        54585                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       838149                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       236592                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           39                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2498025                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       734861                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6388                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50317                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3289591                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     53648704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     21442516                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10564                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        96276                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          75198060                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     344587                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2379730                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.062577                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.242581                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           2231032     93.75%     93.75% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            148479      6.24%     99.99% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               219      0.01%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2379730                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1153078495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79714518                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1257481819                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    326951344                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3747000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     26275944                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180868                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483990                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40103000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186411762                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36433                       # number of replacements
system.iocache.tags.tagsinuse               14.472862                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         271656669000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.472862                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904554                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904554                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31866877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31866877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4715834885                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4715834885                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31866877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31866877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31866877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31866877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 131139.411523                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131139.411523                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131139.411523                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131139.411523                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131139.411523                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            14                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     3.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19716877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19716877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2904634885                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2904634885                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     19716877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     19716877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     19716877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     19716877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81139.411523                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81139.411523                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   133318                       # number of replacements
system.l2c.tags.tagsinuse                64014.997062                       # Cycle average of tags in use
system.l2c.tags.total_refs                     446453                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   198047                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.254278                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12007.955719                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    82.059666                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.029625                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     9722.429733                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3069.037039                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     9.516745                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1816.838650                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      555.114204                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2192.374249                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.183227                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001252                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.148353                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.046830                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.527338                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000145                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.027723                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008470                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.033453                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.976791                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        30866                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        33781                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           78                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5648                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        25140                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           81                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          325                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2821                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30623                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.470978                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001251                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.515457                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5802831                       # Number of tag accesses
system.l2c.tags.data_accesses                 5802831                       # Number of data accesses
system.l2c.Writeback_hits::writebacks          230256                       # number of Writeback hits
system.l2c.Writeback_hits::total               230256                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3083                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             464                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3547                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           148                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           197                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               345                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4599                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1379                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5978                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          467                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           86                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        52086                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        51828                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        50532                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           70                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           13                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        10095                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         4893                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3282                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           173352                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           467                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            86                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               52086                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56427                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        50532                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            70                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            13                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               10095                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6272                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3282                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  179330                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          467                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           86                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              52086                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56427                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        50532                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           70                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           13                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              10095                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6272                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3282                       # number of overall hits
system.l2c.overall_hits::total                 179330                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9481                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2162                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11643                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          497                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1197                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1694                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11009                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7938                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              18947                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          137                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        22412                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9738                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133466                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           16                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3021                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1593                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5720                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         176104                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          137                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22412                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20747                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133466                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3021                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9531                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5720                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195051                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          137                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22412                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20747                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133466                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3021                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9531                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5720                       # number of overall misses
system.l2c.overall_misses::total               195051                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     34581000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5348500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     39929500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3790500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2694500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      6485000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1642305000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1048460500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2690765500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     19306500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       133000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2926929000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1335340500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  20225428758                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      2276000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    405795500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    223263000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    972266423                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  26110738681                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     19306500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2926929000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2977645500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  20225428758                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      2276000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    405795500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1271723500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    972266423                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     28801504181                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     19306500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2926929000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2977645500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  20225428758                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      2276000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    405795500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1271723500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    972266423                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    28801504181                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks       230256                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           230256                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        12564                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2626                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           15190                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          645                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1394                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2039                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15608                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9317                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24925                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          604                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           87                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        74498                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61566                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       183998                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           86                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        13116                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         6486                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         9002                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       349456                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          604                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           87                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           74498                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           77174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       183998                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           86                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           13                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           13116                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           15803                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         9002                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              374381                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          604                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           87                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          74498                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          77174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       183998                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           86                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           13                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          13116                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          15803                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         9002                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             374381                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.754616                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.823305                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.766491                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.770543                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.858680                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.830799                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.705343                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.851991                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.760160                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.300840                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.158172                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.186047                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.230329                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.245606                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.503938                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.300840                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.268834                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.186047                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.230329                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.603113                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.520996                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.300840                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.268834                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.186047                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.230329                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.603113                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.520996                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3647.400063                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2473.866790                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3429.485528                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7626.760563                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2251.044277                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3828.217237                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149178.399491                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132081.191736                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 142015.385021                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140923.357664                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130596.510798                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137126.771411                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       142250                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134324.892420                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140152.542373                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 148268.856363                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140923.357664                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130596.510798                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 143521.738083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       142250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134324.892420                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 133430.227678                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 147661.402305                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140923.357664                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130596.510798                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 143521.738083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       142250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134324.892420                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 133430.227678                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 147661.402305                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               687                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           229                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102021                       # number of writebacks
system.l2c.writebacks::total                   102021                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           13                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3105                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3105                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9481                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2162                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11643                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          497                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1197                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1694                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11009                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7938                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         18947                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          137                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22406                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9737                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133466                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3015                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1593                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5720                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       176091                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          137                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22406                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20746                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133466                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3015                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9531                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5720                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195038                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          137                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22406                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20746                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133466                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3015                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9531                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5720                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195038                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3915                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32040                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         2841                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38908                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28722                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2191                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30913                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3915                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60762                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5032                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69821                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    714754501                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    161986000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    876740501                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     38415000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     91799500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    130214500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1532215000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    969080500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2501295500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     17936500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       123000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2702366000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1237877500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18890768758                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      2116000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    375139500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    207333000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    915066423                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  24348726681                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     17936500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2702366000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2770092500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18890768758                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2116000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    375139500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1176413500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    915066423                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  26850022181                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     17936500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2702366000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2770092500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18890768758                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2116000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    375139500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1176413500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    915066423                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  26850022181                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443682000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5515186000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11878500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    282299000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6253045500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4452219000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    171006500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4623225500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443682000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9967405000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11878500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    453305500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10876271000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.754616                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.823305                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.766491                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.770543                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.858680                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.830799                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.705343                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.851991                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.760160                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158155                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.245606                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.503900                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.268821                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.603113                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.520961                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.268821                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.603113                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.520961                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75388.092079                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 74924.144311                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75301.941166                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77293.762575                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76691.311612                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76868.063754                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139178.399491                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122081.191736                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 132015.385021                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 137665.594300                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 137665.594300                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               38908                       # Transaction distribution
system.membus.trans_dist::ReadResp             215242                       # Transaction distribution
system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
system.membus.trans_dist::Writeback            138211                       # Transaction distribution
system.membus.trans_dist::CleanEvict            17281                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            73717                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40307                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13440                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39445                       # Transaction distribution
system.membus.trans_dist::ReadExResp            18844                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        176334                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13712                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       674810                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       796498                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108909                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108909                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 905407                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27424                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19258908                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19450490                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21767610                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           121785                       # Total snoops (count)
system.membus.snoop_fanout::samples            591590                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  591590    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              591590                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91392000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11844500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1004304747                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1168943229                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64602498                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       982687                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       493902                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       158313                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          22110                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        21385                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          725                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              38912                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            507516                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           368484                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          106099                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           77161                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40652                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         117813                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           21                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51062                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51062                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       468619                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1216476                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       257070                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1473546                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35115318                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4064004                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39179322                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          452154                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1258731                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.293892                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.456806                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 889525     70.67%     70.67% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 368481     29.27%     99.94% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    725      0.06%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1258731                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          836264644                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           342619                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         685711951                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         211221475                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------