path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.843655                       # Number of seconds simulated
sim_ticks                                2843654861000                       # Number of ticks simulated
final_tick                               2843654861000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 157498                       # Simulator instruction rate (inst/s)
host_op_rate                                   190690                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3581426538                       # Simulator tick rate (ticks/s)
host_mem_usage                                 613612                       # Number of bytes of host memory used
host_seconds                                   794.00                       # Real time elapsed on the host
sim_insts                                   125053138                       # Number of instructions simulated
sim_ops                                     151407658                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         9664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1363068                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     10771008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           534304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1165248                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13845276                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       418688                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        26560                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          445248                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7176128                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst            40                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9512208                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          151                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             21823                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       168297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              8372                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        18207                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                216881                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          112127                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               152787                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3398                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              479337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3787734                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              187893                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       409771                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4868831                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         147236                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst           9340                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             156576                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2523558                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst               6226                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          815266                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3345064                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2523558                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3398                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             485562                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3787734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          338                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             187907                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       409771                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          815604                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                8213896                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        216881                       # Number of read requests accepted
system.physmem.writeReqs                       152787                       # Number of write requests accepted
system.physmem.readBursts                      216881                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     152787                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13864960                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     15424                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9526912                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  13845276                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9512208                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      241                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3914                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13516                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               13445                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13090                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14400                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13760                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15799                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12812                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13576                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13750                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13572                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13600                       # Per bank write bursts
system.physmem.perBankRdBursts::10              13300                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11904                       # Per bank write bursts
system.physmem.perBankRdBursts::12              13370                       # Per bank write bursts
system.physmem.perBankRdBursts::13              13720                       # Per bank write bursts
system.physmem.perBankRdBursts::14              13497                       # Per bank write bursts
system.physmem.perBankRdBursts::15              13045                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9322                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9428                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10143                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9576                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8974                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8900                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9376                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9386                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9384                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9431                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9355                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8834                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9379                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9206                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9289                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8875                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
system.physmem.totGap                    2843652584000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  216294                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148351                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     79253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     17902                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     10637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      9321                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      7490                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      6044                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      425                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      318                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      210                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      138                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     8095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    10430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92618                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      252.562223                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.207145                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.469960                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46921     50.66%     50.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18876     20.38%     71.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6855      7.40%     78.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3600      3.89%     82.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3008      3.25%     85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2120      2.29%     87.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1341      1.45%     89.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1115      1.20%     90.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8782      9.48%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92618                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7463                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.028407                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      529.473600                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7462     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7463                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7463                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.946134                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.603737                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.129560                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6171     82.69%     82.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             489      6.55%     89.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              84      1.13%     90.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             205      2.75%     93.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             200      2.68%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              17      0.23%     96.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              17      0.23%     96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              12      0.16%     96.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              25      0.33%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.08%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.08%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               3      0.04%     96.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             165      2.21%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.09%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.08%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              18      0.24%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               7      0.09%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.04%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.11%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7463                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7683149500                       # Total ticks spent queuing
system.physmem.totMemAccLat               11745149500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1083200000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       35465.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  54215.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.88                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.35                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     183194                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89685                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.56                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  60.24                       # Row buffer hit rate for writes
system.physmem.avgGap                      7692449.94                       # Average gap between requests
system.physmem.pageHitRate                      74.66                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2709796310750                       # Time in different power states
system.physmem.memoryStateTime::REF       94955640000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       38900516750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 358956360                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 341235720                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 195859125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 186190125                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                862929600                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                826854600                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               486680400                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               477919440                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          185733231840                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          185733231840                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           81937929780                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           81435296655                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1634313275250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1634754181500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1903888862355                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1903754909880                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.523453                       # Core power per rank (mW)
system.physmem.averagePower::1             669.476347                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          158                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              428                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          158                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          428                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          158                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             428                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               34892527                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17126488                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1674515                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20008950                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               14462185                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.278580                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               10813099                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            822816                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23969265                       # DTB read hits
system.cpu0.dtb.read_misses                     62663                       # DTB read misses
system.cpu0.dtb.write_hits                   17948332                       # DTB write hits
system.cpu0.dtb.write_misses                     6711                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3475                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1396                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1982                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      568                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24031928                       # DTB read accesses
system.cpu0.dtb.write_accesses               17955043                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         41917597                       # DTB hits
system.cpu0.dtb.misses                          69374                       # DTB misses
system.cpu0.dtb.accesses                     41986971                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    70358748                       # ITB inst hits
system.cpu0.itb.inst_misses                      3854                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2220                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7388                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                70362602                       # ITB inst accesses
system.cpu0.itb.hits                         70358748                       # DTB hits
system.cpu0.itb.misses                           3854                       # DTB misses
system.cpu0.itb.accesses                     70362602                       # DTB accesses
system.cpu0.numCycles                       229119066                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  109189984                       # Number of instructions committed
system.cpu0.committedOps                    132016369                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8791665                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1828                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5458204948                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.098352                       # CPI: cycles per instruction
system.cpu0.ipc                              0.476564                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1830                       # number of quiesce instructions executed
system.cpu0.tickCycles                      193229301                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       35889765                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           714801                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          493.827802                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           40473769                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           715313                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            56.581901                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        306537500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.inst   493.827802                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.964507                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.964507                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         83782876                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        83782876                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.inst     22802755                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22802755                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.inst     16862558                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16862558                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       381551                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       381551                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       362630                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       362630                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.inst     39665313                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        39665313                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.inst     39665313                       # number of overall hits
system.cpu0.dcache.overall_hits::total       39665313                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.inst       537301                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       537301                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.inst       532764                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       532764                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6412                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         6412                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        20204                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20204                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.inst      1070065                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1070065                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.inst      1070065                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1070065                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6609674711                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6609674711                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8019150247                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8019150247                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    105707749                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    105707749                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    437634051                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    437634051                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       129000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       129000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.inst  14628824958                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14628824958                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.inst  14628824958                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14628824958                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23340056                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23340056                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17395322                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17395322                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       387963                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387963                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       382834                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       382834                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.inst     40735378                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     40735378                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.inst     40735378                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     40735378                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023021                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.023021                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030627                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.030627                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016527                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016527                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.052775                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052775                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026269                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026269                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026269                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.026269                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       517954                       # number of writebacks
system.cpu0.dcache.writebacks::total           517954                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        42678                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        42678                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       230706                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       230706                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst            1                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.inst       273384                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       273384                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.inst       273384                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       273384                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       494623                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       494623                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       302058                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       302058                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6411                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6411                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        20204                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20204                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.inst       796681                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       796681                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.inst       796681                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       796681                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5117531439                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5117531439                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4270825900                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4270825900                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     92832750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     92832750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    396783949                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    396783949                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       121000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       121000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9388357339                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9388357339                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9388357339                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9388357339                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6191310497                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6191310497                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4803760492                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4803760492                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  10995070989                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10995070989                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021192                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021192                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017364                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017364                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016525                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016525                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.052775                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052775                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019557                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.019557                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019557                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.019557                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1983566                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.796833                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           68366923                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1984078                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.457780                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6227191000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.796833                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999603                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999603                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        142686127                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       142686127                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     68366923                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       68366923                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     68366923                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        68366923                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     68366923                       # number of overall hits
system.cpu0.icache.overall_hits::total       68366923                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1984094                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1984094                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1984094                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1984094                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1984094                       # number of overall misses
system.cpu0.icache.overall_misses::total      1984094                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16546799645                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  16546799645                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  16546799645                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  16546799645                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  16546799645                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  16546799645                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     70351017                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     70351017                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     70351017                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     70351017                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     70351017                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     70351017                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028203                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028203                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028203                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028203                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028203                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028203                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8339.725661                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8339.725661                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8339.725661                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8339.725661                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8339.725661                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8339.725661                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1984094                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1984094                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1984094                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1984094                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1984094                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1984094                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13568682853                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  13568682853                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13568682853                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  13568682853                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13568682853                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  13568682853                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    276787500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    276787500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    276787500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    276787500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028203                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028203                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028203                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6838.729845                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  6838.729845                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  6838.729845                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     17337039                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       425762                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     16383461                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9078                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         6456                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       512279                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      1329409                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          409357                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16202.462840                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3013500                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          425611                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.080409                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4205.324174                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    51.364575                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.062072                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2198.474976                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9747.237044                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.256673                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003135                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.134184                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.594924                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.988920                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8963                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7281                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           54                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          134                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2805                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5150                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          820                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3125                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3482                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          341                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.547058                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.444397                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        55309059                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       55309059                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77781                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4268                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2390782                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2472831                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       517951                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       517951                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4630                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         4630                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         2244                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2244                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       223140                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       223140                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77781                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4268                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      2613922                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2695971                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77781                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4268                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      2613922                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2695971                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          986                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          173                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        94341                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        95500                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        27941                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        27941                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        17958                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        17958                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        46352                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        46352                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          986                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          173                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       140693                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       141852                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          986                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          173                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       140693                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       141852                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     32261749                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3849999                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2894443882                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   2930555630                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    497270548                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    497270548                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    354837739                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    354837739                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       117000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       117000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   1925679719                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1925679719                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     32261749                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3849999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4820123601                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   4856235349                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     32261749                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3849999                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4820123601                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   4856235349                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78767                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4441                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2485123                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2568331                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       517951                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       517951                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        32571                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        32571                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        20202                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20202                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       269492                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269492                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78767                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4441                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2754615                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2837823                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78767                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4441                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2754615                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2837823                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.037962                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.037184                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.857849                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.857849                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.888922                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.888922                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.171998                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171998                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.051075                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.049986                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.051075                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.049986                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst        58500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total        58500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        25463                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs             375                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    67.901333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       214094                       # number of writebacks
system.cpu0.l2cache.writebacks::total          214094                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         7763                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         7763                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3115                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3115                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        10878                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        10878                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        10878                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        10878                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          986                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          173                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        86578                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        87737                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       512278                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       512278                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        27941                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27941                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        17958                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17958                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        43237                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43237                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          986                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          173                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       129815                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       130974                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          986                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          173                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       129815                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       512278                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       643252                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2638999                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2121502252                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2149486002                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21334624793                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21334624793                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    476101816                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    476101816                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    237455029                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    237455029                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst        89000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        89000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1189409987                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1189409987                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2638999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3310912239                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3338895989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2638999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3310912239                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21334624793                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  24673520782                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6176243748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6176243748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4587514507                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4587514507                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10763758255                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10763758255                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.034839                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.034161                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.857849                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.857849                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.888922                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.888922                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.160439                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.160439                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.047126                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.046153                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.047126                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226671                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst        44500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total        44500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2765429                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2670282                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28813                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28813                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       517951                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       696439                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        70465                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42615                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp        93717                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       291656                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       282057                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3974309                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2393187                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11845                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       168040                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6547381                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    127177856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86874167                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17764                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       315068                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         214384855                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1083965                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4385734                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.219720                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.414057                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           3422100     78.03%     78.03% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            963634     21.97%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4385734                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2275890990                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    119346000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2982392646                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1235371968                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7407493                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     89292476                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                4040174                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2339682                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           248924                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2652147                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1629183                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            61.428835                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 794888                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             55483                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4061400                       # DTB read hits
system.cpu1.dtb.read_misses                     20326                       # DTB read misses
system.cpu1.dtb.write_hits                    3327397                       # DTB write hits
system.cpu1.dtb.write_misses                     1493                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2042                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      130                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   315                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      275                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4081726                       # DTB read accesses
system.cpu1.dtb.write_accesses                3328890                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7388797                       # DTB hits
system.cpu1.dtb.misses                          21819                       # DTB misses
system.cpu1.dtb.accesses                      7410616                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7665717                       # ITB inst hits
system.cpu1.itb.inst_misses                      2240                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1155                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1927                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7667957                       # ITB inst accesses
system.cpu1.itb.hits                          7665717                       # DTB hits
system.cpu1.itb.misses                           2240                       # DTB misses
system.cpu1.itb.accesses                      7667957                       # DTB accesses
system.cpu1.numCycles                        40520229                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   15863154                       # Number of instructions committed
system.cpu1.committedOps                     19391289                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1555006                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2808                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5646190749                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.554361                       # CPI: cycles per instruction
system.cpu1.ipc                              0.391487                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2810                       # number of quiesce instructions executed
system.cpu1.tickCycles                       29462484                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       11057745                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           188500                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          474.724355                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6998456                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           188865                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.055336                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     107393225500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.inst   474.724355                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.927196                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.927196                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         14854828                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        14854828                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.inst      3752021                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3752021                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.inst      3051608                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3051608                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        88860                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        88860                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        69213                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        69213                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.inst      6803629                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6803629                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.inst      6803629                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6803629                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.inst       182037                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       182037                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.inst       139457                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       139457                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5164                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5164                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        23160                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23160                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.inst       321494                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        321494                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.inst       321494                       # number of overall misses
system.cpu1.dcache.overall_misses::total       321494                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2747896424                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2747896424                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3339347493                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3339347493                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     93721501                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     93721501                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    540094758                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    540094758                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       317500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       317500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.inst   6087243917                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6087243917                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.inst   6087243917                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6087243917                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3934058                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3934058                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.inst      3191065                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3191065                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        94024                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        94024                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        92373                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92373                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.inst      7125123                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7125123                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.inst      7125123                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7125123                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.046272                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.046272                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043702                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.043702                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.054922                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054922                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.250723                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250723                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.045121                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.045121                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.045121                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.045121                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       115754                       # number of writebacks
system.cpu1.dcache.writebacks::total           115754                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        15456                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        15456                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        49471                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        49471                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.inst        64927                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        64927                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.inst        64927                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        64927                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       166581                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       166581                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        89986                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        89986                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5164                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5164                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        23160                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23160                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.inst       256567                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       256567                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.inst       256567                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       256567                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2204876516                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2204876516                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   1996537354                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1996537354                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     83385499                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83385499                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    492548242                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    492548242                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       303500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       303500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   4201413870                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4201413870                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   4201413870                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4201413870                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    329634997                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    329634997                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    202961999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    202961999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    532596996                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    532596996                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042343                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042343                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.028199                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028199                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.054922                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054922                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.250723                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250723                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.036009                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.036009                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.036009                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.036009                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           893030                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.459009                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6770083                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           893542                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.576681                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      71221486500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.459009                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975506                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975506                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           48                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         16220792                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        16220792                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      6770083                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6770083                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6770083                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6770083                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6770083                       # number of overall hits
system.cpu1.icache.overall_hits::total        6770083                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       893542                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       893542                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       893542                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        893542                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       893542                       # number of overall misses
system.cpu1.icache.overall_misses::total       893542                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7266670468                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7266670468                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7266670468                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7266670468                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7266670468                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7266670468                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7663625                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7663625                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7663625                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7663625                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7663625                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7663625                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.116595                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.116595                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.116595                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.116595                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.116595                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.116595                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8132.433023                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8132.433023                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8132.433023                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8132.433023                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8132.433023                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8132.433023                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       893542                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       893542                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       893542                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       893542                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       893542                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       893542                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5923954530                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5923954530                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5923954530                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5923954530                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5923954530                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5923954530                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10589750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10589750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10589750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10589750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.116595                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.116595                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.116595                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6629.743795                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6629.743795                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6629.743795                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      7064659                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        40510                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      6914419                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         1409                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2627                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       105694                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       724613                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           80002                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15534.005683                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1138706                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           95380                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           11.938624                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6881.050205                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    26.485106                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.098583                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2338.762949                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6287.608842                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.419986                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001617                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.142747                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.383765                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.948120                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022        10071                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           34                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5273                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          132                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         6676                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         3263                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          237                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3167                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1869                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.614685                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002075                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.321838                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        21370209                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       21370209                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        22701                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2439                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       993088                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1018228                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       115754                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       115754                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1810                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1810                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst          740                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          740                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.inst        27796                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27796                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        22701                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2439                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1020884                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1046024                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        22701                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2439                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1020884                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1046024                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          604                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          243                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        72199                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        73046                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst        28140                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28140                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst        22420                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22420                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.inst        32240                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32240                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          604                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          243                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       104439                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       105286                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          604                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          243                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       104439                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       105286                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     13239000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4899500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   1623706138                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1641844638                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst    531483393                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    531483393                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst    440502566                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    440502566                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst       296000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       296000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   1126750383                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1126750383                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     13239000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4899500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   2750456521                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   2768595021                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     13239000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4899500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   2750456521                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   2768595021                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        23305                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2682                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      1065287                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1091274                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       115754                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       115754                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        29950                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29950                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        23160                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23160                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst        60036                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        60036                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        23305                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2682                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1125323                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1151310                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        23305                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2682                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1125323                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1151310                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.025917                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.090604                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.067774                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.066936                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.939566                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.939566                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.968048                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.968048                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.537011                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.537011                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.025917                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.090604                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.092808                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.091449                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.025917                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.090604                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.092808                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.091449                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         4629                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             159                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    29.113208                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        38442                       # number of writebacks
system.cpu1.l2cache.writebacks::total           38442                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1604                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total         1604                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          322                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          322                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1926                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         1926                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1926                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         1926                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          604                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          243                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        70595                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        71442                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       105694                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       105694                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        28140                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28140                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22420                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22420                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        31918                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        31918                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          604                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          243                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       102513                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       103360                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          604                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          243                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       102513                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       105694                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       209054                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   1098179235                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1110385737                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2958247424                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   2958247424                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    404415795                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    404415795                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    308218727                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308218727                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst       247000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       247000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst    862164082                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    862164082                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1960343317                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   1972549819                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1960343317                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2958247424                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4930797243                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    316625253                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    316625253                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    186937501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    186937501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    503562754                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    503562754                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.066269                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.065467                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.939566                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.939566                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.968048                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.968048                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.531648                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.531648                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.091097                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.089776                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.091097                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.181579                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1582615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1137834                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2120                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2120                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       115754                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       151048                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        84372                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41116                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85179                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        76804                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        64396                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1787314                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       769072                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6988                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        51360                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2614734                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     57194048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24925415                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        93220                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          82223411                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     838592                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2085067                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.363773                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.481085                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1326575     63.62%     63.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            758492     36.38%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2085067                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     782771935                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     78513000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1341710719                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    381436893                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4307996                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     28057498                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59407                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           33                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484026                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326658321                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36824131                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36417                       # number of replacements
system.iocache.tags.tagsinuse                0.992159                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36433                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         268855800000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.992159                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062010                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062010                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328467                       # Number of tag accesses
system.iocache.tags.data_accesses              328467                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           33                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           33                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31254127                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31254127                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31254127                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31254127                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31254127                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31254127                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128617.806584                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128617.806584                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128617.806584                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128617.806584                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128617.806584                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18617627                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18617627                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2261621825                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2261621825                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18617627                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18617627                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18617627                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18617627                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76615.748971                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76615.748971                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   151810                       # number of replacements
system.l2c.tags.tagsinuse                64480.586594                       # Cycle average of tags in use
system.l2c.tags.total_refs                     529933                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   216565                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.446993                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12374.174406                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    81.831156                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030524                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3874.361594                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.891665                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      757.615436                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4654.298093                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.188815                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001249                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.059118                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.651968                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000166                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.011560                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.071019                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.983896                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        46322                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        18386                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         6596                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        39440                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           47                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          273                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2604                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        15495                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.706818                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000717                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.280548                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6644341                       # Number of tag accesses
system.l2c.tags.data_accesses                 6644341                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          563                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          116                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              36701                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       207577                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          129                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           56                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              11433                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        45418                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 301993                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          252536                       # number of Writeback hits
system.l2c.Writeback_hits::total               252536                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.inst           11942                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.inst             830                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               12772                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.inst           205                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.inst           179                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               384                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.inst             3525                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.inst             1107                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 4632                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           563                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           116                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               40226                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       207577                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           129                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            56                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               12540                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        45418                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  306625                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          563                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          116                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              40226                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       207577                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          129                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           56                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              12540                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        45418                       # number of overall hits
system.l2c.overall_hits::total                 306625                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          151                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            11286                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       168297                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1852                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        18208                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               199810                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.inst          9028                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.inst          2665                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11693                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.inst          461                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.inst         1254                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1715                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.inst           7011                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.inst           6410                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              13421                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          151                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             18297                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       168297                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              8262                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        18208                       # number of demand (read+write) misses
system.l2c.demand_misses::total                213231                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          151                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            18297                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       168297                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             8262                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        18208                       # number of overall misses
system.l2c.overall_misses::total               213231                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     11975000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    955847998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  18133044658                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1150500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    151717498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2022789954                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    21276600608                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.inst     10528075                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.inst      2736385                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     13264460                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.inst      1131453                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.inst      1006958                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2138411                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.inst    592519659                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.inst    475914481                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1068434140                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     11975000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1548367657                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  18133044658                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1150500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    627631979                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2022789954                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22345034748                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     11975000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1548367657                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  18133044658                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1150500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    627631979                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2022789954                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22345034748                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          714                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          117                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          47987                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       375874                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          144                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           56                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          13285                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        63626                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             501803                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       252536                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           252536                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.inst        20970                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.inst         3495                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           24465                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.inst          666                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.inst         1433                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2099                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.inst        10536                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.inst         7517                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            18053                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          714                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          117                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           58523                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       375874                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          144                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           56                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           20802                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        63626                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              519856                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          714                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          117                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          58523                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       375874                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          144                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           56                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          20802                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        63626                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             519856                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.211485                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.008547                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.235189                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.104167                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.139405                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.286172                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.398184                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.430520                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.762518                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.477948                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.692192                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.875087                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.817056                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.inst     0.665433                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.inst     0.852734                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.743422                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.211485                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.008547                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.312646                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.104167                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.397173                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.286172                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.410173                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.211485                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.008547                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.312646                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.104167                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.397173                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.286172                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.410173                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76700                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 106484.162995                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1166.158064                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  1026.786116                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1134.393227                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  2454.344902                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   802.996810                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1246.886880                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 79609.130467                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        76700                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 104792.618090                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        76700                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 104792.618090                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               845                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       26                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     32.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              112127                       # number of writebacks
system.l2c.writebacks::total                   112127                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          151                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        11286                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       168297                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1852                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        18207                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          199809                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.inst         9028                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2665                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11693                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          461                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1254                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1715                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.inst         7011                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.inst         6410                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         13421                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          151                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        18297                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       168297                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         8262                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        18207                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           213230                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          151                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        18297                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       168297                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         8262                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        18207                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          213230                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10113000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    815475498                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16060717158                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       965000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    128728998                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1800475704                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  18816537858                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     91196953                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     26828647                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    118025600                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      4664957                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     12607247                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     17272204                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst    505062337                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst    394979019                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    900041356                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10113000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1320537835                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  16060717158                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       965000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    523708017                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1800475704                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  19716579214                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10113000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1320537835                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16060717158                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       965000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    523708017                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1800475704                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  19716579214                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5518590247                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    263108750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5781698997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4096001500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    150494000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4246495500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   9614591747                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    413602750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10028194497                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.235189                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.104167                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.139405                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286157                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.398182                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.430520                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.762518                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.477948                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.692192                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.875087                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.817056                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.665433                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.852734                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.743422                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.312646                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.104167                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.397173                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286157                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.410171                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.312646                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.104167                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.397173                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286157                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.410171                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 92466.253407                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 92466.253407                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              238091                       # Transaction distribution
system.membus.trans_dist::ReadResp             238091                       # Transaction distribution
system.membus.trans_dist::WriteReq              30933                       # Transaction distribution
system.membus.trans_dist::WriteResp             30933                       # Transaction distribution
system.membus.trans_dist::Writeback            112127                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            79652                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          39985                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13516                       # Transaction distribution
system.membus.trans_dist::ReadExReq             30363                       # Transaction distribution
system.membus.trans_dist::ReadExResp            13313                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       704934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       826518                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72706                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72706                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 899224                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21038188                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     21229406                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23548702                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123399                       # Total snoops (count)
system.membus.snoop_fanout::samples            498406                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  498406    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              498406                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87864494                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11666999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1620379248                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2120601580                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38542869                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             668340                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            668325                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30933                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30933                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           252536                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           92316                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40369                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         132685                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            38932                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           38932                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1370044                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       368770                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1738814                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     41959415                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7901735                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               49861150                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          291964                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1090717                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.033437                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.179774                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1054247     96.66%     96.66% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36470      3.34%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1090717                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1589301055                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1026000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2361799867                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         804005619                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------