path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.846034                       # Number of seconds simulated
sim_ticks                                2846033690500                       # Number of ticks simulated
final_tick                               2846033690500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 166502                       # Simulator instruction rate (inst/s)
host_op_rate                                   201645                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3701777010                       # Simulator tick rate (ticks/s)
host_mem_usage                                 652712                       # Number of bytes of host memory used
host_seconds                                   768.83                       # Real time elapsed on the host
sim_insts                                   128011279                       # Number of instructions simulated
sim_ops                                     155030352                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1665600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1328952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8468032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           219456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           635604                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       399104                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12726924                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1665600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       219456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1885056                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8843968                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8861532                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          131                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26025                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21289                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       132313                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3429                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9952                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6236                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199403                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138187                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142578                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2946                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              585236                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              466949                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2975380                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               77109                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              223330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       140232                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4471811                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         585236                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          77109                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             662345                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3107471                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3113643                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3107471                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2946                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             585236                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             473106                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2975380                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              77109                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             223344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       140232                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7585453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199403                       # Number of read requests accepted
system.physmem.writeReqs                       178802                       # Number of write requests accepted
system.physmem.readBursts                      199403                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     178802                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12754816                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9923392                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12726924                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11179868                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23728                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14293                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12446                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12462                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12648                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12635                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15144                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12384                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13114                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13234                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12297                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12473                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12152                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11219                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11569                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12199                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11629                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11689                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9980                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10101                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10187                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9953                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9212                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9585                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10195                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10328                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9559                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9737                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9778                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9524                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9387                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9312                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9249                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8966                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          44                       # Number of times write queue was full causing retry
system.physmem.totGap                    2846033184500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  198820                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 174411                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     98514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     48367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7788                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6331                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5269                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4641                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3767                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       751                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      262                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      163                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7029                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1415                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       62                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        91619                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      247.526648                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     138.939609                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     308.892335                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          48258     52.67%     52.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17913     19.55%     72.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6311      6.89%     79.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3675      4.01%     83.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2817      3.07%     86.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1472      1.61%     87.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1018      1.11%     88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1004      1.10%     90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9151      9.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          91619                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6524                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.547670                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      556.789065                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6523     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6524                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6524                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.766554                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.625948                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       41.024429                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            6179     94.71%     94.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              85      1.30%     96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              25      0.38%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              12      0.18%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              31      0.48%     97.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             34      0.52%     97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            24      0.37%     97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            11      0.17%     98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            15      0.23%     98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             5      0.08%     98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            12      0.18%     98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            17      0.26%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            13      0.20%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             5      0.08%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             4      0.06%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             3      0.05%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             4      0.06%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             2      0.03%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             4      0.06%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             3      0.05%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             3      0.05%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            16      0.25%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             3      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             2      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             4      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-655             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::880-895             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6524                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5653495532                       # Total ticks spent queuing
system.physmem.totMemAccLat                9390258032                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    996470000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28367.62                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47117.62                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.49                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.06                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165654                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97073                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.60                       # Row buffer hit rate for writes
system.physmem.avgGap                      7525107.24                       # Average gap between requests
system.physmem.pageHitRate                      74.14                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  361662840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  197335875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 811722600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                515425680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185888851200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83071861560                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634748153750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905595013505                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.562437                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719423686494                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95035200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31571473506                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  330976800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  180592500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 742762800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                489317760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185888851200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82401250860                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635336408750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905370160670                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.483431                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720410023695                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95035200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30588353805                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               20699653                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13612367                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1051860                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            13249801                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                9339959                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            70.491315                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3411685                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            215338                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    70748                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               70748                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47364                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23384                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        70748                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          70748    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        70748                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6854                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  9215.640648                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  8072.361115                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6078.265155                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6652     97.05%     97.05% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          190      2.77%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            4      0.06%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            6      0.09%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6854                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      328505000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5278     77.01%     77.01% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1576     22.99%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6854                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        70748                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        70748                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6854                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6854                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        77602                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17365788                       # DTB read hits
system.cpu0.dtb.read_misses                     64419                       # DTB read misses
system.cpu0.dtb.write_hits                   14563883                       # DTB write hits
system.cpu0.dtb.write_misses                     6329                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3519                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1310                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1951                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      572                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17430207                       # DTB read accesses
system.cpu0.dtb.write_accesses               14570212                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31929671                       # DTB hits
system.cpu0.dtb.misses                          70748                       # DTB misses
system.cpu0.dtb.accesses                     32000419                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3844                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3844                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3537                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3844                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3844    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3844                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2412                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  9287.312604                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  8105.691907                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5199.777734                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          996     41.29%     41.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1373     56.92%     98.22% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575            5      0.21%     98.42% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2412                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      328041000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2112     87.56%     87.56% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          300     12.44%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2412                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3844                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3844                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2412                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2412                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6256                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    38673096                       # ITB inst hits
system.cpu0.itb.inst_misses                      3844                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2215                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7305                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                38676940                       # ITB inst accesses
system.cpu0.itb.hits                         38673096                       # DTB hits
system.cpu0.itb.misses                           3844                       # DTB misses
system.cpu0.itb.accesses                     38676940                       # DTB accesses
system.cpu0.numCycles                       164345884                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   79729346                       # Number of instructions committed
system.cpu0.committedOps                     95953153                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      5189304                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1865                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5527748141                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.061297                       # CPI: cycles per instruction
system.cpu0.ipc                              0.485131                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1866                       # number of quiesce instructions executed
system.cpu0.tickCycles                      127709647                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       36636237                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           716917                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.984031                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           30425669                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           717429                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            42.409310                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        346166500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.984031                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978484                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.978484                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63847334                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63847334                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15827695                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15827695                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     13439418                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      13439418                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       321505                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       321505                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365521                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365521                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361496                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361496                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     29267113                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        29267113                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     29588618                       # number of overall hits
system.cpu0.dcache.overall_hits::total       29588618                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       465920                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       465920                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       577900                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       577900                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       136723                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       136723                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21141                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21141                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20265                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20265                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1043820                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1043820                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1180543                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1180543                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6144584831                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6144584831                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9172351028                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   9172351028                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    319190979                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    319190979                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    453656289                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    453656289                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       133500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       133500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  15316935859                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  15316935859                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  15316935859                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  15316935859                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16293615                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16293615                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     14017318                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     14017318                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       458228                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       458228                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386662                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386662                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381761                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381761                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30310933                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30310933                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30769161                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30769161                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028595                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.028595                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041228                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.041228                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.298373                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.298373                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054676                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054676                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053083                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053083                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034437                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.034437                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038368                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.038368                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13188.068404                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13188.068404                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15871.865423                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15871.865423                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15098.196821                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15098.196821                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22386.197335                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22386.197335                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14673.924488                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14673.924488                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12974.483656                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12974.483656                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       515635                       # number of writebacks
system.cpu0.dcache.writebacks::total           515635                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        72452                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        72452                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       253659                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       253659                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14673                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14673                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       326111                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       326111                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       326111                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       326111                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       393468                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       393468                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324241                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       324241                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       103543                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       103543                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6468                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6468                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20265                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20265                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       717709                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       717709                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       821252                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       821252                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20388                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19084                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39472                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4430984378                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4430984378                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4926577100                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4926577100                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1621170703                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1621170703                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96485758                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96485758                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    422555211                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    422555211                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       127500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       127500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9357561478                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9357561478                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10978732181                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10978732181                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4278812500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4278812500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3259105000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3259105000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7537917500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7537917500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024149                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024149                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023131                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023131                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225964                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225964                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016728                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016728                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053083                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053083                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023678                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023678                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026691                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026691                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11261.358936                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11261.358936                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15194.183031                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15194.183031                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15656.980221                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15656.980221                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14917.402288                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14917.402288                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20851.478460                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20851.478460                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13038.099673                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13038.099673                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13368.286690                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13368.286690                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209869.163233                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209869.163233                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170776.828757                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170776.828757                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190968.724666                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190968.724666                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1965366                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.785087                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36699580                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1965878                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            18.668290                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6403533250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785087                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999580                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999580                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         79296841                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        79296841                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     36699580                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36699580                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36699580                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36699580                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36699580                       # number of overall hits
system.cpu0.icache.overall_hits::total       36699580                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1965894                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1965894                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1965894                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1965894                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1965894                       # number of overall misses
system.cpu0.icache.overall_misses::total      1965894                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18549717200                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18549717200                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  18549717200                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18549717200                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  18549717200                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18549717200                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     38665474                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     38665474                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     38665474                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     38665474                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     38665474                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     38665474                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050844                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050844                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050844                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050844                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050844                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050844                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9435.766730                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9435.766730                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9435.766730                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9435.766730                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9435.766730                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9435.766730                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1965894                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1965894                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1965894                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1965894                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1965894                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1965894                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16574456804                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16574456804                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16574456804                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16574456804                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16574456804                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16574456804                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050844                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.050844                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.050844                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8431.002284                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8431.002284                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8431.002284                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8431.002284                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1838784                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1838936                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          132                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       233824                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          299625                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16147.057230                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2915503                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          315876                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.229897                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6737.365934                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    57.298987                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.096459                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5766.699762                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1949.490017                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1636.106070                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.411216                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003497                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.351971                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.118987                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.099860                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.985538                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1040                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15197                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          337                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          404                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          285                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4113                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7946                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2792                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.063477                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927551                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        55342545                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       55342545                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        81587                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3892                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1894938                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       403004                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2383421                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       515632                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       515632                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28611                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28611                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1830                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1830                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       223241                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       223241                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        81587                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3892                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1894938                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       626245                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2606662                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        81587                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3892                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1894938                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       626245                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2606662                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          835                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          121                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        70956                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       100469                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       172381                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26947                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26947                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18435                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18435                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        45449                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        45449                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          835                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          121                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        70956                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       145918                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       217830                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          835                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          121                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        70956                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       145918                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       217830                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     28533998                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2724498                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   3265841724                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   3007886164                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   6304986384                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    501041294                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    501041294                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    372688311                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    372688311                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       123500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       123500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2240726575                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2240726575                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     28533998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2724498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3265841724                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5248612739                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8545712959                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     28533998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2724498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3265841724                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5248612739                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8545712959                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        82422                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4013                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1965894                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       503473                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2555802                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       515632                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       515632                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55558                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55558                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20265                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20265                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268690                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       268690                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        82422                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4013                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1965894                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       772163                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2824492                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        82422                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4013                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1965894                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       772163                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2824492                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.036094                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.199552                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.067447                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.485025                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.485025                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.909697                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.909697                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169150                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169150                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.036094                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.188973                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.077122                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010131                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.030152                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.036094                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.188973                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.077122                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46026.294098                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29938.450308                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36575.877759                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18593.583479                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18593.583479                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20216.344508                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20216.344508                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49301.999494                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49301.999494                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46026.294098                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35969.604429                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39231.111229                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34172.452695                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22516.512397                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46026.294098                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35969.604429                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39231.111229                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           33                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           33                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       200378                       # number of writebacks
system.cpu0.l2cache.writebacks::total          200378                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           74                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          391                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          465                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3005                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3005                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           74                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3396                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3470                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           74                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3396                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3470                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          835                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          121                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        70882                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       100078                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       171916                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245909                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       245909                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26947                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26947                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18435                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18435                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42444                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        42444                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          835                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          121                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70882                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142522                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       214360                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          835                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          121                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70882                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142522                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245909                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       460269                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23755                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19084                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42839                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2794111276                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2333241113                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   5152380389                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14425244211                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14425244211                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    543842959                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    543842959                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    270479823                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    270479823                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data        97500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        97500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1625124729                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1625124729                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2794111276                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3958365842                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6777505118                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23091000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1937000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2794111276                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3958365842                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14425244211                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21202749329                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4115441500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4397586000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3115690500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3115690500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7231132000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7513276500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.198775                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.067265                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.485025                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.485025                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.909697                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.909697                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.157966                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.157966                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.184575                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075893                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010131                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.030152                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.036056                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.184575                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162956                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23314.226034                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29970.336612                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58660.903875                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20181.948232                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20181.948232                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14672.081530                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14672.081530                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38288.679884                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.679884                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27773.718037                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31617.396520                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39419.193533                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27773.718037                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46065.994731                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201856.067294                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185122.542623                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163261.920981                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163261.920981                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183196.493717                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175384.030906                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2719039                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2643816                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31019                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19084                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       515632                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       304029                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        89544                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42988                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112734                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       297842                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284446                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3938521                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2392407                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11394                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       176554                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6518876                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    126032640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86683880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        16052                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       329688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         213062260                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     679431                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4036359                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.164506                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.370735                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           3372352     83.55%     83.55% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2            664007     16.45%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4036359                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2262112239                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115872000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2959359198                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1234268849                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7386992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     94142746                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               19410315                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          6222605                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           754773                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            10046576                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                7244167                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            72.105830                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                8699318                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            540404                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    26225                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               26225                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19144                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7081                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        26225                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          26225    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        26225                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2726                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  9368.766324                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  8408.351420                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5475.622761                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1046     38.37%     38.37% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1544     56.64%     95.01% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           68      2.49%     97.51% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           59      2.16%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959            2      0.07%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            5      0.18%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2726                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1584726764                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1584726764    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1584726764                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         2009     73.70%     73.70% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          717     26.30%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2726                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        26225                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        26225                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2726                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2726                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        28951                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    11340769                       # DTB read hits
system.cpu1.dtb.read_misses                     24844                       # DTB read misses
system.cpu1.dtb.write_hits                    7074140                       # DTB write hits
system.cpu1.dtb.write_misses                     1381                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2067                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      202                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   452                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      283                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                11365613                       # DTB read accesses
system.cpu1.dtb.write_accesses                7075521                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         18414909                       # DTB hits
system.cpu1.dtb.misses                          26225                       # DTB misses
system.cpu1.dtb.accesses                     18441134                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2259                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2259                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2078                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2259                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2259    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2259                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1118                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  9560.375671                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  8643.967571                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4716.413998                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          181     16.19%     16.19% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          171     15.30%     31.48% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          489     43.74%     75.22% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          245     21.91%     97.14% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     97.23% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      1.34%     98.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           14      1.25%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1118                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1584152264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1584152264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1584152264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          950     84.97%     84.97% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.03%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1118                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2259                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2259                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1118                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1118                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3377                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    39752348                       # ITB inst hits
system.cpu1.itb.inst_misses                      2259                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1156                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1892                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                39754607                       # ITB inst accesses
system.cpu1.itb.hits                         39752348                       # DTB hits
system.cpu1.itb.misses                           2259                       # DTB misses
system.cpu1.itb.accesses                     39754607                       # DTB accesses
system.cpu1.numCycles                       114648497                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   48281933                       # Number of instructions committed
system.cpu1.committedOps                     59077199                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      5147990                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2790                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5576811814                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.374563                       # CPI: cycles per instruction
system.cpu1.ipc                              0.421130                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2790                       # number of quiesce instructions executed
system.cpu1.tickCycles                       97744251                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       16904246                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           195096                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          474.102569                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           17976294                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           195460                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            91.969170                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90457158500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.102569                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.925982                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.925982                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           50                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         36856215                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        36856215                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     10952474                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       10952474                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6779584                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6779584                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50047                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        50047                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80034                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        80034                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71497                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71497                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     17732058                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        17732058                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     17782105                       # number of overall hits
system.cpu1.dcache.overall_hits::total       17782105                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       158503                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       158503                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       144597                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       144597                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30804                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30804                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16970                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16970                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23713                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23713                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       303100                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        303100                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       333904                       # number of overall misses
system.cpu1.dcache.overall_misses::total       333904                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2370328398                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2370328398                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3872727461                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3872727461                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    316464239                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    316464239                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    558424163                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    558424163                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       271500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       271500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6243055859                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6243055859                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6243055859                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6243055859                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     11110977                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     11110977                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6924181                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6924181                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80851                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        80851                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95210                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        95210                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     18035158                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     18035158                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     18116009                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     18116009                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.014265                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.014265                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020883                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.020883                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380997                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380997                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174941                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174941                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249060                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249060                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.016806                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.016806                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.018431                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.018431                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14954.470250                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14954.470250                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26782.903248                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26782.903248                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18648.452504                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18648.452504                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23549.283642                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23549.283642                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20597.346945                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20597.346945                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18697.158042                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18697.158042                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       119832                       # number of writebacks
system.cpu1.dcache.writebacks::total           119832                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16048                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        16048                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52216                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        52216                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12045                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12045                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        68264                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        68264                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        68264                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        68264                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       142455                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       142455                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92381                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        92381                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29949                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29949                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4925                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4925                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23713                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23713                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       234836                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       234836                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       264785                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       264785                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14604                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14604                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11935                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26539                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26539                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1925101376                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1925101376                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2304194019                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2304194019                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    483540014                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    483540014                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     80690501                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     80690501                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521529337                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521529337                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       262500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       262500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4229295395                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4229295395                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4712835409                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4712835409                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2321932001                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2321932001                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1843920001                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1843920001                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4165852002                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4165852002                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.012821                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.012821                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013342                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013342                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.370422                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.370422                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050771                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050771                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249060                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249060                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013021                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.013021                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014616                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.014616                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13513.750841                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13513.750841                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24942.293534                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24942.293534                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16145.447728                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16145.447728                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.858071                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.858071                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21993.393371                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21993.393371                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18009.570062                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18009.570062                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17798.725037                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17798.725037                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158992.878732                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158992.878732                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154496.858065                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154496.858065                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156970.948491                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156970.948491                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           948604                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.330921                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           38801180                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           949116                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.881389                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72079277000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.330921                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975256                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975256                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          467                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           45                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         80449708                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        80449708                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     38801180                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       38801180                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     38801180                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        38801180                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     38801180                       # number of overall hits
system.cpu1.icache.overall_hits::total       38801180                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       949116                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       949116                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       949116                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        949116                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       949116                       # number of overall misses
system.cpu1.icache.overall_misses::total       949116                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8198295158                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8198295158                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8198295158                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8198295158                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8198295158                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8198295158                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     39750296                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     39750296                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     39750296                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     39750296                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     39750296                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     39750296                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023877                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.023877                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023877                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.023877                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023877                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.023877                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8637.822098                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8637.822098                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8637.822098                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8637.822098                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8637.822098                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8637.822098                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       949116                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       949116                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       949116                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       949116                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       949116                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       949116                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7247841842                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7247841842                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7247841842                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7247841842                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7247841842                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7247841842                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10378250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10378250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10378250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10378250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023877                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.023877                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023877                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.023877                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7636.413085                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7636.413085                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7636.413085                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7636.413085                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92662.946429                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92662.946429                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       197332                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       197391                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           51                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        58593                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           54928                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15357.291554                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1177888                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           69820                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           16.870352                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  7821.827388                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    38.231580                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.097899                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4362.380441                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2262.649841                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   872.104404                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.477406                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002333                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.266259                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.138101                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.053229                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.937335                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1066                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           49                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13777                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          657                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          409                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6108                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7366                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.065063                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002991                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.840881                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        22523169                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       22523169                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        28304                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2558                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       928097                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       105681                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1064640                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       119832                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       119832                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1525                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1525                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          984                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          984                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27488                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27488                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        28304                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2558                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       928097                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       133169                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1092128                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        28304                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2558                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       928097                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       133169                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1092128                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          652                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          213                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        21019                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        71648                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        93532                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28424                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28424                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22729                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22729                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34944                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34944                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          652                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          213                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        21019                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       106592                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       128476                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          652                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          213                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        21019                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       106592                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       128476                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14243728                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4276499                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    737905240                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1619303994                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   2375729461                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    539163396                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    539163396                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    459339096                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    459339096                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       256500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       256500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1382755927                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1382755927                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14243728                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4276499                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    737905240                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3002059921                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3758485388                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14243728                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4276499                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    737905240                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3002059921                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3758485388                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        28956                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2771                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       949116                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       177329                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1158172                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       119832                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       119832                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29949                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29949                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23713                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23713                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62432                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62432                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        28956                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2771                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       949116                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       239761                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1220604                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        28956                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2771                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       949116                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       239761                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1220604                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.022146                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.404040                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.080758                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.949080                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.949080                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.958504                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.958504                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.559713                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.559713                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.022146                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.444576                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.105256                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022517                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.076868                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.022146                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.444576                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.105256                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35106.581664                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22600.826178                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25400.178132                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18968.596820                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18968.596820                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20209.384311                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20209.384311                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39570.625200                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39570.625200                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35106.581664                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28164.026578                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29254.377378                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21846.208589                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20077.460094                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35106.581664                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28164.026578                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29254.377378                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          106                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    26.500000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        32037                       # number of writebacks
system.cpu1.l2cache.writebacks::total           32037                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst           22                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           90                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          112                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          230                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          230                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           22                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          320                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          342                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           22                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          320                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          342                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          652                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          213                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        20997                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        71558                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        93420                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23227                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        23227                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28424                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28424                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22729                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22729                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34714                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34714                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          652                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          213                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        20997                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       106272                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       128134                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          652                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          213                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        20997                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       106272                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        23227                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       151361                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14604                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14716                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11935                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26539                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26651                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9997244                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2891999                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    599685760                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1151439996                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1764014999                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    924666076                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    924666076                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    453146005                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    453146005                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    343401219                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    343401219                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       217500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       217500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1124328801                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1124328801                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9997244                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2891999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    599685760                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2275768797                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2888343800                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9997244                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2891999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    599685760                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2275768797                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    924666076                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3813009876                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9435750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2205092749                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2214528499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1754280499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1754280499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9435750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3959373248                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3968808998                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.403532                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.080662                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.949080                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.949080                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.958504                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.958504                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.556029                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.556029                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.443241                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.104976                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022517                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.076868                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.022123                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.443241                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.124005                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16091.003046                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18882.626836                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39809.965816                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15942.372819                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942.372819                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15108.505390                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.505390                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32388.339027                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32388.339027                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21414.566367                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22541.587713                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28560.544840                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21414.566367                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25191.495009                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150992.382156                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150484.404662                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146986.216925                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146986.216925                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149190.747504                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148917.826648                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1571398                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1216942                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        31019                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11935                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       119832                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        28997                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        76686                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42144                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86299                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        85106                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66899                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1898456                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       835008                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7108                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        62262                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2802834                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     60750592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25843924                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11084                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       115824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          86721424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     645948                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1991449                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.302505                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.459343                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1389026     69.75%     69.75% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2            602423     30.25%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1991449                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     839147473                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80233998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1424533908                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    411735495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4337999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     33317735                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198974708                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36789763                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36433                       # number of replacements
system.iocache.tags.tagsinuse               14.479314                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270323444000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.479314                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904957                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904957                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31377127                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31377127                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6657460818                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6657460818                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31377127                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31377127                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31377127                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31377127                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129123.979424                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129123.979424                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.910391                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.910391                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129123.979424                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129123.979424                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129123.979424                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129123.979424                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22685                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3423                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.627228                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18676627                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18676627                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4773786844                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4773786844                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18676627                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18676627                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18676627                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18676627                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76858.547325                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76858.547325                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.193352                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.193352                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76858.547325                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76858.547325                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76858.547325                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76858.547325                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   135621                       # number of replacements
system.l2c.tags.tagsinuse                64040.319526                       # Cycle average of tags in use
system.l2c.tags.total_refs                     379947                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   200130                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.898501                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12350.088291                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.394364                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030949                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8481.237345                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2821.026897                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35473.229907                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.484833                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2216.311582                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      599.378307                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2022.137051                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.188447                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.129413                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043045                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.541279                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000129                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.033818                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009146                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030855                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.977178                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29987                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           56                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34466                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          143                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5502                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        24342                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          307                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3362                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30784                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.457565                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.525909                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5285534                       # Number of tag accesses
system.l2c.tags.data_accesses                 5285534                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          409                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           68                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              48212                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              49449                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        47699                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          127                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           23                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              17668                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data               9341                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         5522                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 178518                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          232415                       # number of Writeback hits
system.l2c.Writeback_hits::total               232415                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3312                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             786                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                4098                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           163                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           161                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               324                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4321                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1657                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5978                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           409                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            68                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               48212                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               53770                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        47699                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           127                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            23                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               17668                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               10998                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5522                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  184496                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          409                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           68                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              48212                       # number of overall hits
system.l2c.overall_hits::cpu0.data              53770                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        47699                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          127                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           23                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              17668                       # number of overall hits
system.l2c.overall_hits::cpu1.data              10998                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5522                       # number of overall hits
system.l2c.overall_hits::total                 184496                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          131                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            22670                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             9764                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       132484                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3329                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1605                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         6236                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               176232                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          9270                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2936                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12206                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          679                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1284                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1963                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11261                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8349                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19610                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          131                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22670                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21025                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       132484                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3329                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9954                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6236                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195842                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          131                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22670                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21025                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       132484                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           12                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3329                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9954                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6236                       # number of overall misses
system.l2c.overall_misses::total               195842                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     11375500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        82500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1826895022                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    860956862                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  13678177756                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1020250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    277468755                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    142082250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher    821626642                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    17619685537                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     12058658                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2910410                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14969068                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1225966                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1472453                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2698419                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1034866909                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    686149232                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1721016141                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     11375500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        82500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1826895022                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1895823771                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13678177756                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1020250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    277468755                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    828231482                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    821626642                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19340701678                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     11375500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        82500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1826895022                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1895823771                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13678177756                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1020250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    277468755                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    828231482                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    821626642                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19340701678                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          540                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           69                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          70882                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          59213                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       180183                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          139                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           23                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          20997                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          10946                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        11758                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             354750                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       232415                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           232415                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        12582                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3722                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           16304                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          842                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1445                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2287                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15582                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10006                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25588                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          540                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           69                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           70882                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           74795                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180183                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          139                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           23                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           20997                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           20952                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11758                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              380338                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          540                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           69                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          70882                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          74795                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180183                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          139                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           23                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          20997                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          20952                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11758                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             380338                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.319827                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.164896                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.158546                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.146629                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.496778                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.736767                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.788823                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.748651                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.806413                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.888581                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.858330                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.722693                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.834399                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.766375                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.319827                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.281102                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.158546                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.475086                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.514916                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.242593                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.014493                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.319827                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.281102                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.086331                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.158546                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.475086                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.514916                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80586.458844                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88176.655264                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83348.980174                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88524.766355                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 99980.057748                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1300.826106                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   991.284060                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1226.369654                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1805.546392                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1146.770249                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1374.640346                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91898.313560                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82183.403042                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 87762.169352                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80586.458844                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 90169.977218                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83348.980174                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83205.895318                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98756.659338                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86835.877863                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80586.458844                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 90169.977218                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85020.833333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83348.980174                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83205.895318                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98756.659338                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              101997                       # number of writebacks
system.l2c.writebacks::total                   101997                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          131                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        22668                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         9764                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           12                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3329                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1605                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         6236                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          176230                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9270                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2936                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12206                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          679                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1284                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1963                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11261                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8349                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19610                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          131                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22668                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21025                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3329                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9954                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6236                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195840                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          131                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22668                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21025                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       132484                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3329                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9954                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6236                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195840                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20388                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14601                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38468                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19084                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11935                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31019                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26536                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69487                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        70000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1542775978                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    738824138                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12045165114                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       870250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    235730745                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    121970250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher    745216962                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15440351437                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    165428726                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     52162926                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    217591652                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     12163677                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     22807281                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     34970958                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    895596591                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    581734768                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1477331359                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1542775978                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1634420729                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12045165114                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       870250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    235730745                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    703705018                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    745216962                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16917682796                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9728000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1542775978                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1634420729                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12045165114                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       870250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    235730745                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    703705018                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    745216962                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16917682796                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3717048000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6862750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919952251                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5848571001                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2762074500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1533074001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4295148501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6479122500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6862750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3453026252                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10143719502                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.164896                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.146629                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.496772                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.736767                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.788823                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.748651                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.806413                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.888581                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858330                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.722693                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.834399                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.766375                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.281102                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.475086                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.514910                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.242593                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.014493                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.319799                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.281102                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735275                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.086331                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.158546                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.475086                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530362                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.514910                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75668.182917                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70811.278162                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75993.925234                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 87614.772950                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.601510                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.664169                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17826.614124                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17914.104566                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.679907                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.057565                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79530.822396                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69677.179063                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75335.612392                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77737.014459                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70811.278162                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70695.702029                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86385.226695                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68059.642580                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77737.014459                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70811.278162                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70695.702029                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86385.226695                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182315.479694                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131494.572358                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152037.303759                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144732.472228                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128451.948136                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138468.309778                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164144.773510                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130126.102352                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 145980.104221                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              214941                       # Transaction distribution
system.membus.trans_dist::ReadResp             214941                       # Transaction distribution
system.membus.trans_dist::WriteReq              31019                       # Transaction distribution
system.membus.trans_dist::WriteResp             31019                       # Transaction distribution
system.membus.trans_dist::Writeback            138187                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            76766                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40830                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14310                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39945                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19469                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       662279                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       784385                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 893281                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28304                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19271336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19463652                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24099108                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           124366                       # Total snoops (count)
system.membus.snoop_fanout::samples            577962                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  577962    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              577962                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91190000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12300498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1168075116                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1171902830                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37484237                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             516760                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            516745                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31019                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31019                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           232415                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36259                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           80723                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41154                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         121877                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51826                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51826                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1082609                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       339699                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1422308                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34055964                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5608584                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39664548                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          289563                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           990166                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.036865                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.188429                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 953664     96.31%     96.31% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36502      3.69%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             990166                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          786658690                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           342000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         681591350                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         259907159                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------