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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.658488 # Number of seconds simulated
sim_ticks 2658488068000 # Number of ticks simulated
final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 70694 # Simulator instruction rate (inst/s)
host_op_rate 85127 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2981704600 # Simulator tick rate (ticks/s)
host_mem_usage 438480 # Number of bytes of host memory used
host_seconds 891.60 # Real time elapsed on the host
sim_insts 63030433 # Number of instructions simulated
sim_ops 75898814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory
system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory
system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory
system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15512805 # Number of read requests accepted
system.physmem.writeReqs 825159 # Number of write requests accepted
system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue
system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 969393 # Per bank write bursts
system.physmem.perBankRdBursts::1 969270 # Per bank write bursts
system.physmem.perBankRdBursts::2 969024 # Per bank write bursts
system.physmem.perBankRdBursts::3 969581 # Per bank write bursts
system.physmem.perBankRdBursts::4 971912 # Per bank write bursts
system.physmem.perBankRdBursts::5 969565 # Per bank write bursts
system.physmem.perBankRdBursts::6 969152 # Per bank write bursts
system.physmem.perBankRdBursts::7 969036 # Per bank write bursts
system.physmem.perBankRdBursts::8 969555 # Per bank write bursts
system.physmem.perBankRdBursts::9 969606 # Per bank write bursts
system.physmem.perBankRdBursts::10 969469 # Per bank write bursts
system.physmem.perBankRdBursts::11 968910 # Per bank write bursts
system.physmem.perBankRdBursts::12 969137 # Per bank write bursts
system.physmem.perBankRdBursts::13 969414 # Per bank write bursts
system.physmem.perBankRdBursts::14 969294 # Per bank write bursts
system.physmem.perBankRdBursts::15 968822 # Per bank write bursts
system.physmem.perBankWrBursts::0 7303 # Per bank write bursts
system.physmem.perBankWrBursts::1 7359 # Per bank write bursts
system.physmem.perBankWrBursts::2 6981 # Per bank write bursts
system.physmem.perBankWrBursts::3 7260 # Per bank write bursts
system.physmem.perBankWrBursts::4 7486 # Per bank write bursts
system.physmem.perBankWrBursts::5 7442 # Per bank write bursts
system.physmem.perBankWrBursts::6 7374 # Per bank write bursts
system.physmem.perBankWrBursts::7 7195 # Per bank write bursts
system.physmem.perBankWrBursts::8 7413 # Per bank write bursts
system.physmem.perBankWrBursts::9 7378 # Per bank write bursts
system.physmem.perBankWrBursts::10 7327 # Per bank write bursts
system.physmem.perBankWrBursts::11 7067 # Per bank write bursts
system.physmem.perBankWrBursts::12 6951 # Per bank write bursts
system.physmem.perBankWrBursts::13 7051 # Per bank write bursts
system.physmem.perBankWrBursts::14 7072 # Per bank write bursts
system.physmem.perBankWrBursts::15 6798 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2658486560500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 59 # Read request sizes (log2)
system.physmem.readPktSize::3 15335449 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 177297 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 67875 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads
system.physmem.totQLat 404032545000 # Total ticks spent queuing
system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.94 # Data bus utilization in percentage
system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
system.physmem.readRowHits 14503540 # Number of row buffer hits during reads
system.physmem.writeRowHits 85448 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes
system.physmem.avgGap 162718.35 # Average gap between requests
system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states
system.physmem.memoryStateTime::REF 88772580000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ)
system.physmem.averagePower::0 697.245591 # Core power per rank (mW)
system.physmem.averagePower::1 697.198662 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 16692376 # Transaction distribution
system.membus.trans_dist::ReadResp 16692376 # Transaction distribution
system.membus.trans_dist::WriteReq 768869 # Transaction distribution
system.membus.trans_dist::WriteResp 768869 # Transaction distribution
system.membus.trans_dist::Writeback 67875 # Transaction distribution
system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution
system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution
system.membus.trans_dist::ReadExReq 15293 # Transaction distribution
system.membus.trans_dist::ReadExResp 8420 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 68687 # Total snoops (count)
system.membus.snoop_fanout::samples 327086 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 327086 # Request fanout histogram
system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 92119 # number of replacements
system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use
system.l2c.tags.total_refs 396231 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5120698 # Number of tag accesses
system.l2c.tags.data_accesses 5120698 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits
system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits
system.l2c.Writeback_hits::total 215010 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits
system.l2c.demand_hits::total 204060 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits
system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits
system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits
system.l2c.overall_hits::total 204060 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3178 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80451 # number of ReadReq misses
system.l2c.ReadReq_misses::total 166440 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.inst 7948 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.inst 5460 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 13408 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.inst 1046 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.inst 1101 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2147 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.inst 4019 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.inst 4520 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 8539 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 8241 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 7698 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 80451 # number of demand (read+write) misses
system.l2c.demand_misses::total 174979 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 8241 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 78569 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses
system.l2c.overall_misses::cpu1.inst 7698 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 80451 # number of overall misses
system.l2c.overall_misses::total 174979 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 256500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 326360000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1107250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 255357749 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 16477212323 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.inst 13294932 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.inst 6165736 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 19460668 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 621976 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4504808 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 5126784 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.inst 291276419 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.inst 332394712 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 623671131 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 256500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 617636419 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1107250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 587752461 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 17100883454 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 256500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 617636419 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1107250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 587752461 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of overall miss cycles
system.l2c.overall_miss_latency::total 17100883454 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 197 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 19153 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166585 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 251 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 59 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 22864 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156739 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 365892 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 215010 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 215010 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.inst 10999 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.inst 7485 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.inst 1146 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.inst 1314 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2460 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.inst 6230 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.inst 6917 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 13147 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 197 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 25383 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166585 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 251 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 59 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 29781 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156739 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 379039 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 197 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 25383 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166585 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 251 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 59 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 29781 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156739 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 379039 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.045455 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.220435 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.138996 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.454888 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.722611 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.729459 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.725384 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.912740 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837900 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.872764 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.inst 0.645104 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.inst 0.653462 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.649502 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.045455 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.324666 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.258487 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.461639 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.045455 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.324666 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.258487 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.461639 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 64125 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77299.857887 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80351.714600 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 98997.911097 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1672.739305 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1129.255678 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1451.422136 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 594.623327 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4091.560400 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 2387.882627 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 72474.849216 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73538.653097 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73037.958894 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 97731.061750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 97731.061750 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 255 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 42.500000 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 67875 # number of writebacks
system.l2c.writebacks::total 67875 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 4222 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 3176 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 166430 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7948 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5460 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 13408 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1046 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1101 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2147 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.inst 4019 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.inst 4520 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 8539 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 8241 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 7696 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 174969 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 8241 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 7696 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 174969 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 207500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273765000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 936250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 215773749 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 14418655831 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 80020888 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 54949416 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 134970304 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10533533 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11044096 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 21577629 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 240707081 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 275649788 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 516356869 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 207500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 514472081 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 936250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 491423537 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 14935012700 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 207500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 514472081 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 936250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 491423537 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 14935012700 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12573700750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155061349748 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167635050498 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125597500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721355858 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16846953358 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13699298250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170782705606 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184482003856 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.220435 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138908 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.454861 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.722611 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.729459 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.725384 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.912740 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837900 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.872764 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.645104 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.653462 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.649502 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.461612 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.461612 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 170698 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution
system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution
system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.branchPred.lookups 7252165 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 6449087 # DTB read hits
system.cpu0.dtb.read_misses 22394 # DTB read misses
system.cpu0.dtb.write_hits 5803603 # DTB write hits
system.cpu0.dtb.write_misses 1784 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 6471481 # DTB read accesses
system.cpu0.dtb.write_accesses 5805387 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 12252690 # DTB hits
system.cpu0.dtb.misses 24178 # DTB misses
system.cpu0.dtb.accesses 12276868 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 13302311 # ITB inst hits
system.cpu0.itb.inst_misses 3954 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses
system.cpu0.itb.hits 13302311 # DTB hits
system.cpu0.itb.misses 3954 # DTB misses
system.cpu0.itb.accesses 13306265 # DTB accesses
system.cpu0.numCycles 86799146 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 29471412 # Number of instructions committed
system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.945198 # CPI: cycles per instruction
system.cpu0.ipc 0.339536 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed
system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped
system.cpu0.icache.tags.replacements 670908 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits
system.cpu0.icache.overall_hits::total 12627162 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses
system.cpu0.icache.overall_misses::total 671424 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 661783 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements 185629 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16039.205043 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1209112 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 201843 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.990359 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 5120294500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 4761.005363 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.831562 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.161164 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2118.524351 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9136.682602 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.290589 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001394 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.129304 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.557659 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.978955 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8350 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7848 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 57 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 864 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5964 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1431 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1438 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509644 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.479004 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 22924468 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 22924468 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29315 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5251 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 886043 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 920609 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 275708 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 275708 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1811 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 1811 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 729 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 729 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107812 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 107812 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29315 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5251 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 993855 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1028421 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29315 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5251 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 993855 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1028421 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 519 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49158 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 49848 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18945 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 18945 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10134 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 10134 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23532 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 23532 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 519 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 72690 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 73380 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 519 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 72690 # number of overall misses
system.cpu0.l2cache.overall_misses::total 73380 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11037500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618999 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1323798925 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 1338455424 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312100526 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 312100526 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 201024600 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 201024600 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1393500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1393500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 857324396 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 857324396 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11037500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618999 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2181123321 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 2195779820 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11037500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618999 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2181123321 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 2195779820 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 29834 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5422 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935201 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 970457 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 275708 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 275708 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20756 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 20756 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10863 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 10863 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131344 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 131344 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 29834 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5422 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1066545 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1101801 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.932891 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179163 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179163 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031538 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068155 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.066600 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031538 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068155 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.066600 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21163.736842 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26929.470788 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26850.734714 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16474.031459 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16474.031459 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19836.648905 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19836.648905 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 232250 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232250 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 36432.279279 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 36432.279279 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 29923.409921 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 29923.409921 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 30 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 24.300000 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 114449 # number of writebacks
system.cpu0.l2cache.writebacks::total 114449 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2940 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 2940 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 800 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 800 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3740 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 3740 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3740 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 3740 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 519 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 171 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46218 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 46908 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 225933 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18945 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18945 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10134 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10134 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 6 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22732 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 22732 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 519 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 171 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68950 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 69640 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 519 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 171 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68950 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 295573 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2421001 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 946752983 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 956578484 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8634543726 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 342474562 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 342474562 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 146006456 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 146006456 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1155500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1155500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 598541592 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 598541592 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2421001 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1545294575 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 1555120076 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2421001 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1545294575 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 10189663802 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14161707249 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14161707249 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312859997 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312859997 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15474567246 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15474567246 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049420 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048336 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.932891 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.173072 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.173072 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063206 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.268264 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22330.845434 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 362294 # number of replacements
system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 24357333 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.inst 5805631 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5805631 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275579 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5275579 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147422 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146630 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 146630 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.inst 11081210 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11081210 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.inst 11081210 # number of overall hits
system.cpu0.dcache.overall_hits::total 11081210 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.inst 308329 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 308329 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.inst 276386 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 276386 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10191 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10869 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 10869 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.inst 584715 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.inst 584715 # number of overall misses
system.cpu0.dcache.overall_misses::total 584715 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3680932639 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4210104069 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 167480751 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254581965 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13495.526381 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13495.526381 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 275708 # number of writebacks
system.cpu0.dcache.writebacks::total 275708 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54553 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 54553 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124298 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 124298 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.inst 178851 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 178851 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.inst 178851 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 178851 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 253776 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 253776 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152088 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 152088 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10117 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10117 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10869 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 10869 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.inst 405864 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 405864 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.inst 405864 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 405864 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2514607539 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2514607539 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2141849701 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141849701 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 146522249 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146522249 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231876035 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231876035 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1427500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1427500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4656457240 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 4656457240 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4656457240 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 4656457240 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14652229736 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14652229736 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394826498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394826498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16047056234 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16047056234 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041508 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041508 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027394 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027394 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064189 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064189 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069010 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069010 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.034791 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.034791 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9908.768122 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9908.768122 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14082.963159 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14082.963159 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14482.776416 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14482.776416 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21333.704573 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21333.704573 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 7012649 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7899300 # DTB read hits
system.cpu1.dtb.read_misses 20789 # DTB read misses
system.cpu1.dtb.write_hits 6047693 # DTB write hits
system.cpu1.dtb.write_misses 2209 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7920089 # DTB read accesses
system.cpu1.dtb.write_accesses 6049902 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 13946993 # DTB hits
system.cpu1.dtb.misses 22998 # DTB misses
system.cpu1.dtb.accesses 13969991 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 14215184 # ITB inst hits
system.cpu1.itb.inst_misses 5010 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses
system.cpu1.itb.hits 14215184 # DTB hits
system.cpu1.itb.misses 5010 # DTB misses
system.cpu1.itb.accesses 14220194 # DTB accesses
system.cpu1.numCycles 502294457 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 33559021 # Number of instructions committed
system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 14.967494 # CPI: cycles per instruction
system.cpu1.ipc 0.066811 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed
system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped
system.cpu1.icache.tags.replacements 777492 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits
system.cpu1.icache.overall_hits::total 13433657 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses
system.cpu1.icache.overall_misses::total 778004 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 606235 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements 179644 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits
system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 146 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 146 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 85592 # number of overall misses
system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1004785618 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1004785618 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11596750 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3042000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2529918546 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 2544557296 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11596750 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3042000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2529918546 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 2544557296 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29788 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 987949 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 1025341 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 242084 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 242084 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20604 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 20604 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13688 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 13688 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136335 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 136335 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29788 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 1124284 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 1161676 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29788 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 1124284 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 1161676 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019200 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062346 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.905455 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.905455 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.915400 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.915400 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.176015 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.176015 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019200 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076130 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.074232 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019200 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076130 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.074232 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.616438 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24760.661223 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24740.852208 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16737.334477 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16737.334477 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20053.406624 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20053.406624 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 278833.333333 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 278833.333333 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41871.301329 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41871.301329 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29507.929633 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29507.929633 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 1374 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 55 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.981818 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 100561 # number of writebacks
system.cpu1.l2cache.writebacks::total 100561 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3711 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3711 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1353 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 1353 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5064 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5064 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 495 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 146 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57884 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 58525 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 195430 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18656 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18656 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12530 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12530 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22644 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 22644 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 495 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 146 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80528 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 81169 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 495 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 146 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80528 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 276599 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2020000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1052949978 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1063101228 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10102217802 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 306954055 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 306954055 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178539396 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178539396 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 654500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 654500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 627825362 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 627825362 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2020000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1680775340 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 1690926590 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2020000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1680775340 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 11793144392 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174927425750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174927425750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797119642 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797119642 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203724545392 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203724545392 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058590 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.057079 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.905455 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.905455 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.915400 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915400 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.166091 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.166091 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069872 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.238103 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18190.691348 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18164.907783 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51692.257084 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16453.369157 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16453.369157 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14248.954190 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 218166.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27725.903639 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27725.903639 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20832.172258 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42636.251006 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 322748 # number of replacements
system.cpu1.dcache.tags.tagsinuse 491.331318 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 11400815 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 323107 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 35.284952 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 72473667000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.331318 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959631 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.959631 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 24164293 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 24164293 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375660 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 6375660 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.inst 4821255 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4821255 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83384 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 83384 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81522 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 81522 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.inst 11196915 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11196915 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.inst 11196915 # number of overall hits
system.cpu1.dcache.overall_hits::total 11196915 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.inst 235192 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 235192 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.inst 286280 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 286280 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11913 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11913 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13691 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 13691 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.inst 521472 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 521472 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.inst 521472 # number of overall misses
system.cpu1.dcache.overall_misses::total 521472 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3078984138 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3078984138 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4572469338 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4572469338 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 214431997 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 214431997 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314961410 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 314961410 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 915000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 915000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.inst 7651453476 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7651453476 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.inst 7651453476 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7651453476 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6610852 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 6610852 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5107535 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5107535 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95297 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 95297 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95213 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 95213 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.inst 11718387 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 11718387 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.inst 11718387 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 11718387 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035577 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.035577 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056051 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.056051 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.125009 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125009 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143793 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143793 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044500 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.044500 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044500 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.044500 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13091.364239 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13091.364239 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15972.018087 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 15972.018087 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17999.831864 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17999.831864 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23004.996713 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23004.996713 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14672.798302 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14672.798302 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 242084 # number of writebacks
system.cpu1.dcache.writebacks::total 242084 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36921 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 36921 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129344 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 129344 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 46 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.inst 166265 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 166265 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.inst 166265 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 166265 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 198271 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 198271 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156936 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 156936 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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