path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.845843                       # Number of seconds simulated
sim_ticks                                2845842660500                       # Number of ticks simulated
final_tick                               2845842660500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 164712                       # Simulator instruction rate (inst/s)
host_op_rate                                   199442                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3743328799                       # Simulator tick rate (ticks/s)
host_mem_usage                                 646452                       # Number of bytes of host memory used
host_seconds                                   760.24                       # Real time elapsed on the host
sim_insts                                   125221621                       # Number of instructions simulated
sim_ops                                     151624712                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        10368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3007420                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8732480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           774240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       399936                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12926236                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1722304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       153024                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1875328                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8977344                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8995088                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             47516                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       136445                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             12121                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6249                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                202521                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          140271                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               144707                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3643                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst             1056777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3068504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              272060                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       140533                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4542147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         605200                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53771                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             658971                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3154547                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst               6221                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3160782                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3154547                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst            1062998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3068504                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             272074                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       140533                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7702929                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        202521                       # Number of read requests accepted
system.physmem.writeReqs                       180931                       # Number of write requests accepted
system.physmem.readBursts                      202521                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     180931                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12951936                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  11206784                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12926236                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11313424                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5797                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13571                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12806                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12696                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13455                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13223                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15141                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12251                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12720                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12666                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12396                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12410                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12030                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11077                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12224                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12978                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12239                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12062                       # Per bank write bursts
system.physmem.perBankWrBursts::0               11243                       # Per bank write bursts
system.physmem.perBankWrBursts::1               11520                       # Per bank write bursts
system.physmem.perBankWrBursts::2               11868                       # Per bank write bursts
system.physmem.perBankWrBursts::3               11342                       # Per bank write bursts
system.physmem.perBankWrBursts::4               10753                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10659                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11197                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10854                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10720                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10780                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10917                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10553                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10892                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10850                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10512                       # Per bank write bursts
system.physmem.perBankWrBursts::15              10446                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    2845842079500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  201934                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 176495                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     98520                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     50579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9843                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6337                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5553                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4965                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       735                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      250                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      156                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10076                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    12804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    12238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    12014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    11495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    11369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9041                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        94139                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      256.627498                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     142.457232                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     317.924062                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          48795     51.83%     51.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18347     19.49%     71.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6488      6.89%     78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3770      4.00%     82.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2738      2.91%     85.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1619      1.72%     86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          964      1.02%     87.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1076      1.14%     89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10342     10.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          94139                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7479                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.058430                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      520.327968                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7478     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7479                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7479                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.413023                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.870843                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.578889                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            6390     85.44%     85.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             248      3.32%     88.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             198      2.65%     91.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              77      1.03%     92.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             144      1.93%     94.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              30      0.40%     94.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              35      0.47%     95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              33      0.44%     95.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              72      0.96%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              21      0.28%     96.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103             96      1.28%     98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            18      0.24%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            22      0.29%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            12      0.16%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            35      0.47%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             4      0.05%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            12      0.16%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             4      0.05%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             8      0.11%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             2      0.03%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             4      0.05%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             3      0.04%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             2      0.03%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7479                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5783977250                       # Total ticks spent queuing
system.physmem.totMemAccLat                9578489750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1011870000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28580.63                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47330.63                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.55                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.54                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.98                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                     168404                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    114936                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.21                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  65.63                       # Row buffer hit rate for writes
system.physmem.avgGap                      7421638.38                       # Average gap between requests
system.physmem.pageHitRate                      75.06                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  372813840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  203420250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 818672400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                579545280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185876137200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83421293220                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634324841000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905596723190                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.608836                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2718714861000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95028700000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32092142750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  338877000                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  184903125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 759837000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                555141600                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185876137200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82372109895                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635245177250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905332183070                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.515879                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720254769500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95028700000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30559102000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               35059389                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17250705                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1579435                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20094508                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               14609065                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.701780                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               10810171                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            733013                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    67889                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               67889                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44852                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23037                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        67889                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          67889    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        67889                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6673                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  8598.195564                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  7320.525431                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6106.619536                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6491     97.27%     97.27% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          168      2.52%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            6      0.09%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6673                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    287368000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      287368000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    287368000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5164     77.39%     77.39% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1509     22.61%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6673                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67889                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67889                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6673                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6673                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        74562                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23969568                       # DTB read hits
system.cpu0.dtb.read_misses                     61820                       # DTB read misses
system.cpu0.dtb.write_hits                   17946825                       # DTB write hits
system.cpu0.dtb.write_misses                     6069                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3496                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1251                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2004                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24031388                       # DTB read accesses
system.cpu0.dtb.write_accesses               17952894                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         41916393                       # DTB hits
system.cpu0.dtb.misses                          67889                       # DTB misses
system.cpu0.dtb.accesses                     41984282                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3825                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3825                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3518                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3825                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3825    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3825                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2419                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  8874.535345                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  7628.532351                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4888.994435                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191         1491     61.64%     61.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383          888     36.71%     98.35% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575            4      0.17%     98.51% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2419                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    286941000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      286941000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    286941000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2119     87.60%     87.60% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          300     12.40%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2419                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3825                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3825                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2419                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2419                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6244                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    70462798                       # ITB inst hits
system.cpu0.itb.inst_misses                      3825                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2222                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7291                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                70466623                       # ITB inst accesses
system.cpu0.itb.hits                         70462798                       # DTB hits
system.cpu0.itb.misses                           3825                       # DTB misses
system.cpu0.itb.accesses                     70466623                       # DTB accesses
system.cpu0.numCycles                       234985394                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  109265327                       # Number of instructions committed
system.cpu0.committedOps                    132114239                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8364757                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1821                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5456715361                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.150594                       # CPI: cycles per instruction
system.cpu0.ipc                              0.464988                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1824                       # number of quiesce instructions executed
system.cpu0.tickCycles                      195318282                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       39667112                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           718541                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          494.305697                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           40476936                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           719053                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            56.292006                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        306903000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.inst   494.305697                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.965441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.965441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         83802985                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        83802985                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.inst     22808347                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22808347                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.inst     16863099                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16863099                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       381264                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       381264                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       362825                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       362825                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.inst     39671446                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        39671446                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.inst     39671446                       # number of overall hits
system.cpu0.dcache.overall_hits::total       39671446                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.inst       540080                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       540080                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.inst       532227                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       532227                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6489                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         6489                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        19898                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19898                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.inst      1072307                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1072307                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.inst      1072307                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1072307                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6648434719                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6648434719                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8319872197                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8319872197                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    104923750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    104923750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    438142885                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    438142885                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       309000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       309000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.inst  14968306916                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14968306916                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.inst  14968306916                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14968306916                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23348427                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23348427                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17395326                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17395326                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       387753                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387753                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       382723                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       382723                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.inst     40743753                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     40743753                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.inst     40743753                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     40743753                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023131                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.023131                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030596                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.030596                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016735                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016735                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.051991                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051991                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026318                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026318                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026318                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.026318                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       523102                       # number of writebacks
system.cpu0.dcache.writebacks::total           523102                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        42658                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        42658                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       230433                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       230433                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.inst       273091                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       273091                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.inst       273091                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       273091                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       497422                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       497422                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       301794                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       301794                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6489                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6489                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        19898                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19898                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.inst       799216                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       799216                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.inst       799216                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       799216                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5149793898                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149793898                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4423706193                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4423706193                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     91926250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     91926250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    397751115                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    397751115                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       291000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       291000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9573500091                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9573500091                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9573500091                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9573500091                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6190990749                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6190990749                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4804555500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4804555500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  10995546249                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10995546249                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021304                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021304                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017349                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017349                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016735                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016735                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.051991                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051991                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019616                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.019616                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019616                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.019616                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1982441                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.792915                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           68472197                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1982953                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.530419                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6378447750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.792915                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999596                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999596                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        142893294                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       142893294                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     68472197                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       68472197                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     68472197                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        68472197                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     68472197                       # number of overall hits
system.cpu0.icache.overall_hits::total       68472197                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1982967                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1982967                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1982967                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1982967                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1982967                       # number of overall misses
system.cpu0.icache.overall_misses::total      1982967                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18641895952                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18641895952                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  18641895952                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18641895952                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  18641895952                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18641895952                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     70455164                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     70455164                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     70455164                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     70455164                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     70455164                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     70455164                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028145                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028145                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028145                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028145                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028145                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028145                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9401.011692                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9401.011692                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9401.011692                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9401.011692                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9401.011692                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9401.011692                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1982967                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1982967                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1982967                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1982967                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1982967                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1982967                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  15657207046                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  15657207046                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  15657207046                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  15657207046                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  15657207046                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  15657207046                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    278031000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    278031000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    278031000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    278031000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028145                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028145                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028145                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7895.848517                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7895.848517                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7895.848517                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      2292717                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      2293221                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          436                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       284211                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          303376                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16141.726832                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2969035                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          319611                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.289527                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2825848630000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6310.295058                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    58.412646                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.063392                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  7791.524761                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1981.430976                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.385150                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003565                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.475557                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.120937                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.985213                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1941                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14280                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          509                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          923                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          497                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4022                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7455                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2494                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.118469                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.871582                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        55347065                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       55347065                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        80493                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4332                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2344344                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2429169                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       523100                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       523100                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4781                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         4781                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         1890                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1890                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       226532                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       226532                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        80493                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4332                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      2570876                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2655701                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        80493                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4332                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      2570876                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2655701                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          854                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          113                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       142527                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       143494                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        26406                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26406                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        18006                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18006                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        44082                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44082                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          854                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          113                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       186609                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       187576                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          854                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          113                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       186609                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       187576                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     30085500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2495499                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   5310554679                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   5343135678                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    462181513                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    462181513                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    354964789                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    354964789                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       282000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       282000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   2099231484                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2099231484                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     30085500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2495499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   7409786163                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   7442367162                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     30085500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2495499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   7409786163                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   7442367162                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        81347                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4445                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2486871                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2572663                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       523100                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       523100                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        31187                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        31187                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        19896                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19896                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       270614                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       270614                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        81347                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4445                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2757485                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2843277                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        81347                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4445                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2757485                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2843277                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.057312                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.055776                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.846699                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.846699                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.905006                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.905006                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.162896                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.162896                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.067674                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.065972                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.067674                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.065972                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37259.990591                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17502.897561                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19713.694824                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst       141000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       141000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 47621.058119                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39707.549813                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39707.549813                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       201133                       # number of writebacks
system.cpu0.l2cache.writebacks::total          201133                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst          511                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          512                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3265                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3265                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         3776                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3777                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         3776                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3777                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          854                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          112                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       142016                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       142982                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       280772                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       280772                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        26406                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26406                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        18006                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18006                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        40817                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        40817                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          854                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          112                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       182833                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       183799                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          854                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          112                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       182833                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       280772                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       464571                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   4279514975                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   4305290474                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15488924735                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15488924735                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    449600763                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    449600763                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    240569359                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    240569359                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst       219000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       219000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1467254248                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1467254248                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   5746769223                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   5772544722                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   5746769223                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15488924735                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21261469457                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6177076991                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6177076991                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4588309497                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4588309497                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10765386488                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10765386488                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.057106                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.055577                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.846699                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.846699                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.905006                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.905006                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.150831                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.150831                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.066304                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.064643                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.066304                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163393                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst       109500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       109500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2726808                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2669763                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28813                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28813                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       523100                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       388140                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        64720                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42432                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp        88655                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       299964                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       286773                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3972081                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2399294                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11788                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       172273                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6555436                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    127106560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     87442327                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17780                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       325388                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         214892055                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     732010                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4046250                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.152317                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.359328                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           3429939     84.77%     84.77% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            616311     15.23%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4046250                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2284841999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    117254000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2984852953                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1241569539                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7347491                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     90940738                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                4088735                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2366310                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           253216                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2663045                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1651600                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            62.019230                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 809555                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             58673                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    25571                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               25571                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18521                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7050                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        25571                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          25571    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        25571                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2708                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  8701.256278                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  7631.681902                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5745.938863                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         2093     77.29%     77.29% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383          481     17.76%     95.05% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           65      2.40%     97.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.07%     99.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            9      0.33%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            4      0.15%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2708                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1108722264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1108722264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1108722264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1997     73.74%     73.74% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          711     26.26%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2708                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        25571                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        25571                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2708                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2708                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        28279                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4075725                       # DTB read hits
system.cpu1.dtb.read_misses                     23546                       # DTB read misses
system.cpu1.dtb.write_hits                    3346999                       # DTB write hits
system.cpu1.dtb.write_misses                     2025                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2069                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      121                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   325                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      279                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4099271                       # DTB read accesses
system.cpu1.dtb.write_accesses                3349024                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7422724                       # DTB hits
system.cpu1.dtb.misses                          25571                       # DTB misses
system.cpu1.dtb.accesses                      7448295                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2243                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2243                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2062                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2243                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2243    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2243                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1122                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  8831.106061                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  7825.020839                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4777.823788                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          160     14.26%     14.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          676     60.25%     74.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287            3      0.27%     74.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          248     22.10%     96.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     96.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           13      1.16%     98.13% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.69%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1122                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1108154264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1108154264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1108154264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          954     85.03%     85.03% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     14.97%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1122                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2243                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2243                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1122                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1122                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3365                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     7772051                       # ITB inst hits
system.cpu1.itb.inst_misses                      2243                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1160                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1845                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7774294                       # ITB inst accesses
system.cpu1.itb.hits                          7772051                       # DTB hits
system.cpu1.itb.misses                           2243                       # DTB misses
system.cpu1.itb.accesses                      7774294                       # DTB accesses
system.cpu1.numCycles                        42246986                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   15956294                       # Number of instructions committed
system.cpu1.committedOps                     19510473                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1491389                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2792                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5648821854                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.647669                       # CPI: cycles per instruction
system.cpu1.ipc                              0.377691                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2795                       # number of quiesce instructions executed
system.cpu1.tickCycles                       30354295                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       11892691                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           187758                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          478.493571                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7034054                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           188124                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.390519                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     108317904000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.inst   478.493571                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.934558                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.934558                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          366                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.714844                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         14914460                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        14914460                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.inst      3762812                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3762812                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.inst      3070723                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3070723                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        89288                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        89288                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        69262                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        69262                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.inst      6833535                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6833535                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.inst      6833535                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6833535                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.inst       181434                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       181434                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.inst       139542                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       139542                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5058                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5058                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        23425                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23425                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.inst       320976                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        320976                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.inst       320976                       # number of overall misses
system.cpu1.dcache.overall_misses::total       320976                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2698134351                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2698134351                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3673411367                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3673411367                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     91654251                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     91654251                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    540931813                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    540931813                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       185500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       185500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.inst   6371545718                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6371545718                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.inst   6371545718                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6371545718                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3944246                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3944246                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.inst      3210265                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3210265                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        94346                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        94346                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        92687                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92687                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.inst      7154511                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7154511                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.inst      7154511                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7154511                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.046000                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.046000                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043467                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.043467                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.053611                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.053611                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.252732                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.252732                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.044863                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.044863                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.044863                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044863                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       113901                       # number of writebacks
system.cpu1.dcache.writebacks::total           113901                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        15137                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        15137                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        49794                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        49794                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.inst        64931                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        64931                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.inst        64931                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        64931                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       166297                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       166297                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        89748                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        89748                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5058                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5058                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        23425                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23425                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.inst       256045                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       256045                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.inst       256045                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       256045                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2162409829                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2162409829                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   2163633710                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2163633710                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     81526749                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     81526749                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    492905187                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    492905187                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       177500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       177500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   4326043539                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4326043539                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   4326043539                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4326043539                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    330271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    330271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    203208500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    203208500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    533479500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    533479500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042162                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042162                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027957                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027957                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.053611                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053611                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.252732                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.252732                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.035788                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.035788                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.035788                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035788                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           908016                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.415703                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6861520                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           908528                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.552348                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      71602668000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.415703                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975421                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975421                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         16448624                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        16448624                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      6861520                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6861520                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6861520                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6861520                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6861520                       # number of overall hits
system.cpu1.icache.overall_hits::total        6861520                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       908528                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       908528                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       908528                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        908528                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       908528                       # number of overall misses
system.cpu1.icache.overall_misses::total       908528                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7748571238                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7748571238                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7748571238                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7748571238                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7748571238                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7748571238                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7770048                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7770048                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7770048                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7770048                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7770048                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7770048                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.116927                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.116927                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.116927                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.116927                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.116927                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.116927                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8528.709339                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8528.709339                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8528.709339                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8528.709339                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8528.709339                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8528.709339                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       908528                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       908528                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       908528                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       908528                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       908528                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       908528                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6381932762                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   6381932762                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6381932762                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   6381932762                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6381932762                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   6381932762                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10331250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10331250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10331250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10331250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.116927                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.116927                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.116927                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7024.475593                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7024.475593                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7024.475593                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       255012                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       255045                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           26                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        67427                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           54264                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15327.785502                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1131516                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           69292                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           16.329677                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  8763.818423                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    26.824644                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.109281                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5323.780218                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1213.252936                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.534901                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001637                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.324938                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.074051                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.935534                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         2056                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           45                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        12927                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           84                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          880                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1092                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          271                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5756                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6900                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.125488                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002747                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.789001                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        21629208                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       21629208                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        28145                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2626                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       993919                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1024690                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       113900                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       113900                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1602                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1602                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst          885                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          885                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.inst        24979                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        24979                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        28145                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2626                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1018898                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1049669                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        28145                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2626                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1018898                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1049669                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          614                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          219                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        85964                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        86797                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst        28133                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28133                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst        22540                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22540                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.inst        35034                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        35034                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          614                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          219                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       120998                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       121831                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          614                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          219                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       120998                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       121831                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     13117250                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4335498                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   2028659662                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   2046112410                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst    524558345                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    524558345                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst    440871540                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    440871540                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst       173000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       173000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   1316941950                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1316941950                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     13117250                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4335498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   3345601612                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3363054360                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     13117250                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4335498                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   3345601612                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3363054360                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        28759                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2845                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      1079883                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1111487                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       113900                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       113900                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        29735                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29735                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        23425                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23425                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst        60013                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        60013                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        28759                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2845                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1139896                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1171500                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        28759                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2845                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1139896                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1171500                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.079605                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.078091                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.946124                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.946124                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.962220                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962220                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.583774                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.583774                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.106148                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.103996                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.106148                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.103996                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 23598.944465                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18645.659723                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19559.518190                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 37590.396472                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27650.057125                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27650.057125                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        33019                       # number of writebacks
system.cpu1.l2cache.writebacks::total           33019                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          106                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          106                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          284                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          284                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          390                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          390                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          390                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          390                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          614                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          219                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        85858                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        86691                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25785                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        25785                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        28133                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28133                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22540                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22540                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        34750                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34750                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          614                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          219                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       120608                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       121441                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          614                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          219                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       120608                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25785                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       147226                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   1423893692                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1435514940                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1025770621                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1025770621                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    399929245                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    399929245                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    306606785                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306606785                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst       145000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       145000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   1042779776                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1042779776                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   2466673468                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2478294716                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   2466673468                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1025770621                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3504065337                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    316947250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    316947250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    187186000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    187186000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    504133250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    504133250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.079507                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.077996                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.946124                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.946124                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.962220                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962220                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.579041                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.579041                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.105806                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103663                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.105806                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.125673                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1492249                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1157222                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2126                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2126                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       113900                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        36842                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        74786                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41424                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85596                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        82199                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        64364                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1817284                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       767101                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7150                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        61380                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2652915                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58153088                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24793955                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11380                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       115036                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          83073459                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     610470                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1874725                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.283158                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.450533                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1343882     71.68%     71.68% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            530843     28.32%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1874725                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     789561722                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79017500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1364909988                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    381206023                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4307495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     32623745                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59440                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23216                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484026                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347036169                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36822569                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36417                       # number of replacements
system.iocache.tags.tagsinuse                0.997930                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36433                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         269849823000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.997930                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062371                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062371                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30354377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30354377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9625347223                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9625347223                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     30354377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     30354377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     30354377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     30354377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124915.131687                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124915.131687                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124915.131687                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124915.131687                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124915.131687                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         56938                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7266                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.836224                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36174                       # number of writebacks
system.iocache.writebacks::total                36174                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17717377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17717377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7741561361                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7741561361                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17717377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17717377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17717377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17717377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72911.016461                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72911.016461                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   139153                       # number of replacements
system.l2c.tags.tagsinuse                64176.379405                       # Cycle average of tags in use
system.l2c.tags.total_refs                     380612                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   203608                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.869337                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   11502.485032                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    90.401142                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.038214                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst    12425.194881                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.683124                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1856.879628                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1880.036266                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.175514                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001379                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.189593                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.555628                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000117                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.028334                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.028687                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.979254                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        31795                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32593                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          145                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5678                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        25972                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3295                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        28977                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.485153                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001022                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.497330                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5313847                       # Number of tag accesses
system.l2c.tags.data_accesses                 5313847                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          426                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           63                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              70654                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        75814                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          118                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           32                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              24007                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         7439                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 178553                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          234152                       # number of Writeback hits
system.l2c.Writeback_hits::total               234152                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.inst            2938                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.inst             658                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3596                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.inst           142                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.inst           176                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               318                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.inst             3842                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.inst             1332                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5174                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           426                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            63                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               74496                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        75814                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           118                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            32                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               25339                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         7439                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  183727                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          426                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           63                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              74496                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        75814                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          118                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           32                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              25339                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         7439                       # number of overall hits
system.l2c.overall_hits::total                 183727                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          162                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            32548                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       136690                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3333                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               178995                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.inst          8970                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.inst          2734                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11704                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.inst          618                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.inst         1189                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1807                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.inst          11575                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.inst           8676                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              20251                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          162                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             44123                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       136690                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             12009                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) misses
system.l2c.demand_misses::total                199246                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          162                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            44123                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       136690                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           12                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            12009                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6249                       # number of overall misses
system.l2c.overall_misses::total               199246                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     12996250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   2445317489                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  14069068891                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       960250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    258262249                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher    826051791                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    17612731920                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.inst      7054791                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.inst      1587933                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      8642724                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.inst       937466                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.inst       512978                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1450444                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.inst    952737665                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.inst    639334486                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1592072151                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     12996250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3398055154                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14069068891                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       960250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    897596735                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    826051791                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19204804071                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     12996250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3398055154                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14069068891                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       960250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    897596735                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    826051791                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19204804071                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          588                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           64                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         103202                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       212504                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          130                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           32                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          27340                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        13688                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             357548                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       234152                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           234152                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.inst        11908                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.inst         3392                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           15300                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.inst          760                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.inst         1365                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2125                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.inst        15417                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.inst        10008                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25425                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          588                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           64                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          118619                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       212504                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          130                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           32                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           37348                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        13688                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              382973                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          588                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           64                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         118619                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       212504                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          130                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           32                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          37348                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        13688                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             382973                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.275510                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.015625                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.315381                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.092308                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.121909                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.500618                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.753275                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.806014                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.764967                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.813158                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.871062                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.850353                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.inst     0.750795                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.inst     0.866906                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.796500                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.275510                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.015625                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.371972                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.092308                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.321543                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.520261                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.275510                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.015625                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.371972                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.092308                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.321543                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.520261                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75129.577516                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77486.423342                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 98397.898936                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst   786.487291                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst   580.809437                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   738.441900                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  1516.935275                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   431.436501                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   802.680686                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 82309.949460                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73690.005302                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 78616.964644                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 77013.239218                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74743.670164                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 96387.400856                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 77013.239218                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74743.670164                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 96387.400856                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              104097                       # number of writebacks
system.l2c.writebacks::total                   104097                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          162                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        32540                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       136690                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           12                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3330                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          178984                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.inst         8970                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2734                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11704                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          618                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1189                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1807                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.inst        11575                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.inst         8676                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         20251                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          162                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        44115                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       136690                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        12006                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           199235                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          162                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        44115                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       136690                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        12006                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          199235                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2034453239                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12379828891                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       810750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    216209999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher    749741791                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15392098420                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     91762404                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     27532715                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    119295119                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6310115                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     11917186                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     18227301                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst    807808323                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst    530171012                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1337979335                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2842261562                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12379828891                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       810750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    746381011                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    749741791                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16730077755                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2842261562                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12379828891                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       810750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    746381011                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    749741791                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16730077755                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5519244498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    263262750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5782507248                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4096891000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    150604000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4247495000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   9616135498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    413866750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10030002248                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.315304                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.121800                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.500587                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.753275                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.806014                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.764967                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.813158                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.871062                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.850353                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.750795                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.866906                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.796500                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.371905                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.321463                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.520232                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.371905                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.321463                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.520232                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 83971.580069                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 83971.580069                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              217279                       # Transaction distribution
system.membus.trans_dist::ReadResp             217279                       # Transaction distribution
system.membus.trans_dist::WriteReq              30939                       # Transaction distribution
system.membus.trans_dist::WriteResp             30939                       # Transaction distribution
system.membus.trans_dist::Writeback            140271                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            75080                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40217                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13603                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40948                       # Transaction distribution
system.membus.trans_dist::ReadExResp            20159                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13590                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       668031                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       789629                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108880                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108880                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 898509                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27180                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19605228                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19796474                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4634432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4634432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24430906                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123136                       # Total snoops (count)
system.membus.snoop_fanout::samples            511969                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  511969    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              511969                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88887000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11855500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1869891749                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2005520473                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38480431                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             516876                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            516861                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30939                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30939                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           234152                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           78584                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40535                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         119119                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51536                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51536                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1131248                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       290761                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1422009                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34509719                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5415139                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39924858                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          285546                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           919868                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.039644                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.195121                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 883401     96.04%     96.04% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36467      3.96%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             919868                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1489301846                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1026000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1891845782                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         645358377                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------