path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.848948                       # Number of seconds simulated
sim_ticks                                2848948370000                       # Number of ticks simulated
final_tick                               2848948370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 158621                       # Simulator instruction rate (inst/s)
host_op_rate                                   192077                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3558804720                       # Simulator tick rate (ticks/s)
host_mem_usage                                 665700                       # Number of bytes of host memory used
host_seconds                                   800.54                       # Real time elapsed on the host
sim_insts                                   126981470                       # Number of instructions simulated
sim_ops                                     153764073                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1698304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1350900                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8536512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           207232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           624212                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       339264                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12767176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1698304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       207232                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1905536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8850048                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8867612                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26536                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21631                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133383                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3238                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9774                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5301                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                200031                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138282                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142673                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3145                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              596116                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              474175                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2996373                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               72740                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              219103                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       119084                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4481364                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         596116                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          72740                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             668856                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3106426                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3112591                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3106426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             596116                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             480326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2996373                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              72740                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             219117                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       119084                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7593956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        200031                       # Number of read requests accepted
system.physmem.writeReqs                       142673                       # Number of write requests accepted
system.physmem.readBursts                      200031                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     142673                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12791872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10112                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8880320                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12767176                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8867612                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      158                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          68768                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12184                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12601                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13506                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12929                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15744                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12758                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12529                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12787                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11927                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12161                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11607                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10617                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11871                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12870                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12074                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11708                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8731                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9199                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9827                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9174                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8354                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8906                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8822                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8920                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8409                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8625                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8250                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7761                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8553                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8825                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8501                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7898                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
system.physmem.totGap                    2848947824000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  199449                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 138282                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     88254                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61332                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7796                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5163                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4597                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3794                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       675                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      220                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      170                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92034                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.479584                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     133.901184                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     297.713631                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          49789     54.10%     54.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17966     19.52%     73.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6251      6.79%     80.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3568      3.88%     84.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2967      3.22%     87.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1449      1.57%     89.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          893      0.97%     90.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          932      1.01%     91.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8219      8.93%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92034                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6844                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.203828                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      563.949624                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6843     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6844                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6844                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.273963                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.786776                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.867549                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5615     82.04%     82.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             464      6.78%     88.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             114      1.67%     90.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             150      2.19%     92.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              34      0.50%     93.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             131      1.91%     95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              38      0.56%     95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              19      0.28%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              23      0.34%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              24      0.35%     96.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.12%     96.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.12%     96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             141      2.06%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.13%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              23      0.34%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               5      0.07%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.04%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.04%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.19%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6844                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5355833046                       # Total ticks spent queuing
system.physmem.totMemAccLat                9103451796                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    999365000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26796.18                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45546.18                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165962                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80631                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.10                       # Row buffer hit rate for writes
system.physmem.avgGap                      8313144.36                       # Average gap between requests
system.physmem.pageHitRate                      72.82                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  368376120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  200998875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 819296400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                466125840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            85041435285                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634767692000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1907742977160                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.631992                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719447345615                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95132440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     34362631885                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  327400920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  178641375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 739705200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                433006560                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            83645503290                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635992193750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1907395503735                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.510026                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2721498270016                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95132440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32317496984                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               36425252                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17807915                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1745628                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20690008                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               15088743                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.927681                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               11310340                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            873015                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    73398                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               73398                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47504                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25894                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        73398                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          73398    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        73398                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7534                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12254.313778                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11412.538854                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6583.009911                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         7485     99.35%     99.35% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           43      0.57%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            5      0.07%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7534                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    581987000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      581987000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    581987000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5832     77.41%     77.41% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1702     22.59%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7534                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        73398                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        73398                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7534                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7534                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        80932                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24893776                       # DTB read hits
system.cpu0.dtb.read_misses                     66568                       # DTB read misses
system.cpu0.dtb.write_hits                   18528826                       # DTB write hits
system.cpu0.dtb.write_misses                     6830                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3826                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1295                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2023                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      643                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24960344                       # DTB read accesses
system.cpu0.dtb.write_accesses               18535656                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43422602                       # DTB hits
system.cpu0.dtb.misses                          73398                       # DTB misses
system.cpu0.dtb.accesses                     43496000                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     4162                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                4162                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3838                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         4162                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           4162    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         4162                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2674                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12829.655946                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 12107.498542                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5222.854689                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2410     90.13%     90.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          239      8.94%     99.07% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           23      0.86%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2674                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    581277500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      581277500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    581277500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2355     88.07%     88.07% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          319     11.93%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2674                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4162                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4162                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6836                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    71465911                       # ITB inst hits
system.cpu0.itb.inst_misses                      4162                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2452                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     8217                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                71470073                       # ITB inst accesses
system.cpu0.itb.hits                         71465911                       # DTB hits
system.cpu0.itb.misses                           4162                       # DTB misses
system.cpu0.itb.accesses                     71470073                       # DTB accesses
system.cpu0.numCycles                       248898522                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  112980792                       # Number of instructions committed
system.cpu0.committedOps                    136605971                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8918624                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1867                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5449022663                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.203016                       # CPI: cycles per instruction
system.cpu0.ipc                              0.453923                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1869                       # number of quiesce instructions executed
system.cpu0.tickCycles                      199912219                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       48986303                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           760179                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          497.990908                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           41826926                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           760691                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            54.985436                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        600550000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.990908                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972638                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.972638                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         86810511                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        86810511                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23283800                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23283800                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17355484                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17355484                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329213                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       329213                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374953                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374953                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370901                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       370901                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     40639284                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        40639284                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     40968497                       # number of overall hits
system.cpu0.dcache.overall_hits::total       40968497                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       494585                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       494585                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       604894                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       604894                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141990                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       141990                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21416                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21416                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20509                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20509                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1099479                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1099479                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1241469                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1241469                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6989932000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6989932000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12583639500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  12583639500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328970000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    328970000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    535273000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    535273000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       491000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       491000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  19573571500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  19573571500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  19573571500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  19573571500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     23778385                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23778385                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17960378                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17960378                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471203                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       471203                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396369                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396369                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391410                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391410                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     41738763                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     41738763                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     42209966                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     42209966                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020800                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.020800                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033679                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033679                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301335                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301335                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054030                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054030                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052398                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052398                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026342                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026342                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029412                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029412                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14132.923562                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14132.923562                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20803.048964                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20803.048964                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.945088                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.945088                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26099.419767                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26099.419767                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17802.587862                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17802.587862                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.460137                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15766.460137                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       760179                       # number of writebacks
system.cpu0.dcache.writebacks::total           760179                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        76321                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        76321                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266412                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       266412                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14897                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14897                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       342733                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       342733                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       342733                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       342733                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       418264                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       418264                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       338482                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       338482                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108425                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       108425                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6519                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6519                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20509                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20509                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       756746                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       756746                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       865171                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       865171                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32043                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60768                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5296846500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5296846500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7120379000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7120379000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1808041000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1808041000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103110500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103110500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    514774000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    514774000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       481000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       481000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12417225500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  12417225500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14225266500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  14225266500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702942500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702942500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452503000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5452503000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12155445500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12155445500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017590                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017590                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018846                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018846                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230103                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230103                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016447                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016447                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052398                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052398                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018131                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.018131                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020497                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020497                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12663.883337                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12663.883337                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21036.211674                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21036.211674                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16675.499193                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16675.499193                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15816.919773                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15816.919773                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25099.907358                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25099.907358                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16408.709792                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16408.709792                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16442.144385                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16442.144385                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209185.859626                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209185.859626                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189817.336815                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189817.336815                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200030.369602                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200030.369602                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          2044142                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.727750                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           69412626                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          2044654                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            33.948348                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6975539000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.727750                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999468                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999468                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        144959270                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       144959270                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     69412626                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       69412626                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     69412626                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        69412626                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     69412626                       # number of overall hits
system.cpu0.icache.overall_hits::total       69412626                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      2044673                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2044673                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      2044673                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2044673                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      2044673                       # number of overall misses
system.cpu0.icache.overall_misses::total      2044673                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20581599000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  20581599000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  20581599000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  20581599000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  20581599000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  20581599000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     71457299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     71457299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     71457299                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     71457299                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     71457299                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     71457299                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028614                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028614                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028614                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028614                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028614                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028614                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10065.961159                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10065.961159                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10065.961159                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10065.961159                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      2044142                       # number of writebacks
system.cpu0.icache.writebacks::total          2044142                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2044673                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      2044673                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      2044673                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      2044673                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      2044673                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      2044673                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3917                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19559263000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  19559263000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19559263000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  19559263000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19559263000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  19559263000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557356500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    557356500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028614                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028614                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028614                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9565.961403                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1928199                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1928402                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          177                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       245070                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          307107                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16117.232598                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4904017                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          323243                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           15.171301                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.112164                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.295680                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.052107                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1300.772647                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.900642                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003680                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000003                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.079393                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983718                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          975                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15154                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          320                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          419                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          227                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4177                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8282                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2255                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059509                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924927                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        93492271                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       93492271                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        89943                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5714                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         95657                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       509380                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       509380                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      2249647                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      2249647                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233063                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       233063                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1974299                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1974299                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       431967                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       431967                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        89943                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5714                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1974299                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       665030                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2734986                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        89943                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5714                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1974299                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       665030                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2734986                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          730                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          113                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          843                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56685                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        56685                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20508                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20508                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48745                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        48745                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        70374                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        70374                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101234                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101234                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          730                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          113                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        70374                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       149979                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       221196                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          730                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          113                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        70374                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       149979                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       221196                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     34979500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2794000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     37773500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    198503500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    198503500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     45129500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     45129500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       464999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       464999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3219724000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   3219724000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4513596000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4513596000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550732497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550732497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     34979500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2794000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4513596000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6770456497                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  11321825997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     34979500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2794000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4513596000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6770456497                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  11321825997                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        90673                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5827                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        96500                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       509380                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       509380                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      2249647                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      2249647                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56685                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56685                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20508                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20508                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281808                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       281808                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2044673                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      2044673                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       533201                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       533201                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        90673                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5827                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2044673                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       815009                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2956182                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        90673                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5827                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2044673                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       815009                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2956182                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.008736                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.172972                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.172972                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034418                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034418                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.189861                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.189861                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034418                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.184021                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.074825                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034418                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.184021                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.074825                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44808.422301                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3501.869983                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3501.869983                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2200.580261                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2200.580261                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       464999                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       464999                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66052.395117                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66052.395117                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64137.266604                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64137.266604                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35074.505571                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35074.505571                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 51184.587411                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 51184.587411                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       238189                       # number of writebacks
system.cpu0.l2cache.writebacks::total          238189                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5772                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5772                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           79                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           79                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          597                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          597                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           79                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6369                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6448                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           79                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6369                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6448                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          730                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          113                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          843                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264088                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       264088                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56685                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56685                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20508                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20508                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42973                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        42973                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        70295                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        70295                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100637                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100637                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          730                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          113                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70295                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143610                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       214748                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          730                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          113                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70295                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143610                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264088                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       478836                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35960                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64685                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     32715500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21010993372                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1525168000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1525168000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    360192000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    360192000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       404999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       404999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2462258500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2462258500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4089276000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4089276000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2913504497                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2913504497                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4089276000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5375762997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   9497754497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4089276000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5375762997                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  30508747869                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6446417500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6972437500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5236548000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5236548000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11682965500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12208985500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008736                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152490                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152490                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034380                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.188741                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.188741                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072644                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.161978                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38808.422301                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79560.575914                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26906.024521                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26906.024521                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17563.487420                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17563.487420                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       404999                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       404999                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57297.803272                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57297.803272                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58173.070631                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28950.629460                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28950.629460                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44227.440987                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63714.398811                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201180.210967                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193894.257508                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182299.321149                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182299.321149                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192255.224789                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188745.234598                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      5764816                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2905184                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        45291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       351229                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       346765                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4464                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        143291                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2770361                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28725                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28725                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       748097                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      2249647                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       247676                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       331668                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87164                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42906                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114222                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       300767                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       297392                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2044673                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       607119                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3062                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6104641                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2759378                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13827                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       189965                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          9067811                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    259587264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104603354                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23308                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       362692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         364576618                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1079592                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4075784                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.104187                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.309067                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3655604     89.69%     89.69% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            415716     10.20%     99.89% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4464      0.11%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4075784                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    5775269994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115824460                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   3073569625                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1308368315                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      8011477                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     99320942                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                3602112                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2032281                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           210658                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2218631                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1453392                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            65.508505                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 748126                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             55361                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    22520                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               22520                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18297                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4223                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        22520                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          22520    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        22520                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1840                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11809.782609                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11060.962968                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6551.399815                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1685     91.58%     91.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          142      7.72%     99.29% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.43%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.16%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1840                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1558893032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1558893032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1558893032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1331     72.34%     72.34% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          509     27.66%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1840                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22520                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22520                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1840                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1840                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3580818                       # DTB read hits
system.cpu1.dtb.read_misses                     20748                       # DTB read misses
system.cpu1.dtb.write_hits                    2975375                       # DTB write hits
system.cpu1.dtb.write_misses                     1772                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1719                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       96                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   254                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3601566                       # DTB read accesses
system.cpu1.dtb.write_accesses                2977147                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6556193                       # DTB hits
system.cpu1.dtb.misses                          22520                       # DTB misses
system.cpu1.dtb.accesses                      6578713                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1949                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1949                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          152                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1797                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1949                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1949    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1949                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          843                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11825.029656                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11322.074300                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4470.335302                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          130     15.42%     15.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          558     66.19%     81.61% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          110     13.05%     94.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           21      2.49%     97.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            4      0.47%     97.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           10      1.19%     98.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            2      0.24%     99.05% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.71%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          843                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1559948532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1559948532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1559948532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          703     83.39%     83.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          140     16.61%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          843                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1949                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1949                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          843                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          843                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2792                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     6911047                       # ITB inst hits
system.cpu1.itb.inst_misses                      1949                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     907                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1031                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 6912996                       # ITB inst accesses
system.cpu1.itb.hits                          6911047                       # DTB hits
system.cpu1.itb.misses                           1949                       # DTB misses
system.cpu1.itb.accesses                      6912996                       # DTB accesses
system.cpu1.numCycles                        40490463                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   14000678                       # Number of instructions committed
system.cpu1.committedOps                     17158102                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1376852                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5656768220                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.892036                       # CPI: cycles per instruction
system.cpu1.ipc                              0.345777                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
system.cpu1.tickCycles                       27318087                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       13172376                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           156172                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          474.293359                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6205519                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           156527                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            39.645039                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      91623607000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.293359                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.926354                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.926354                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          304                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         13166537                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        13166537                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3257703                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3257703                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2730447                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2730447                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42566                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        42566                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70436                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        70436                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61872                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        61872                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5988150                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5988150                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6030716                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6030716                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       134164                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       134164                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       121295                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       121295                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24483                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24483                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16576                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16576                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23384                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23384                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       255459                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        255459                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       279942                       # number of overall misses
system.cpu1.dcache.overall_misses::total       279942                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2171565000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2171565000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4482158000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4482158000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319581000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    319581000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    639162500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    639162500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1395500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1395500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6653723000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6653723000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6653723000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6653723000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3391867                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3391867                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2851742                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2851742                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67049                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        67049                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87012                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        87012                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85256                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        85256                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6243609                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6243609                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6310658                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6310658                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039555                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.039555                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042534                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.042534                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.365151                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.365151                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190502                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190502                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274280                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274280                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040915                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.040915                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044360                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044360                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16185.899347                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16185.899347                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36952.537203                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 36952.537203                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19279.741795                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19279.741795                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27333.326206                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27333.326206                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26046.148306                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26046.148306                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23768.219846                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23768.219846                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       156173                       # number of writebacks
system.cpu1.dcache.writebacks::total           156173                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12677                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        12677                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        41645                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        41645                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11699                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11699                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        54322                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        54322                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        54322                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        54322                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       121487                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       121487                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79650                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        79650                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23961                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23961                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4877                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4877                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23384                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23384                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       201137                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       201137                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       225098                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       225098                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2976                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5287                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1847735500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1847735500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2733456500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2733456500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    448084000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    448084000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87974000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87974000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    615791500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    615791500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1382500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1382500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4581192000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4581192000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5029276000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5029276000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389353500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389353500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251607000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251607000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    640960500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    640960500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035817                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035817                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027930                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027930                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.357366                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.357366                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056050                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056050                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274280                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274280                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032215                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.032215                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035669                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035669                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15209.326924                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15209.326924                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34318.349027                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34318.349027                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18700.555069                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18700.555069                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18038.548288                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18038.548288                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26333.882142                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26333.882142                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22776.475735                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22776.475735                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22342.606331                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22342.606331                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130831.149194                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130831.149194                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108873.647772                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108873.647772                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121233.308114                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121233.308114                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           857356                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.135276                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6052000                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           857868                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.054698                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      73316283000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135276                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974874                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974874                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         14677604                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        14677604                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      6052000                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6052000                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6052000                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6052000                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6052000                       # number of overall hits
system.cpu1.icache.overall_hits::total        6052000                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       857868                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       857868                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       857868                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        857868                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       857868                       # number of overall misses
system.cpu1.icache.overall_misses::total       857868                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7591768500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7591768500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7591768500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7591768500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7591768500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7591768500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      6909868                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      6909868                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      6909868                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      6909868                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      6909868                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      6909868                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124151                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.124151                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124151                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.124151                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124151                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.124151                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8849.576508                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8849.576508                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8849.576508                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8849.576508                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       857356                       # number of writebacks
system.cpu1.icache.writebacks::total           857356                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       857868                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       857868                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       857868                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       857868                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       857868                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       857868                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7162834500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7162834500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7162834500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7162834500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7162834500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7162834500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     15350500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124151                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.124151                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.124151                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8349.576508                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       119508                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       119564                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           49                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        48908                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           37772                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15172.719385                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1844058                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           52876                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           34.875142                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.461893                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.967636                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.078899                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   403.210957                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.899564                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001890                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.024610                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.926069                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          917                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14102                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           47                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          870                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           53                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1682                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12104                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.055969                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.860718                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        34274864                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       34274864                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23931                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2459                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         26390                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        94554                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        94554                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       900775                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       900775                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17922                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        17922                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       845092                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       845092                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        83494                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        83494                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23931                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2459                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       845092                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       101416                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         972898                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23931                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2459                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       845092                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       101416                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        972898                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          683                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          243                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          926                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29302                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29302                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23383                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23383                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32429                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32429                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12776                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        12776                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        66828                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        66828                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          683                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          243                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        12776                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        99257                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       112959                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          683                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          243                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        12776                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        99257                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       112959                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     15528000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4905000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     20433000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65464500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     65464500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59174500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59174500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1363000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1363000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1719425500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1719425500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    735868000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    735868000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1599140998                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1599140998                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     15528000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4905000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    735868000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3318566498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4074867498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     15528000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4905000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    735868000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3318566498                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4074867498                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24614                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2702                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        27316                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        94554                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        94554                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       900775                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       900775                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29302                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29302                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23383                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23383                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50351                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50351                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       857868                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       857868                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       150322                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       150322                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24614                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2702                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       857868                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       200673                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1085857                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24614                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2702                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       857868                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       200673                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1085857                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.033900                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.644059                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.644059                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.014893                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.014893                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.444566                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.444566                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.014893                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.494621                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.104028                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.014893                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.494621                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.104028                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22065.874730                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2234.130776                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2234.130776                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2530.663302                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2530.663302                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1363000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1363000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53021.230997                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53021.230997                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57597.683156                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57597.683156                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23929.206291                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23929.206291                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 36073.863065                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 36073.863065                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           91                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    22.750000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        29006                       # number of writebacks
system.cpu1.l2cache.writebacks::total           29006                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          239                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          239                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           41                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           41                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          280                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          289                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          280                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          289                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          683                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          243                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          926                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20213                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        20213                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29302                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29302                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23383                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23383                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32190                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32190                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        12767                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        12767                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66787                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66787                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          683                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          243                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12767                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        98977                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       112670                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          683                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          243                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12767                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98977                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20213                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       132883                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3088                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5399                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14877000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    967332273                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    596044000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    596044000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    438887000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    438887000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1502190000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1502190000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    658879500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    658879500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1196481498                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1196481498                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    658879500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2698671498                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3372427998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    658879500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2698671498                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4339760271                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365478500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    379933000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234145500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234145500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599624000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614078500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.033900                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639312                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639312                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014882                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.444293                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103761                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122376                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16065.874730                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47856.937268                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.410143                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.410143                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18769.490656                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18769.490656                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1285000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1285000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46666.356011                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46666.356011                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51608.012846                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.886101                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.886101                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29931.907322                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32658.506137                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122808.635753                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123035.297927                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101317.827780                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101317.827780                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113414.790997                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113739.303575                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      2131909                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1073389                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18199                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       177399                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       176178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1221                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         33577                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1078735                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2311                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2311                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       124920                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       900775                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        97230                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        24545                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        71695                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41696                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84990                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57514                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55014                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       857868                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       234653                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           35                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2557119                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       745420                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6448                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        51357                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3360344                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    108744896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25394242                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10808                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        98456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         134248402                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     381517                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1451505                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.140526                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.349944                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1248752     86.03%     86.03% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            201532     13.88%     99.92% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1221      0.08%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1451505                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    2095009994                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     78651519                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1287084271                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    333125737                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3746000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     26768449                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483988                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             51019501                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               109500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               572500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               45500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6101000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              169500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32834001                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              123500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186304797                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               32500                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36449                       # number of replacements
system.iocache.tags.tagsinuse               14.470000                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         272418338000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.470000                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904375                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904375                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31658876                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31658876                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4735531921                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4735531921                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31658876                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31658876                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31658876                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31658876                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 130283.440329                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 130283.440329                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130729.127678                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130729.127678                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130283.440329                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130283.440329                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           628                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   73                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.602740                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19508876                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19508876                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2924331921                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2924331921                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     19508876                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     19508876                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     19508876                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     19508876                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80283.440329                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 80283.440329                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80729.127678                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80729.127678                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   131732                       # number of replacements
system.l2c.tags.tagsinuse                63242.215263                       # Cycle average of tags in use
system.l2c.tags.total_refs                     477411                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   195803                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.438221                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13388.492550                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    80.863480                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.040287                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     9301.116819                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2921.908325                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33330.007466                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.315084                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1918.660878                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      548.645359                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1744.165016                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.204292                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001234                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.141924                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.044585                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.508576                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000127                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.029276                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008372                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.026614                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.965000                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29065                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34948                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          132                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4807                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        24126                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           58                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3276                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        31196                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.443497                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000885                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.533264                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6405394                       # Number of tag accesses
system.l2c.tags.data_accesses                 6405394                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       267195                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          267195                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           33822                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2200                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               36022                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2272                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           961                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3233                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4378                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1264                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5642                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          435                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker          108                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        47657                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        51900                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        49884                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           81                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           16                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         9621                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         5534                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3616                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           168852                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           435                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           108                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               47657                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56278                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        49884                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            81                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            16                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                9621                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6798                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3616                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  174494                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          435                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          108                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              47657                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56278                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        49884                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           81                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           16                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               9621                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6798                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3616                       # number of overall hits
system.l2c.overall_hits::total                 174494                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         10312                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2381                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12693                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          744                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1293                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2037                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11496                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8171                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19667                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          140                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        22638                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9851                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133540                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           12                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3146                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1600                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5301                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         176229                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          140                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22638                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21347                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133540                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3146                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9771                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5301                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195896                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          140                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22638                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21347                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133540                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           12                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3146                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9771                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5301                       # number of overall misses
system.l2c.overall_misses::total               195896                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     32489500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6475500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     38965000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      5652000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3486500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      9138500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1701392500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1078681000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2780073500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     19211500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       133000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2956600500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1349455000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  20123328515                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      1634000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    418631500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    219796500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    890020222                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  25978810737                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     19211500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2956600500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3050847500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  20123328515                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1634000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    418631500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1298477500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    890020222                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     28758884237                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     19211500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2956600500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3050847500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  20123328515                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1634000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    418631500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1298477500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    890020222                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    28758884237                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       267195                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       267195                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        44134                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4581                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           48715                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         3016                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2254                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5270                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15874                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9435                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25309                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          575                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker          109                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        70295                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61751                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       183424                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           93                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           16                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        12767                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         7134                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8917                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       345081                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          575                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          109                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           70295                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           77625                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       183424                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           93                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           16                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           12767                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           16569                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8917                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              370390                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          575                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          109                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          70295                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          77625                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       183424                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           93                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           16                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          12767                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          16569                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8917                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             370390                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.233652                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.519756                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.260556                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.246684                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.573647                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.386528                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.724203                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.866031                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.777075                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.322043                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159528                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.246417                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.224278                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.510689                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.322043                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.275002                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.246417                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.589716                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.528891                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.322043                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.275002                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.246417                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.589716                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.528891                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3150.649728                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2719.655607                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3069.802253                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7596.774194                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2696.442382                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4486.254296                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147998.651705                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132013.339860                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 141357.273606                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       137225                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130603.432282                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136986.600345                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150691.392205                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133067.863954                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 137372.812500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167896.665158                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 147415.072077                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       137225                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130603.432282                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 142916.920410                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150691.392205                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133067.863954                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 132890.952820                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167896.665158                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 146806.898747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       137225                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130603.432282                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 142916.920410                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150691.392205                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133067.863954                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 132890.952820                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167896.665158                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 146806.898747                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               305                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     50.833333                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102076                       # number of writebacks
system.l2c.writebacks::total                   102076                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            8                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3577                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3577                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        10312                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2381                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12693                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          744                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1293                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2037                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11496                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8171                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19667                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          140                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22630                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9851                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133540                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           12                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3139                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1600                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5301                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       176214                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          140                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22630                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21347                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133540                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3139                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9771                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5301                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195881                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          140                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22630                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21347                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133540                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3139                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9771                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5301                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195881                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        39045                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31036                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        70081                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    779392000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    179030000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    958422000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     57592000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     99091000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    156683000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1586432500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    996971000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2583403500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     17811500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       123000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2729644000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1250945000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18787928515                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      1514000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    386686000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    203796500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    837010222                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  24215458737                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     17811500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2729644000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2837377500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18787928515                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1514000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    386686000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1200767500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    837010222                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  26798862237                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     17811500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2729644000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2837377500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18787928515                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1514000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    386686000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1200767500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    837010222                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  26798862237                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869618000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    311913500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6637396500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4748092000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    194851500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4942943500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10617710000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    506765000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11580340000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.233652                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.519756                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.260556                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.246684                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.573647                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.386528                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.724203                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.866031                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.777075                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159528                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.224278                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.510645                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.528851                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.528851                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75581.070597                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75191.096178                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75507.917750                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77408.602151                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76636.504254                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76918.507609                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137998.651705                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122013.339860                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 131357.273606                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.600345                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127372.812500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137420.742603                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183179.415161                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104915.405314                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169993.507491                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165294.760661                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84314.798788                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159264.837608                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174725.348868                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95905.563967                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 165242.219717                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               39045                       # Transaction distribution
system.membus.trans_dist::ReadResp             215502                       # Transaction distribution
system.membus.trans_dist::WriteReq              31036                       # Transaction distribution
system.membus.trans_dist::WriteResp             31036                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       138282                       # Transaction distribution
system.membus.trans_dist::CleanEvict            17700                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            74095                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40637                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14846                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40045                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19551                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        176457                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14226                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678987                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       801187                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108925                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108925                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 910112                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28452                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19316644                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19509252                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21827396                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           120950                       # Total snoops (count)
system.membus.snoop_fanout::samples            593773                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  593773    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              593773                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91220498                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12309500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1009592824                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1175000125                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64118281                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      1045381                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       564426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       153843                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20977                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        20003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          974                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              39048                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            502086                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31036                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31036                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       405496                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          105907                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          110001                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43870                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         153871                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51160                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51160                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       463053                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1307707                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       268101                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1575808                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36951502                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4337654                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41289156                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          448414                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           942644                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.339212                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.475620                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 623862     66.18%     66.18% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 317808     33.71%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    974      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             942644                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          904161512                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           342622                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         693453750                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         213389277                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------