path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.647778                       # Number of seconds simulated
sim_ticks                                2647778082500                       # Number of ticks simulated
final_tick                               2647778082500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 109262                       # Simulator instruction rate (inst/s)
host_op_rate                                   132319                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2267003011                       # Simulator tick rate (ticks/s)
host_mem_usage                                 618500                       # Number of bytes of host memory used
host_seconds                                  1167.96                       # Real time elapsed on the host
sim_insts                                   127613917                       # Number of instructions simulated
sim_ops                                     154544077                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         8192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1505216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1244784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8319232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           374976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           749140                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       607232                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12811716                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1505216                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       374976                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1880192                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9040448                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9058012                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          128                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             23519                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             19972                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       129988                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           30                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5859                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             11726                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         9488                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                200726                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          141257                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               145648                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3094                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            24                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              568483                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              470124                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3141967                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              141619                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              282932                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       229336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              363                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4838667                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         568483                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         141619                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             710102                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3414353                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6618                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3420986                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3414353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             568483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             476742                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3141967                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             141619                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             282947                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       229336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             363                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                8259653                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        200726                       # Number of read requests accepted
system.physmem.writeReqs                       145648                       # Number of write requests accepted
system.physmem.readBursts                      200726                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     145648                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12837568                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9070080                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12811716                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9058012                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12684                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12558                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12677                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12470                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15173                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12439                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12705                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12895                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12483                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12862                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12103                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11319                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11938                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12281                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12069                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11931                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9144                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9177                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9224                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8920                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8442                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8744                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9263                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9163                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8908                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9183                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8711                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8187                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8717                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8673                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8851                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8413                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
system.physmem.totGap                    2647777471000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     553                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  200145                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 141257                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     87468                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11522                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9750                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7877                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6392                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4696                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       756                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      239                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      160                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2893                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       90                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        94963                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      230.695997                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     131.239554                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     294.689609                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52509     55.29%     55.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18085     19.04%     74.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6234      6.56%     80.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3686      3.88%     84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2895      3.05%     87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1483      1.56%     89.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          908      0.96%     90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1023      1.08%     91.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8140      8.57%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          94963                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7063                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.398839                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      555.406402                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7061     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7063                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7063                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.065128                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.613340                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.212436                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5945     84.17%     84.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             392      5.55%     89.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              71      1.01%     90.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              48      0.68%     91.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             279      3.95%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              27      0.38%     95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.27%     96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              25      0.35%     96.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              16      0.23%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.17%     96.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               3      0.04%     96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.10%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             160      2.27%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.08%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.07%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.10%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.06%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.04%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.11%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.06%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7063                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5391615341                       # Total ticks spent queuing
system.physmem.totMemAccLat                9152621591                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1002935000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26879.19                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45629.19                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.85                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.43                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.84                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.42                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166580                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80763                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  56.97                       # Row buffer hit rate for writes
system.physmem.avgGap                      7644273.16                       # Average gap between requests
system.physmem.pageHitRate                      72.25                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  370341720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  202071375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 808080000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                467058960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           172939896480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            79567681680                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1518869897250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1773225027465                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.703351                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2526645938707                       # Time in different power states
system.physmem_0.memoryStateTime::REF     88415080000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32716967293                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  347578560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  189651000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 756490800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                451286640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           172939896480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            78874475895                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1519477980750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1773037360125                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.632470                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2527659145749                       # Time in different power states
system.physmem_1.memoryStateTime::REF     88415080000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31702650501                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          193                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          314                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              508                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          193                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          314                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          508                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          193                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          314                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             508                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               34732065                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         16497595                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1496295                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            19609177                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               10269070                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            52.368695                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               11117365                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            739154                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4170441                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           3984607                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          185834                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        94839                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    65243                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               65243                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44492                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        20751                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        65243                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          65243    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        65243                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6699                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5808.192470                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6323     94.39%     94.39% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          330      4.93%     99.31% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           32      0.48%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            7      0.10%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            3      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.04%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6699                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    338010000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      338010000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    338010000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5176     77.27%     77.27% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1523     22.73%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6699                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65243                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65243                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6699                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6699                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        71942                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23418517                       # DTB read hits
system.cpu0.dtb.read_misses                     59363                       # DTB read misses
system.cpu0.dtb.write_hits                   17357852                       # DTB write hits
system.cpu0.dtb.write_misses                     5880                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3435                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1178                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1722                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      516                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                23477880                       # DTB read accesses
system.cpu0.dtb.write_accesses               17363732                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         40776369                       # DTB hits
system.cpu0.dtb.misses                          65243                       # DTB misses
system.cpu0.dtb.accesses                     40841612                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     4001                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                4001                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          306                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3695                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         4001                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           4001    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         4001                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2427                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4734.087286                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          373     15.37%     15.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1885     77.67%     93.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          118      4.86%     97.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           27      1.11%     99.01% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           22      0.91%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2427                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    337545500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      337545500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    337545500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2126     87.60%     87.60% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          301     12.40%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2427                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4001                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4001                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2427                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2427                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6428                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    68314752                       # ITB inst hits
system.cpu0.itb.inst_misses                      4001                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2164                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7135                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                68318753                       # ITB inst accesses
system.cpu0.itb.hits                         68314752                       # DTB hits
system.cpu0.itb.misses                           4001                       # DTB misses
system.cpu0.itb.accesses                     68318753                       # DTB accesses
system.cpu0.numPwrStateTransitions               4126                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         2063                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1227700157.144935                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   21500702795.368797                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1198     58.07%     58.07% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          860     41.69%     99.76% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.05%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            3      0.15%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499984309000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           2063                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   115032658310                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       230068064                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  106706103                       # Number of instructions committed
system.cpu0.committedOps                    129024022                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8506641                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     2063                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5065528558                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.156091                       # CPI: cycles per instruction
system.cpu0.ipc                              0.463802                       # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass               2272      0.00%      0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu               87919988     68.14%     68.14% # Class of committed instruction
system.cpu0.op_class_0::IntMult                105727      0.08%     68.23% # Class of committed instruction
system.cpu0.op_class_0::IntDiv                      0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatMult                   0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt                   0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd                     0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu                     0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp                     0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt                     0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdMult                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdShift                   0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt                    0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc            7151      0.01%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult               0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     68.23% # Class of committed instruction
system.cpu0.op_class_0::MemRead              22900542     17.75%     85.98% # Class of committed instruction
system.cpu0.op_class_0::MemWrite             18088342     14.02%    100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::total               129024022                       # Class of committed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2063                       # number of quiesce instructions executed
system.cpu0.tickCycles                      178511666                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       51556398                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           681177                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          487.337065                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           39381714                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           681689                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            57.770793                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        356009000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   487.337065                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.951830                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.951830                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         81578447                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        81578447                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     21978387                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       21978387                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     16273218                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16273218                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306177                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       306177                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       357355                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       357355                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352292                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       352292                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     38251605                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        38251605                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     38557782                       # number of overall hits
system.cpu0.dcache.overall_hits::total       38557782                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       418335                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       418335                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       561531                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       561531                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131453                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       131453                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20802                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20802                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21460                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21460                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       979866                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        979866                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1111319                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1111319                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5562272000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5562272000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10028849500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10028849500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328076000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    328076000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    523772000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    523772000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       516000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       516000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  15591121500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  15591121500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  15591121500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  15591121500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     22396722                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     22396722                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     16834749                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     16834749                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       437630                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       437630                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378157                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       378157                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373752                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       373752                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     39231471                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     39231471                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     39669101                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     39669101                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.018678                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.018678                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033355                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033355                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300375                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300375                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055009                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055009                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.057418                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.057418                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024977                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.024977                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028015                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.028015                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       681177                       # number of writebacks
system.cpu0.dcache.writebacks::total           681177                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        44450                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        44450                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       246335                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       246335                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14695                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14695                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       290785                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       290785                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       290785                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       290785                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       373885                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       373885                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       315196                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       315196                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        98829                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        98829                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6107                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6107                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21460                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21460                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       689081                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       689081                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       787910                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       787910                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29629                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29629                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26357                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26357                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55986                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55986                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4452451000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4452451000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5571993500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5571993500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1619437000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1619437000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94023500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94023500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    502325000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    502325000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       503000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       503000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10024444500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10024444500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11643881500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  11643881500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6101487500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6101487500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6101487500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6101487500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016694                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016694                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018723                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018723                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225828                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225828                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016149                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016149                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.057418                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.057418                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017564                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017564                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019862                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.019862                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1887196                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.757846                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           66419655                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1887708                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.185344                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6638125000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.757846                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999527                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999527                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        138502472                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       138502472                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     66419655                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       66419655                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     66419655                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        66419655                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     66419655                       # number of overall hits
system.cpu0.icache.overall_hits::total       66419655                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1887721                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1887721                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1887721                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1887721                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1887721                       # number of overall misses
system.cpu0.icache.overall_misses::total      1887721                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17836461000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  17836461000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  17836461000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  17836461000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  17836461000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  17836461000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     68307376                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     68307376                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     68307376                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     68307376                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     68307376                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     68307376                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027636                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027636                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027636                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027636                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027636                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027636                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9448.674354                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9448.674354                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9448.674354                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9448.674354                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9448.674354                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9448.674354                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1887196                       # number of writebacks
system.cpu0.icache.writebacks::total          1887196                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1887721                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1887721                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1887721                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1887721                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1887721                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1887721                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3448                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3448                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16892601000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16892601000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16892601000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16892601000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16892601000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16892601000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    319413000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    319413000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027636                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027636                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027636                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8948.674619                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8948.674619                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8948.674619                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1767222                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1767306                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           74                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       225214                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          281957                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16020.304669                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4495555                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          298080                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           15.081706                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.898882                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.073768                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   805.233405                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.924872                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003778                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.049148                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.977802                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1000                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15110                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           18                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          315                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          390                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          277                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          335                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4038                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7911                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2755                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061035                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.922241                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        85783129                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       85783129                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77844                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5474                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         83318                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       465182                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       465182                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      2062277                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      2062277                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       213330                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       213330                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1827339                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1827339                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       378100                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       378100                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77844                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5474                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1827339                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       591430                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2502087                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77844                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5474                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1827339                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       591430                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2502087                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          760                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          121                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          881                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        57605                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        57605                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        21456                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        21456                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44266                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44266                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        60382                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        60382                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       100716                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       100716                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          760                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          121                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        60382                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144982                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       206245                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          760                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          121                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        60382                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144982                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       206245                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     27717500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2799500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     30517000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    116554500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    116554500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     30031000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     30031000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       482498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       482498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2238448000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2238448000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2969526500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2969526500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2950737493                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2950737493                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     27717500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2799500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2969526500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5189185493                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8189228993                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     27717500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2799500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2969526500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5189185493                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8189228993                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78604                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5595                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        84199                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       465182                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       465182                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      2062277                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      2062277                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        57605                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        57605                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21456                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21456                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257596                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       257596                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1887721                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1887721                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       478816                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       478816                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78604                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5595                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1887721                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       736412                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2708332                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78604                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5595                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1887721                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       736412                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2708332                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009669                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.021626                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.010463                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171843                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171843                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.031987                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.031987                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.210344                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.210344                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009669                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.021626                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.031987                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.196876                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.076152                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009669                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.021626                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.031987                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.196876                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.076152                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34639.046538                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2023.339988                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2023.339988                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1399.655108                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1399.655108                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 120624.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 120624.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50568.110966                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50568.110966                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49179.002020                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49179.002020                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29297.604085                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29297.604085                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49179.002020                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35791.929295                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39706.315271                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49179.002020                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35791.929295                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39706.315271                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches            9085                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       227660                       # number of writebacks
system.cpu0.l2cache.writebacks::total          227660                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2626                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2626                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           53                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           53                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          363                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          363                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           53                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         2989                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3042                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           53                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         2989                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3042                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          760                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          121                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          881                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       247545                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       247545                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        57605                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        57605                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        21456                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        21456                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41640                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41640                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        60329                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        60329                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100353                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100353                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          760                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          121                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        60329                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141993                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       203203                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          760                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          121                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        60329                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141993                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       247545                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       450748                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29629                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        33077                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26357                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26357                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55986                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        59434                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     25231000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14000669196                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14000669196                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1121106500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1121106500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    340294500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    340294500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       404498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       404498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1697761000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1697761000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2606173000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2606173000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2329095993                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2329095993                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2606173000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4026856993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6658260993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2606173000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4026856993                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14000669196                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  20658930189                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5864363500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6156192500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5864363500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6156192500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010463                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.161648                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.161648                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.031959                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.209586                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.209586                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075029                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.166430                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      5292246                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2668157                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        40914                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       334901                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       330475                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4426                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        126809                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2542571                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        26357                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26357                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       693110                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      2103191                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       223137                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       294264                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        92982                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43850                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       116200                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       275510                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       272175                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1887721                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       569608                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3113                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5669533                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2525108                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13291                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       164598                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          8372530                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    241815296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     94996751                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22380                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         337148843                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1025467                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18711896                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      3771293                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.106316                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.312026                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3374771     89.49%     89.49% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            392096     10.40%     99.88% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4426      0.12%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3771293                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    5293903990                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114422325                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2837181638                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1188012916                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7701489                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     86027432                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                5469499                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3374978                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           316517                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             3346860                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                2136825                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            63.845664                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 972408                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             68961                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups         195238                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits            132437                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           62801                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        28788                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    30404                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               30404                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        23807                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6597                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        30404                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          30404    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        30404                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2736                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8821.385005                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767         2714     99.20%     99.20% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535           14      0.51%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303            4      0.15%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071            3      0.11%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2736                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1954228032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1954228032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1954228032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         2033     74.31%     74.31% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          703     25.69%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2736                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30404                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30404                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2736                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2736                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        33140                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     5173966                       # DTB read hits
system.cpu1.dtb.read_misses                     27871                       # DTB read misses
system.cpu1.dtb.write_hits                    4222414                       # DTB write hits
system.cpu1.dtb.write_misses                     2533                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2009                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      306                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   555                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 5201837                       # DTB read accesses
system.cpu1.dtb.write_accesses                4224947                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          9396380                       # DTB hits
system.cpu1.dtb.misses                          30404                       # DTB misses
system.cpu1.dtb.accesses                      9426784                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     2488                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2488                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2306                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2488                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2488    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2488                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1135                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5007.072010                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095            4      0.35%      0.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          156     13.74%     14.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          686     60.44%     74.54% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          210     18.50%     93.04% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           30      2.64%     95.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     95.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           21      1.85%     97.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.70%     98.41% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959           15      1.32%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.26%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1135                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1954817532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1954817532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1954817532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          965     85.02%     85.02% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          170     14.98%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1135                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2488                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2488                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1135                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1135                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3623                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    10174079                       # ITB inst hits
system.cpu1.itb.inst_misses                      2488                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1107                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1891                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                10176567                       # ITB inst accesses
system.cpu1.itb.hits                         10174079                       # DTB hits
system.cpu1.itb.misses                           2488                       # DTB misses
system.cpu1.itb.accesses                     10176567                       # DTB accesses
system.cpu1.numPwrStateTransitions               5445                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2723                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    962192053.212266                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   19383110303.670654                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1861     68.34%     68.34% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          855     31.40%     99.74% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            3      0.11%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            4      0.15%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 499966911836                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2723                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    27729121603                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                        55461727                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   20907814                       # Number of instructions committed
system.cpu1.committedOps                     25520055                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1855956                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2723                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5239453402                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.652679                       # CPI: cycles per instruction
system.cpu1.ipc                              0.376977                       # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass                 67      0.00%      0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu               16137166     63.23%     63.23% # Class of committed instruction
system.cpu1.op_class_0::IntMult                 34169      0.13%     63.37% # Class of committed instruction
system.cpu1.op_class_0::IntDiv                      0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatMult                   0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt                   0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd                     0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu                     0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp                     0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt                     0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdMult                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdShift                   0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt                    0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     63.37% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc            4083      0.02%     63.38% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult               0      0.00%     63.38% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     63.38% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     63.38% # Class of committed instruction
system.cpu1.op_class_0::MemRead               4989153     19.55%     82.93% # Class of committed instruction
system.cpu1.op_class_0::MemWrite              4355417     17.07%    100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::total                25520055                       # Class of committed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2723                       # number of quiesce instructions executed
system.cpu1.tickCycles                       37036327                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       18425400                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           231690                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          479.724430                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8932333                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           232024                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.497453                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     109862994000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.724430                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.936962                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.936962                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          334                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           70                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.652344                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18884551                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18884551                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      4750067                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4750067                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3901959                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3901959                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65733                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        65733                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87399                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        87399                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79392                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        79392                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8652026                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8652026                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8717759                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8717759                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       172325                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       172325                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       169730                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       169730                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34831                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        34831                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17668                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17668                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23402                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23402                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       342055                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        342055                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       376886                       # number of overall misses
system.cpu1.dcache.overall_misses::total       376886                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2622225500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2622225500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4369952500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4369952500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    333352000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    333352000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    570866500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    570866500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       547000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       547000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6992178000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6992178000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6992178000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6992178000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4922392                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4922392                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4071689                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4071689                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       100564                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       100564                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105067                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       105067                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102794                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       102794                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8994081                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8994081                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      9094645                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      9094645                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035008                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035008                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.041685                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.041685                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.346357                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.346357                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.168159                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.168159                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227659                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227659                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038031                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038031                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041440                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.041440                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20441.677508                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20441.677508                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18552.501287                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18552.501287                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       231690                       # number of writebacks
system.cpu1.dcache.writebacks::total           231690                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         6182                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total         6182                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        63208                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        63208                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12205                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12205                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        69390                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        69390                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        69390                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        69390                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166143                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       166143                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       106522                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       106522                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33373                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        33373                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5463                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5463                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23402                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23402                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       272665                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       272665                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       306038                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       306038                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5399                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5399                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4698                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4698                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10097                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10097                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2348457500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2348457500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2649909000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2649909000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    556338500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    556338500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     95279500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     95279500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    547474500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    547474500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       537000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       537000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4998366500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4998366500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5554705000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5554705000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    994956000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    994956000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    994956000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    994956000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033752                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033752                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026162                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026162                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331858                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331858                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051995                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051995                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227659                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227659                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030316                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.030316                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033650                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033650                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          1038587                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.233977                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            9132995                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          1039099                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             8.789341                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72888333000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.233977                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973113                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973113                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         21383287                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        21383287                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst      9132995                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        9132995                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      9132995                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         9132995                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      9132995                       # number of overall hits
system.cpu1.icache.overall_hits::total        9132995                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      1039099                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      1039099                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      1039099                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       1039099                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      1039099                       # number of overall misses
system.cpu1.icache.overall_misses::total      1039099                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9377315500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9377315500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9377315500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9377315500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9377315500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9377315500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     10172094                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     10172094                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     10172094                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     10172094                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     10172094                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     10172094                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.102152                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.102152                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.102152                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.102152                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.102152                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.102152                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9024.467832                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9024.467832                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9024.467832                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9024.467832                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9024.467832                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9024.467832                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      1038587                       # number of writebacks
system.cpu1.icache.writebacks::total          1038587                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1039099                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      1039099                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      1039099                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      1039099                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      1039099                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      1039099                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8857766000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   8857766000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8857766000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   8857766000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8857766000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   8857766000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10704000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10704000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10704000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10704000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.102152                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.102152                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.102152                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8524.467832                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8524.467832                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8524.467832                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       276399                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       276459                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           53                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        69493                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           70219                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15563.656432                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           2283330                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           85023                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           26.855439                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    54.124799                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.170471                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1123.538345                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.878041                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003304                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000010                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.068575                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.949930                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1056                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           42                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13706                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          291                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          761                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5206                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         8191                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.064453                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002563                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.836548                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        42757972                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       42757972                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        32984                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         3253                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         36237                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       134317                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       134317                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      1113970                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      1113970                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37754                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        37754                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1012452                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      1012452                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       130088                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       130088                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        32984                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         3253                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1012452                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       167842                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1216531                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        32984                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         3253                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1012452                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       167842                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1216531                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          703                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          237                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          940                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        31976                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        31976                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23401                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23401                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36794                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        36794                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        26647                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        26647                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        74889                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        74889                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          703                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          237                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        26647                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       111683                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       139270                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          703                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          237                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        26647                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       111683                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       139270                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17920000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4860500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     22780500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     79820500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     79820500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     32048000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     32048000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       521000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       521000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1478483000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1478483000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1147386500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1147386500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1827426992                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1827426992                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17920000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4860500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1147386500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3305909992                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4476076992                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17920000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4860500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1147386500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3305909992                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4476076992                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33687                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3490                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        37177                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       134317                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       134317                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      1113970                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      1113970                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31976                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        31976                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23401                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23401                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74548                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        74548                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1039099                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      1039099                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       204977                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       204977                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33687                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3490                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1039099                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       279525                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1355801                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33687                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3490                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1039099                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       279525                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1355801                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020869                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.067908                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.025284                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.493561                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.493561                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025644                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025644                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.365353                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.365353                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020869                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.067908                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025644                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.399546                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.102722                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020869                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.067908                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025644                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.399546                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.102722                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24234.574468                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2496.262822                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2496.262822                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1369.514123                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1369.514123                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       521000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       521000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40182.720009                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40182.720009                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43058.749578                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43058.749578                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24401.807902                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24401.807902                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43058.749578                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29600.834433                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32139.563380                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43058.749578                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29600.834433                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32139.563380                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches            2265                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        42373                       # number of writebacks
system.cpu1.l2cache.writebacks::total           42373                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          331                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          331                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           22                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           22                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          129                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          129                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           22                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          460                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          482                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           22                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          460                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          482                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          703                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          237                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          940                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        38782                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        38782                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        31976                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        31976                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23401                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23401                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        36463                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        36463                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        26625                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        26625                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        74760                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        74760                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          703                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          237                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        26625                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       111223                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       138788                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          703                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          237                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        26625                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       111223                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        38782                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       177570                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5399                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5511                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         4698                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         4698                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10097                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10209                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3438500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     17140500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1312457547                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1312457547                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    566974500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    566974500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    370291999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    370291999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       461000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       461000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1222094000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1222094000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    987020000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    987020000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1373517992                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1373517992                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3438500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    987020000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2595611992                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3599772492                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3438500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    987020000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2595611992                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1312457547                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4912230039                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9808000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    951737000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    961545000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9808000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    951737000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    961545000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025284                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.489121                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.489121                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.025623                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.364724                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.364724                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.397900                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.102366                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.397900                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.130971                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       461000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       461000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      2654318                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1335711                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        21986                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       212975                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       211032                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1943                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         47306                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1331970                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         4698                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         4698                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       177822                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      1135956                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       137781                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        47279                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        75014                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42924                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89713                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        82844                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        80563                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1039099                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       293637                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          236                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3117009                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1002647                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8284                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70688                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          4198628                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    132979072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     35729427                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       134748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         168857207                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     473910                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              5785960                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1814338                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.136111                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.346015                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1569330     86.50%     86.50% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            243065     13.40%     99.89% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1943      0.11%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1814338                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    2620766990                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     87124018                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1558968196                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    456771923                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4794998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     37016968                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31014                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31014                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180872                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48375000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               113500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               329000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                27500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               619500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               45500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6358000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38893000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187720844                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36462                       # number of replacements
system.iocache.tags.tagsinuse               14.359878                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         271405535000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.359878                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.897492                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.897492                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
system.iocache.tags.data_accesses              328320                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36480                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36480                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36480                       # number of overall misses
system.iocache.overall_misses::total            36480                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     33042377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     33042377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4307289467                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4307289467                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4340331844                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4340331844                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4340331844                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4340331844                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36480                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36480                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36480                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36480                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129071.785156                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118978.394846                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118978.394846                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118978.394846                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118978.394846                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            32                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.666667                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36480                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36480                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36480                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36480                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20242377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20242377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2493740476                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2493740476                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2513982853                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2513982853                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2513982853                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2513982853                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68914.003646                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68914.003646                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   135113                       # number of replacements
system.l2c.tags.tagsinuse                63251.941629                       # Cycle average of tags in use
system.l2c.tags.total_refs                     475115                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   198978                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.387777                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   14216.048080                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    74.910809                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.033810                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7426.792759                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2102.106662                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    20.238831                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3811.016358                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1509.520853                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4194.357849                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.216920                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001143                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.113324                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.032076                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.456191                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000309                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.058151                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.023033                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.064001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.965148                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        27324                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           89                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        36452                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          105                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4822                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        22394                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           88                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3262                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        32736                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.416931                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001358                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.556213                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6444953                       # Number of tag accesses
system.l2c.tags.data_accesses                 6444953                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       270033                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          270033                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32996                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            3857                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               36853                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2004                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1040                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3044                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3941                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1936                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5877                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          357                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           67                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        40247                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        47388                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        44871                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          179                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           29                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        20863                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        12359                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8223                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           174583                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           357                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            67                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               40247                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51329                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        44871                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           179                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            29                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               20863                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               14295                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         8223                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  180460                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          357                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           67                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              40247                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51329                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        44871                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          179                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           29                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              20863                       # number of overall hits
system.l2c.overall_hits::cpu1.data              14295                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         8223                       # number of overall hits
system.l2c.overall_hits::total                 180460                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9513                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4300                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             13813                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          964                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1203                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2167                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11039                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8960                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19999                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          128                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        20082                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8636                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       130145                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           30                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         5762                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2791                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         9488                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         177063                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          128                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             20082                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19675                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       130145                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           30                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5762                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             11751                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         9488                       # number of demand (read+write) misses
system.l2c.demand_misses::total                197062                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          128                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            20082                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19675                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       130145                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           30                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5762                       # number of overall misses
system.l2c.overall_misses::cpu1.data            11751                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         9488                       # number of overall misses
system.l2c.overall_misses::total               197062                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     11061000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      7336000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     18397000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1913000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1241000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3154000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1093563000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    738422000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1831985000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     11632000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        84000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1625007000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    768151000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13218838629                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3061500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    480657500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    249182500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1135921938                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  17492536067                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     11632000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        84000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1625007000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1861714000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13218838629                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      3061500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    480657500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    987604500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1135921938                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19324521067                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     11632000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        84000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1625007000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1861714000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13218838629                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      3061500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    480657500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    987604500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1135921938                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19324521067                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       270033                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       270033                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        42509                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         8157                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           50666                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2968                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2243                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5211                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        14980                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10896                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25876                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          485                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           68                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        60329                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        56024                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       175016                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          209                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           29                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        26625                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        15150                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17711                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       351646                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          485                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           68                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           60329                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           71004                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       175016                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          209                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           29                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           26625                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           26046                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17711                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              377522                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          485                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           68                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          60329                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          71004                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175016                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          209                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           29                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          26625                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          26046                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17711                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             377522                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.223788                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.527155                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.272629                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.324798                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.536335                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.415851                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.736916                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.822320                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.772878                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.332875                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.154148                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.216413                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.184224                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.503526                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.332875                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.277097                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.216413                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.451163                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.521988                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.332875                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.277097                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.216413                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.451163                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.521988                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1162.724693                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1706.046512                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1331.861290                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1984.439834                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1031.587697                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1455.468389                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99063.592717                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82413.169643                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 91603.830192                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        90875                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        84000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80918.583806                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88947.545160                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       102050                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83418.517876                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89280.723755                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 98792.723872                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        90875                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80918.583806                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 94623.329098                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       102050                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83418.517876                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84044.294103                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98063.153053                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        90875                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80918.583806                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 94623.329098                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       102050                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83418.517876                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84044.294103                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98063.153053                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                49                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     24.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              105051                       # number of writebacks
system.l2c.writebacks::total                   105051                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         4156                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         4156                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9513                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4300                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        13813                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          964                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1203                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2167                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11039                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8960                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19999                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          128                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        20082                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8636                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       130145                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           30                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5760                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2791                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         9488                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       177061                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          128                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        20082                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19675                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       130145                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           30                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5760                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        11751                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         9488                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           197060                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          128                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        20082                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19675                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       130145                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           30                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5760                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        11751                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         9488                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          197060                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29629                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5396                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38585                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26357                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4698                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31055                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        55986                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10094                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69640                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    226847000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    101654500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    328501500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     24479500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     30201499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     54680999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    983173000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    648820503                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1631993503                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     10352000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker        74000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1424184505                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    681791000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11917387132                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      2761500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    422975502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    221269506                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1041037947                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  15721833092                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10352000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        74000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1424184505                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1664964000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11917387132                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2761500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    422975502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    870090009                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1041037947                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17353826595                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10352000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        74000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1424184505                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1664964000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11917387132                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2761500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    422975502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    870090009                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1041037947                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17353826595                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    219420500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5330978502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7456000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    854539500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6412394502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    219420500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5330978502                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7456000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    854539500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6412394502                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.223788                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.527155                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.272629                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.324798                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.536335                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.415851                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.736916                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.822320                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.772878                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.154148                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.184224                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.503521                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.277097                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.451163                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.521983                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.277097                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.451163                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.521983                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23846.000210                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23640.581395                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23782.053138                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25393.672199                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25105.152951                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25233.502077                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89063.592717                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72413.002567                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81603.755338                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78947.545160                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79279.651021                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88793.314688                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84623.329098                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74043.911922                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 88063.668908                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 88063.668908                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        535318                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       308111                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          583                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               38585                       # Transaction distribution
system.membus.trans_dist::ReadResp             215902                       # Transaction distribution
system.membus.trans_dist::WriteReq              31055                       # Transaction distribution
system.membus.trans_dist::WriteResp             31055                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       141257                       # Transaction distribution
system.membus.trans_dist::CleanEvict            18818                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            79128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41795                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40708                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19870                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        177317                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14304                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       675920                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       798178                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72957                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72957                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 871135                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19551584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19744330                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22062474                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           126237                       # Total snoops (count)
system.membus.snoopTraffic                      37184                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            444815                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.011558                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.106883                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  439674     98.84%     98.84% # Request fanout histogram
system.membus.snoop_fanout::1                    5141      1.16%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              444815                       # Request fanout histogram
system.membus.reqLayer0.occupancy            94951000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12539499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1031011447                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1149570495                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1412877                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1073312                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       580718                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       172518                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20634                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19568                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1066                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              38588                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            515387                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31055                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31055                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       375084                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          144219                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          115852                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         44839                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         160691                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51833                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51833                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       476801                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4556                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1253209                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       392983                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1646192                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34630659                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7267527                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41898186                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          395888                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  16395788                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           898686                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.386698                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.489423                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 552232     61.45%     61.45% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 345388     38.43%     99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1066      0.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             898686                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          930017339                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           361623                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         658710189                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         272587474                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------