path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.847227                       # Number of seconds simulated
sim_ticks                                2847227406000                       # Number of ticks simulated
final_tick                               2847227406000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 166460                       # Simulator instruction rate (inst/s)
host_op_rate                                   201569                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3722516357                       # Simulator tick rate (ticks/s)
host_mem_usage                                 624360                       # Number of bytes of host memory used
host_seconds                                   764.87                       # Real time elapsed on the host
sim_insts                                   127319545                       # Number of instructions simulated
sim_ops                                     154173476                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         7488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1647744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1317552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8353536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           217280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           643604                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       446720                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12635780                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1647744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       217280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1865024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8874176                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8891740                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          117                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             25746                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21109                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       130524                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3395                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10077                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6980                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197977                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138659                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143050                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2630                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              578719                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              462749                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2933919                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           292                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               76313                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              226046                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       156896                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4437924                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         578719                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          76313                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             655032                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3116778                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6155                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3122947                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3116778                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2630                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             578719                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             468904                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2933919                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          292                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              76313                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             226060                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       156896                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7560871                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197977                       # Number of read requests accepted
system.physmem.writeReqs                       143050                       # Number of write requests accepted
system.physmem.readBursts                      197977                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     143050                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12661056                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8904256                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12635780                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8891740                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11990                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12090                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12710                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12556                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14859                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12263                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12121                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12401                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11839                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11973                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12288                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11633                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12418                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12730                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11938                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12020                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8637                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8726                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9304                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8986                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8078                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8592                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8645                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8770                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8363                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8478                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8927                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8795                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9084                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8813                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8578                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8353                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          38                       # Number of times write queue was full causing retry
system.physmem.totGap                    2847226871000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     553                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  197396                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 138659                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     85811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11580                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9476                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7635                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6090                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4527                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3699                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       718                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      266                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      164                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      145                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92332                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      233.562015                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     132.589518                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     297.350425                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          50532     54.73%     54.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17809     19.29%     74.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6200      6.71%     80.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3503      3.79%     84.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2794      3.03%     87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1407      1.52%     89.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          909      0.98%     90.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          989      1.07%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8189      8.87%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92332                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6903                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.657830                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      561.171003                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6902     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6903                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6903                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.154860                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.644326                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.603874                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5813     84.21%     84.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             373      5.40%     89.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              70      1.01%     90.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              58      0.84%     91.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             265      3.84%     95.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              25      0.36%     95.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              18      0.26%     95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              26      0.38%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              14      0.20%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               9      0.13%     96.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               3      0.04%     96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.12%     96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             153      2.22%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.09%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.09%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.07%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               5      0.07%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.04%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.04%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.04%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.01%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             8      0.12%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.13%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             6      0.09%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6903                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5250518808                       # Total ticks spent queuing
system.physmem.totMemAccLat                8959812558                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    989145000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26540.69                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45290.69                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.45                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.13                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.07                       # Average write queue length when enqueuing
system.physmem.readRowHits                     164412                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80213                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.11                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.64                       # Row buffer hit rate for writes
system.physmem.avgGap                      8348977.86                       # Average gap between requests
system.physmem.pageHitRate                      72.59                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  354957120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  193677000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 787722000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                451902240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185966660880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83190012300                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1635359290500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1906304222040                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.531375                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2720439936839                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95074980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31706739411                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  343072800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  187192500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 755336400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                449653680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185966660880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82901008620                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635612802500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1906215727380                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.500294                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720864046511                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95074980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31288281989                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               20737076                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13605991                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1017313                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            13202297                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8722072                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            66.064807                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3399643                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            216094                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups         760668                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits            581758                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          178910                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        99353                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    68420                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               68420                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46092                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22328                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        68420                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          68420    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        68420                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6777                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5803.014677                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6374     94.05%     94.05% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          345      5.09%     99.14% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           47      0.69%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            6      0.09%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6777                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    338010000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      338010000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    338010000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5225     77.10%     77.10% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1552     22.90%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6777                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        68420                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        68420                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6777                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6777                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        75197                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17339981                       # DTB read hits
system.cpu0.dtb.read_misses                     61941                       # DTB read misses
system.cpu0.dtb.write_hits                   14540400                       # DTB write hits
system.cpu0.dtb.write_misses                     6479                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3449                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1354                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1959                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      521                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17401922                       # DTB read accesses
system.cpu0.dtb.write_accesses               14546879                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31880381                       # DTB hits
system.cpu0.dtb.misses                          68420                       # DTB misses
system.cpu0.dtb.accesses                     31948801                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     3977                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3977                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          304                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3673                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3977                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3977    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3977                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2411                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4752.572139                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          358     14.85%     14.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1847     76.61%     91.46% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          161      6.68%     98.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           17      0.71%     98.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           26      1.08%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2411                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    337545500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      337545500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    337545500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2112     87.60%     87.60% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          299     12.40%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2411                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3977                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3977                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2411                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2411                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6388                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    38606266                       # ITB inst hits
system.cpu0.itb.inst_misses                      3977                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2152                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     6955                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                38610243                       # ITB inst accesses
system.cpu0.itb.hits                         38606266                       # DTB hits
system.cpu0.itb.misses                           3977                       # DTB misses
system.cpu0.itb.accesses                     38610243                       # DTB accesses
system.cpu0.numPwrStateTransitions               3704                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1852                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1492233091.644168                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23940880637.068275                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1073     57.94%     57.94% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          772     41.68%     99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.68% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.05%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499965331660                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1852                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON    83611720275                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       167224982                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   79715648                       # Number of instructions committed
system.cpu0.committedOps                     95927461                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      5237247                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1849                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5527254348                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.097769                       # CPI: cycles per instruction
system.cpu0.ipc                              0.476697                       # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass               2273      0.00%      0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu               63730677     66.44%     66.44% # Class of committed instruction
system.cpu0.op_class_0::IntMult                 92076      0.10%     66.53% # Class of committed instruction
system.cpu0.op_class_0::IntDiv                      0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatMult                   0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt                   0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd                     0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu                     0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp                     0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt                     0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdMult                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdShift                   0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt                    0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     66.53% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc            8115      0.01%     66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult               0      0.00%     66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     66.54% # Class of committed instruction
system.cpu0.op_class_0::MemRead              16811055     17.52%     84.07% # Class of committed instruction
system.cpu0.op_class_0::MemWrite             15283265     15.93%    100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::total                95927461                       # Class of committed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1852                       # number of quiesce instructions executed
system.cpu0.tickCycles                      128530134                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       38694848                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           715130                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.249385                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           30394670                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           715642                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            42.471892                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        356009000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.249385                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.977050                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.977050                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63780153                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63780153                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     15810332                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15810332                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     13424812                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      13424812                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       320440                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       320440                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365226                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365226                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361080                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361080                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     29235144                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        29235144                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     29555584                       # number of overall hits
system.cpu0.dcache.overall_hits::total       29555584                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       463723                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       463723                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       580901                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       580901                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       136483                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       136483                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21307                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21307                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20567                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20567                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1044624                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1044624                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1181107                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1181107                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6183627500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6183627500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10315375000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10315375000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    321766500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    321766500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    497952500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    497952500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       229500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       229500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  16499002500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  16499002500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  16499002500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  16499002500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16274055                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16274055                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     14005713                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     14005713                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456923                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       456923                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386533                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386533                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381647                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381647                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30279768                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30279768                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30736691                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30736691                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028495                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.028495                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041476                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.041476                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.298700                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.298700                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055123                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055123                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053890                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053890                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034499                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.034499                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038427                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.038427                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       715130                       # number of writebacks
system.cpu0.dcache.writebacks::total           715130                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        71798                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        71798                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       255281                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       255281                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14780                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14780                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       327079                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       327079                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       327079                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       327079                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       391925                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       391925                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325620                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       325620                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       103078                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       103078                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6527                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6527                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20567                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20567                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       717545                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       717545                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       820623                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       820623                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20575                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20575                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19271                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19271                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39846                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4674150000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4674150000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5703236000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5703236000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1673631500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1673631500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101407500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101407500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    477391500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    477391500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       223500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       223500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10377386000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10377386000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12051017500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12051017500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4615609000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4615609000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4615609000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4615609000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024083                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024083                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023249                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023249                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225592                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225592                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016886                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016886                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053890                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053890                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023697                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023697                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026698                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026698                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1962004                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.774944                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36636559                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1962516                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            18.668158                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6612168000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774944                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999560                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999560                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          101                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         79160710                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        79160710                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     36636559                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36636559                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36636559                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36636559                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36636559                       # number of overall hits
system.cpu0.icache.overall_hits::total       36636559                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1962531                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1962531                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1962531                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1962531                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1962531                       # number of overall misses
system.cpu0.icache.overall_misses::total      1962531                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18757498000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18757498000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  18757498000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18757498000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  18757498000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18757498000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     38599090                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     38599090                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     38599090                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     38599090                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     38599090                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     38599090                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050844                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050844                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050844                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050844                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050844                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050844                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9557.809787                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9557.809787                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9557.809787                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9557.809787                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9557.809787                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9557.809787                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1962004                       # number of writebacks
system.cpu0.icache.writebacks::total          1962004                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1962531                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1962531                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1962531                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1962531                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1962531                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1962531                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3449                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3449                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3449                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3449                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  17776233000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  17776233000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  17776233000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  17776233000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  17776233000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  17776233000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    319470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    319470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    319470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    319470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050844                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.050844                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050844                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.050844                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9057.810042                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9057.810042                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9057.810042                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9057.810042                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9057.810042                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9057.810042                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1841200                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1841258                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           51                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       233630                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          298119                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16125.660847                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4682482                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          314209                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           14.902444                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    58.059574                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.057522                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1311.534778                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.900635                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003544                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.080050                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.984232                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          965                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15115                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          296                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          400                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          257                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4162                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7775                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2779                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.058899                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.922546                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        89320549                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       89320549                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        82730                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5417                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         88147                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       481961                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       481961                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      2152508                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      2152508                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       222191                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       222191                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1894118                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1894118                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       400891                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       400891                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        82730                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5417                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1894118                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       623082                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2605347                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        82730                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5417                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1894118                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       623082                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2605347                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          856                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          128                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          984                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56746                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        56746                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20566                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20566                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        46690                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        46690                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        68413                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        68413                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       100633                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       100633                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          856                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          128                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        68413                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       147323                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       216720                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          856                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          128                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        68413                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       147323                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       216720                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     28767000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2997000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     31764000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    121525500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    121525500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     25214000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     25214000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       212499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       212499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2304231000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2304231000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3342274500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3342274500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3044310495                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3044310495                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     28767000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2997000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3342274500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5348541495                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8722579995                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     28767000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2997000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3342274500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5348541495                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8722579995                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        83586                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5545                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        89131                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       481961                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       481961                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      2152508                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      2152508                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56747                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56747                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20566                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20566                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268881                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       268881                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1962531                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1962531                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       501524                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       501524                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        83586                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5545                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1962531                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       770405                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2822067                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        83586                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5545                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1962531                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       770405                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2822067                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010241                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.023084                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.011040                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.173646                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.173646                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034860                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034860                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.200654                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.200654                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010241                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.023084                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034860                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.191228                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.076795                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010241                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.023084                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034860                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.191228                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.076795                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33606.308411                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23414.062500                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32280.487805                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2141.569450                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2141.569450                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1226.004084                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1226.004084                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       212499                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       212499                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49351.702720                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49351.702720                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48854.377092                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48854.377092                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30251.612244                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30251.612244                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33606.308411                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23414.062500                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48854.377092                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36304.864108                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40248.154277                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33606.308411                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23414.062500                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48854.377092                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36304.864108                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40248.154277                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           11097                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       233923                       # number of writebacks
system.cpu0.l2cache.writebacks::total          233923                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2672                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2672                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           73                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           73                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          384                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          384                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           73                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3056                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3129                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           73                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3056                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3129                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          856                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          128                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          984                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       258926                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       258926                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56746                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56746                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20566                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20566                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        44018                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        44018                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        68340                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        68340                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100249                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100249                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          856                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          128                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        68340                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       144267                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       213591                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          856                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          128                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        68340                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       144267                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       258926                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       472517                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3449                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20575                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        24024                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19271                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19271                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3449                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        43295                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23631000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2229000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     25860000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14017177372                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14017177372                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1114674000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1114674000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    322353500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    322353500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       176499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       176499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1755037000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1755037000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2929882500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2929882500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2420870995                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2420870995                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23631000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2229000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2929882500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4175907995                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   7131650495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23631000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2229000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2929882500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4175907995                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14017177372                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21148827867                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    291877500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4450889000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4742766500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    291877500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4450889000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4742766500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010241                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.023084                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.011040                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163708                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163708                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034822                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034822                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.199889                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.199889                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010241                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.023084                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034822                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.187261                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075686                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010241                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.023084                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034822                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.187261                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.167436                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       176499                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       176499                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      5508026                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2775137                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        42660                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       346625                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       340732                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         5893                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        122459                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2635557                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19271                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19271                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       716131                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      2195168                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       240019                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       309687                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        88590                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43220                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114518                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           14                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       288089                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284462                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1962531                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       586533                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3131                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5893963                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2592135                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13195                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       174334                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          8673627                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    251390912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     99322292                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22180                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       334344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         351069728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1056913                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3897709                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.106693                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.313582                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3487742     89.48%     89.48% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            404074     10.37%     99.85% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              5893      0.15%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3897709                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    5501303494                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115667783                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2949460514                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1225261932                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7656487                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     90771952                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               19337823                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          6215951                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           910078                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             9913117                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3669706                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            37.018689                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                8699112                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            707232                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        3579063                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           3516137                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           62926                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        23615                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    26974                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               26974                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20087                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6887                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        26974                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          26974    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        26974                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2714                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5760.245338                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          673     24.80%     24.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1844     67.94%     92.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          118      4.35%     97.09% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.06%     99.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           13      0.48%     99.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            4      0.15%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.04%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.07%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            2      0.07%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2714                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -2024068032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -2024068032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -2024068032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1997     73.58%     73.58% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          717     26.42%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2714                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        26974                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        26974                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2714                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2714                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        29688                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    11185393                       # DTB read hits
system.cpu1.dtb.read_misses                     25019                       # DTB read misses
system.cpu1.dtb.write_hits                    6992115                       # DTB write hits
system.cpu1.dtb.write_misses                     1955                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1996                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      164                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   367                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      283                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                11210412                       # DTB read accesses
system.cpu1.dtb.write_accesses                6994070                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         18177508                       # DTB hits
system.cpu1.dtb.misses                          26974                       # DTB misses
system.cpu1.dtb.accesses                     18204482                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     2420                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2420                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2239                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2420                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2420    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2420                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1133                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4742.932714                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          196     17.30%     17.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          640     56.49%     73.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          219     19.33%     93.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           41      3.62%     96.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     96.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      1.32%     98.23% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.71%     98.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            3      0.26%     99.21% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.44%     99.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.18%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1133                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -2024645532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -2024645532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -2024645532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          964     85.08%     85.08% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          169     14.92%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1133                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2420                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2420                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1133                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1133                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3553                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    39602800                       # ITB inst hits
system.cpu1.itb.inst_misses                      2420                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1102                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1819                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                39605220                       # ITB inst accesses
system.cpu1.itb.hits                         39602800                       # DTB hits
system.cpu1.itb.misses                           2420                       # DTB misses
system.cpu1.itb.accesses                     39605220                       # DTB accesses
system.cpu1.numPwrStateTransitions               5553                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2777                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1004505001.039251                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25654466824.490025                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1974     71.08%     71.08% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          799     28.77%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 949981296504                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2777                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    57717018114                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       115435582                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   47603897                       # Number of instructions committed
system.cpu1.committedOps                     58246015                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      5049538                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2772                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5578401245                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.424919                       # CPI: cycles per instruction
system.cpu1.ipc                              0.412385                       # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass                 66      0.00%      0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu               40076529     68.81%     68.81% # Class of committed instruction
system.cpu1.op_class_0::IntMult                 45752      0.08%     68.88% # Class of committed instruction
system.cpu1.op_class_0::IntDiv                      0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatMult                   0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt                   0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd                     0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu                     0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp                     0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt                     0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdMult                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdShift                   0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt                    0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     68.88% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc            3347      0.01%     68.89% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult               0      0.00%     68.89% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     68.89% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     68.89% # Class of committed instruction
system.cpu1.op_class_0::MemRead              11012402     18.91%     87.80% # Class of committed instruction
system.cpu1.op_class_0::MemWrite              7107919     12.20%    100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::total                58246015                       # Class of committed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2777                       # number of quiesce instructions executed
system.cpu1.tickCycles                       97896037                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       17539545                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           196286                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.109798                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           17737294                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           196629                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            90.206907                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      91177108000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.109798                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920136                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.920136                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          343                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          280                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.669922                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         36398755                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        36398755                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     10795076                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       10795076                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6704752                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6704752                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50350                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        50350                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80171                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        80171                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71533                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71533                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     17499828                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        17499828                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     17550178                       # number of overall hits
system.cpu1.dcache.overall_hits::total       17550178                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       159722                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       159722                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       145538                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       145538                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        31004                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        31004                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16960                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16960                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23795                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23795                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       305260                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        305260                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       336264                       # number of overall misses
system.cpu1.dcache.overall_misses::total       336264                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2429598500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2429598500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3913148500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3913148500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    317482500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    317482500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    583924500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    583924500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       387500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       387500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6342747000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6342747000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6342747000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6342747000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     10954798                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     10954798                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6850290                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6850290                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        81354                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        81354                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97131                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97131                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95328                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        95328                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     17805088                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     17805088                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     17886442                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     17886442                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.014580                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.014580                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.021246                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.021246                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.381100                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.381100                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174610                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174610                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249612                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249612                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.017145                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.017145                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.018800                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.018800                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       196286                       # number of writebacks
system.cpu1.dcache.writebacks::total           196286                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16292                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        16292                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52982                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        52982                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12069                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12069                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        69274                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        69274                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        69274                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        69274                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143430                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       143430                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92556                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        92556                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        30096                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        30096                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4891                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4891                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23795                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23795                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       235986                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       235986                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       266082                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       266082                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14424                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14424                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11758                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11758                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26182                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26182                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2041290000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2041290000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2380409500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2380409500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    535271500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    535271500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82814000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     82814000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    560137500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    560137500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       379500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       379500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4421699500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4421699500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4956971000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4956971000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2479783500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2479783500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2479783500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2479783500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013093                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013093                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013511                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013511                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.369939                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.369939                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050355                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050355                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249612                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249612                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013254                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.013254                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014876                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.014876                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           946364                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.210861                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           38654025                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           946876                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.822690                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72815756000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.210861                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975021                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975021                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          462                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           50                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         80148678                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        80148678                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     38654025                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       38654025                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     38654025                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        38654025                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     38654025                       # number of overall hits
system.cpu1.icache.overall_hits::total       38654025                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       946876                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       946876                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       946876                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        946876                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       946876                       # number of overall misses
system.cpu1.icache.overall_misses::total       946876                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8324695000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8324695000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8324695000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8324695000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8324695000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8324695000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     39600901                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     39600901                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     39600901                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     39600901                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     39600901                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     39600901                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023910                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.023910                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023910                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.023910                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023910                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.023910                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8791.747811                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8791.747811                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8791.747811                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8791.747811                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8791.747811                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8791.747811                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       946364                       # number of writebacks
system.cpu1.icache.writebacks::total           946364                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       946876                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       946876                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       946876                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       946876                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       946876                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       946876                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7851257000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7851257000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7851257000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7851257000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7851257000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7851257000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10474500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10474500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10474500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10474500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023910                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023910                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023910                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.023910                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023910                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.023910                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8291.747811                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8291.747811                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8291.747811                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8291.747811                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8291.747811                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8291.747811                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       199879                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       199934                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           48                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        58626                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           53638                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15286.424872                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           2058198                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           68366                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           30.105579                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    39.116539                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.045474                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   428.691662                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.904332                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002387                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000125                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026165                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.933009                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          907                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           45                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13776                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          323                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          581                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5681                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7813                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.055359                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002747                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.840820                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        38543839                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       38543839                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        30076                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         3135                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         33211                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       117792                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       117792                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      1004693                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      1004693                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28032                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        28032                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       926813                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       926813                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       106584                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       106584                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        30076                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         3135                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       926813                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       134616                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1094640                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        30076                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         3135                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       926813                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       134616                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1094640                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          622                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          230                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          852                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        30029                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        30029                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23795                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23795                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34495                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34495                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        20063                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        20063                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        71833                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        71833                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          622                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          230                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        20063                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       106328                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       127243                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          622                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          230                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        20063                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       106328                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       127243                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14337000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4653500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     18990500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     67215000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     67215000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     37021000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     37021000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       366000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       366000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1366050498                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1366050498                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    796902000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    796902000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1679934496                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1679934496                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14337000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4653500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    796902000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3045984994                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3861877494                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14337000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4653500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    796902000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3045984994                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3861877494                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        30698                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3365                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        34063                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       117792                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       117792                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      1004693                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      1004693                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30029                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30029                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23795                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23795                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62527                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62527                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       946876                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       946876                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       178417                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       178417                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        30698                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3365                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       946876                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       240944                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1221883                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        30698                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3365                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       946876                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       240944                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1221883                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020262                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.068351                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.025012                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.551682                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.551682                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.021189                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.021189                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.402613                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.402613                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020262                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.068351                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.021189                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.441298                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.104137                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020262                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.068351                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.021189                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.441298                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.104137                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23049.839228                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20232.608696                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22289.319249                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2238.336275                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2238.336275                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1555.831057                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1555.831057                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39601.405943                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39601.405943                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39719.982057                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39719.982057                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23386.667632                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23386.667632                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23049.839228                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20232.608696                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39719.982057                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28647.063746                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30350.412156                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23049.839228                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20232.608696                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39719.982057                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28647.063746                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30350.412156                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          149                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    37.250000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             841                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        35327                       # number of writebacks
system.cpu1.l2cache.writebacks::total           35327                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          230                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          230                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           22                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           22                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           84                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           84                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           22                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          314                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          336                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           22                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          314                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          336                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          622                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          230                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          852                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        26036                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        26036                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        30029                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        30029                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23795                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23795                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34265                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34265                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        20041                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        20041                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        71749                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        71749                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          622                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          230                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        20041                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       106014                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       126907                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          622                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          230                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        20041                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       106014                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        26036                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       152943                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14424                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14536                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11758                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11758                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26182                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26294                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     10605000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3273500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     13878500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1006636893                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1006636893                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    505691500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    505691500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    380458500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    380458500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       318000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       318000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1135025000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1135025000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    675844000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    675844000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1246810496                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1246810496                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     10605000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3273500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    675844000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2381835496                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3071557996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     10605000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3273500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    675844000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2381835496                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1006636893                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4078194889                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9578500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2364337500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2373916000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9578500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2364337500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2373916000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020262                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.068351                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025012                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.548003                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.548003                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.021165                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.021165                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.402142                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402142                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020262                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.068351                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.021165                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.439994                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103862                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020262                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.068351                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.021165                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.439994                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.125170                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      2394243                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1206431                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        20164                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       192169                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       190372                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1797                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         53056                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1216172                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11758                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11758                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       154274                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      1024857                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       118852                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        31456                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        74303                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42261                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86315                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           14                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        69975                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        67112                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       946876                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       270105                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           65                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2840340                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       913098                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8024                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        64559                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3826021                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    121174528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     30799564                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13460                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       122792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         152110344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     428107                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1655199                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.135380                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.345288                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1432915     86.57%     86.57% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            220487     13.32%     99.89% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1797      0.11%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1655199                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    2373087991                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79906669                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1420645672                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    410383006                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4659998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     33872477                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48463001                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               326500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                84000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               574000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               18000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6138000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            33143500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187679851                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36449                       # number of replacements
system.iocache.tags.tagsinuse               14.476064                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         271175186000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.476064                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904754                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904754                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36467                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36467                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36467                       # number of overall misses
system.iocache.overall_misses::total            36467                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31712877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31712877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4301380974                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4301380974                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4333093851                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4333093851                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4333093851                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4333093851                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36467                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36467                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36467                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36467                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 130505.666667                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118822.328434                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118822.328434                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118822.328434                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118822.328434                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           152                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    9                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    16.888889                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36467                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36467                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36467                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36467                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19562877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19562877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2487893822                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2487893822                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2507456699                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2507456699                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2507456699                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2507456699                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68759.610031                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68759.610031                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   131721                       # number of replacements
system.l2c.tags.tagsinuse                63119.316885                       # Cycle average of tags in use
system.l2c.tags.total_refs                     480965                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   195649                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.458305                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13508.912510                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    74.990696                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.038635                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     9208.691215                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2842.970469                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.769626                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2121.922145                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      593.095570                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1670.405219                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.206130                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001144                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.140513                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043380                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.504906                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000134                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.032378                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009050                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.025488                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.963124                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        27523                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        36326                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          134                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4354                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23032                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           79                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          409                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3689                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        32199                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.419968                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001205                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.554291                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6440622                       # Number of tag accesses
system.l2c.tags.data_accesses                 6440622                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       269250                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          269250                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           33826                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2712                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               36538                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2202                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1074                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3276                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4226                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1659                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5885                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          466                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           69                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        46028                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        50195                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        48669                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          136                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           26                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        16745                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        10025                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5491                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           177850                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           466                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            69                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               46028                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               54421                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        48669                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           136                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            26                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               16745                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               11684                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5491                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  183735                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          466                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           69                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              46028                       # number of overall hits
system.l2c.overall_hits::cpu0.data              54421                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        48669                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          136                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           26                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              16745                       # number of overall hits
system.l2c.overall_hits::cpu1.data              11684                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5491                       # number of overall hits
system.l2c.overall_hits::total                 183735                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9873                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3017                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12890                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          747                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1385                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2132                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11157                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8253                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19410                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          117                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        22311                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9661                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       130681                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           13                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3296                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1822                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6980                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         174882                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          117                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22311                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20818                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       130681                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3296                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10075                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6980                       # number of demand (read+write) misses
system.l2c.demand_misses::total                194292                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          117                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22311                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20818                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       130681                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3296                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10075                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6980                       # number of overall misses
system.l2c.overall_misses::total               194292                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     11941000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3314000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     15255000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1661000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2074000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3735000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1109421000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    686062500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1795483500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10072500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        84000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1812545500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    856898000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13156370360                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      1285500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    273248000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    169259000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    891916725                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  17171679585                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     10072500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        84000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1812545500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1966319000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13156370360                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1285500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    273248000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    855321500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    891916725                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     18967163085                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     10072500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        84000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1812545500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1966319000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13156370360                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1285500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    273248000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    855321500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    891916725                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    18967163085                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       269250                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       269250                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        43699                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5729                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           49428                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2949                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2459                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5408                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15383                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9912                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25295                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          583                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           70                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        68339                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        59856                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179350                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          149                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           26                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        20041                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        11847                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        12471                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       352732                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          583                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           70                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           68339                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           75239                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179350                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          149                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           20041                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21759                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        12471                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              378027                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          583                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           70                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          68339                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          75239                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179350                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          149                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          20041                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21759                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        12471                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             378027                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.225932                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.526619                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.260783                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.253306                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.563237                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.394231                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.725281                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.832627                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.767345                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.200686                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.014286                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.326475                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.161404                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.087248                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.164463                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.153794                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.495793                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.200686                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.014286                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.326475                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.276692                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.087248                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.164463                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.463027                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.513963                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.200686                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.014286                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.326475                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.276692                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.087248                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.164463                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.463027                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.513963                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1209.460144                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1098.442161                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1183.475562                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2223.560910                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1497.472924                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1751.876173                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99437.214305                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83128.862232                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 92503.013910                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86089.743590                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        84000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81239.993725                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88696.615257                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 98884.615385                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82902.912621                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92897.365532                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 98190.091519                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86089.743590                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 81239.993725                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 94452.829282                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98884.615385                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82902.912621                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84895.434243                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 97621.945757                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86089.743590                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 81239.993725                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 94452.829282                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98884.615385                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82902.912621                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84895.434243                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 97621.945757                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              102453                       # number of writebacks
system.l2c.writebacks::total                   102453                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            3                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         4008                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         4008                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9873                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3017                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12890                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          747                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1385                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2132                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11157                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8253                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19410                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          117                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22308                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9661                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       130681                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           13                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3296                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1822                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6980                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       174879                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          117                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22308                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20818                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       130681                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3296                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10075                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6980                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           194289                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          117                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22308                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20818                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       130681                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3296                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10075                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6980                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          194289                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3449                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20575                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14421                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38557                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19271                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11758                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31029                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3449                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26179                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69586                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    236541500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     69602500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    306144000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     19267000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     34208500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     53475500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    997851000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    603531502                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1601382502                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      8902500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker        74000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1589128504                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    760287501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11849557367                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      1155500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    240287501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    151039000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    822114729                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  15422546602                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      8902500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        74000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1589128504                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1758138501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11849557367                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1155500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    240287501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    754570502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    822114729                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17023929104                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      8902500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        74000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1589128504                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1758138501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11849557367                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1155500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    240287501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    754570502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    822114729                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17023929104                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    219448500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4080498000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7226000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2104700001                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6411872501                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    219448500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4080498000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7226000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2104700001                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6411872501                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.225932                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.526619                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.260783                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.253306                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.563237                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.394231                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.725281                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.832627                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.767345                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.200686                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.014286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.326431                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.161404                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.087248                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.164463                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.153794                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.495784                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.200686                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.014286                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.326431                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.276692                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.087248                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.164463                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.463027                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.513955                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.200686                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.014286                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.326431                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.276692                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728637                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.087248                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.164463                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.463027                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.559699                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.513955                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87621.682669                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87621.682669                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        526346                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       301567                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          567                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               38557                       # Transaction distribution
system.membus.trans_dist::ReadResp             213679                       # Transaction distribution
system.membus.trans_dist::WriteReq              31029                       # Transaction distribution
system.membus.trans_dist::WriteResp             31029                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       138659                       # Transaction distribution
system.membus.trans_dist::CleanEvict            18543                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            76988                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41072                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39665                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19299                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        175122                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664223                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       786371                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72931                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72931                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 859302                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28380                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19209376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19401896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21720040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123861                       # Total snoops (count)
system.membus.snoop_fanout::samples            438659                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.011132                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.104918                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  433776     98.89%     98.89% # Request fanout histogram
system.membus.snoop_fanout::1                    4883      1.11%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              438659                       # Request fanout histogram
system.membus.reqLayer0.occupancy            89013499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12314999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1002605728                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1133893717                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1318131                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1068358                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       578478                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       169754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          19773                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        18732                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1041                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              38560                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            513452                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31029                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31029                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       371703                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          144260                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          113415                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         44348                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         157763                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           14                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51662                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51662                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       474894                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4314                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1271960                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       368625                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1640585                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36024040                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5855360                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41879400                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          387762                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           889983                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.383411                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.488617                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 549795     61.78%     61.78% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 339147     38.11%     99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1041      0.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             889983                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          926156147                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           342619                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         669727799                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         257138606                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------