path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.846057                       # Number of seconds simulated
sim_ticks                                2846057099000                       # Number of ticks simulated
final_tick                               2846057099000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 155095                       # Simulator instruction rate (inst/s)
host_op_rate                                   187821                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3461671389                       # Simulator tick rate (ticks/s)
host_mem_usage                                 654788                       # Number of bytes of host memory used
host_seconds                                   822.16                       # Real time elapsed on the host
sim_insts                                   127513349                       # Number of instructions simulated
sim_ops                                     154419501                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         7744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1469184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1233972                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8227712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         2752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           383104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           711064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       574528                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12611084                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1469184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       383104                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1852288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8917568                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8935132                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          121                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             22956                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             19804                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       128558                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           43                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5986                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             11132                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         8977                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197593                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          139337                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143728                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2721                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              516217                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              433572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2890916                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           967                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              134609                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              249842                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       201868                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4431072                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         516217                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         134609                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             650826                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3133306                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3139477                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3133306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2721                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             516217                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             439730                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2890916                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          967                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             134609                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             249856                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       201868                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7570549                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197593                       # Number of read requests accepted
system.physmem.writeReqs                       143728                       # Number of write requests accepted
system.physmem.readBursts                      197593                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     143728                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12635520                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8947648                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12611084                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8935132                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          51189                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12157                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12292                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12950                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12405                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15321                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12434                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12677                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13084                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12267                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12426                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11655                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11073                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11997                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11769                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11320                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11603                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8631                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8804                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9518                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8865                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8658                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8780                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9135                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9275                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8996                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8951                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8409                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8136                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8895                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8304                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8310                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8140                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
system.physmem.totGap                    2846056522500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  197010                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 139337                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     84527                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62953                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11439                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9638                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7653                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4583                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3751                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       746                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      272                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8859                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10384                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7940                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      106                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        90385                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      238.790065                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     135.540737                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     300.321787                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          48391     53.54%     53.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17645     19.52%     73.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6369      7.05%     80.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3664      4.05%     84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2743      3.03%     87.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1397      1.55%     88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          884      0.98%     89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1036      1.15%     90.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8256      9.13%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          90385                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6985                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.264567                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      537.756673                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6984     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6985                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6985                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.015319                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.579154                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.029266                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5867     83.99%     83.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             359      5.14%     89.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             198      2.83%     91.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              50      0.72%     92.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              72      1.03%     93.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             159      2.28%     95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.27%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              12      0.17%     96.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.16%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.11%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.07%     96.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             162      2.32%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.09%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.09%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              10      0.14%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.01%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.20%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             4      0.06%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6985                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5478181174                       # Total ticks spent queuing
system.physmem.totMemAccLat                9179993674                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    987150000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27747.46                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46497.46                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.14                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.43                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.99                       # Average write queue length when enqueuing
system.physmem.readRowHits                     164056                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     82794                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.10                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.21                       # Row buffer hit rate for writes
system.physmem.avgGap                      8338357.51                       # Average gap between requests
system.physmem.pageHitRate                      73.19                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  356771520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  194667000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 805888200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                464395680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83219414895                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634632736250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905564250425                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.546132                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719229075521                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95035980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31791929979                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  326539080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  178171125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 734050200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                441553680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82136174355                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635582947250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905289812570                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.449705                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720812978493                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95035980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30205644507                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               19599196                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         12768904                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           991514                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            12558764                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8839837                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            70.387795                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3295346                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            199810                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    67395                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               67395                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44710                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22685                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        67395                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          67395    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        67395                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6692                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9352.624092                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5969.180600                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6501     97.15%     97.15% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          173      2.59%     99.73% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           11      0.16%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6692                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    327753000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      327753000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    327753000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5137     76.76%     76.76% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1555     23.24%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6692                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67395                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67395                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6692                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6692                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        74087                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    16492967                       # DTB read hits
system.cpu0.dtb.read_misses                     61485                       # DTB read misses
system.cpu0.dtb.write_hits                   13879033                       # DTB write hits
system.cpu0.dtb.write_misses                     5910                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3512                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1104                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1584                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                16554452                       # DTB read accesses
system.cpu0.dtb.write_accesses               13884943                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         30372000                       # DTB hits
system.cpu0.dtb.misses                          67395                       # DTB misses
system.cpu0.dtb.accesses                     30439395                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3867                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3867                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3560                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3867                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3867    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3867                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2421                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9615.276250                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7885.681727                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767         2419     99.92%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2421                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    327059500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      327059500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    327059500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2121     87.61%     87.61% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          300     12.39%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2421                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3867                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3867                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2421                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2421                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6288                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    36759532                       # ITB inst hits
system.cpu0.itb.inst_misses                      3867                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2224                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7295                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                36763399                       # ITB inst accesses
system.cpu0.itb.hits                         36759532                       # DTB hits
system.cpu0.itb.misses                           3867                       # DTB misses
system.cpu0.itb.accesses                     36763399                       # DTB accesses
system.cpu0.numCycles                       154883476                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   75627253                       # Number of instructions committed
system.cpu0.committedOps                     91033342                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      4957970                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     2062                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5537267530                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.047985                       # CPI: cycles per instruction
system.cpu0.ipc                              0.488285                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2064                       # number of quiesce instructions executed
system.cpu0.tickCycles                      121009607                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       33873869                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           680149                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          489.017964                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           28930962                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           680661                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            42.504216                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        345600000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   489.017964                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.955113                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.955113                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         60723709                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        60723709                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15008806                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15008806                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     12795540                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      12795540                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306691                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       306691                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356713                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       356713                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352309                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       352309                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     27804346                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        27804346                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     28111037                       # number of overall hits
system.cpu0.dcache.overall_hits::total       28111037                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       442745                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       442745                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       557072                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       557072                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131875                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       131875                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21262                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21262                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21236                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21236                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       999817                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        999817                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1131692                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1131692                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5845429500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5845429500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8925410000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8925410000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    323710500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    323710500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    479970000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    479970000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       445000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       445000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  14770839500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14770839500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  14770839500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14770839500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     15451551                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     15451551                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13352612                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13352612                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438566                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       438566                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377975                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       377975                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373545                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       373545                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     28804163                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     28804163                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     29242729                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     29242729                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028654                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.028654                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041720                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.041720                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300696                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300696                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056252                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056252                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056850                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056850                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034711                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.034711                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038700                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.038700                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       493052                       # number of writebacks
system.cpu0.dcache.writebacks::total           493052                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69962                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        69962                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244118                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       244118                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15072                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15072                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       314080                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       314080                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       314080                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       314080                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372783                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       372783                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312954                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       312954                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99314                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        99314                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6190                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6190                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21236                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21236                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       685737                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       685737                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       785051                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       785051                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18001                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34757                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4391149500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4391149500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4970740000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4970740000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1612906500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1612906500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94756000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94756000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    458745000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    458745000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       434000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       434000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9361889500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9361889500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10974796000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10974796000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3751362500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3751362500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2725552500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725552500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6476915000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6476915000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024126                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024126                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023438                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023438                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226452                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226452                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016377                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016377                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056850                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056850                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023807                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023807                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026846                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026846                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1879741                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.785261                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           34871642                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1880253                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            18.546250                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6165545000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785261                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999581                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999581                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         75384087                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        75384087                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     34871642                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       34871642                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     34871642                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        34871642                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     34871642                       # number of overall hits
system.cpu0.icache.overall_hits::total       34871642                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1880268                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1880268                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1880268                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1880268                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1880268                       # number of overall misses
system.cpu0.icache.overall_misses::total      1880268                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17494991000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  17494991000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  17494991000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  17494991000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  17494991000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  17494991000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     36751910                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     36751910                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     36751910                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     36751910                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     36751910                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     36751910                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051161                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051161                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051161                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051161                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051161                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051161                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9304.519888                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9304.519888                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9304.519888                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9304.519888                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1880268                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1880268                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1880268                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1880268                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1880268                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1880268                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3426                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16554857500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16554857500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16554857500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16554857500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16554857500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16554857500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    314279000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    314279000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051161                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.051161                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.051161                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8804.520154                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1762988                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1763146                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          137                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       223158                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          285163                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16064.441291                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4801094                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          301400                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           15.929310                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  8613.892017                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    45.679204                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.072727                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4663.239886                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1620.721287                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1120.836170                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.525750                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002788                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.284622                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.098921                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068410                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.980496                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1029                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15199                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          305                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          401                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          310                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4239                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7941                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2698                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062805                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927673                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        85389688                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       85389688                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        78899                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4233                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         83132                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       493050                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       493050                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28200                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28200                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1701                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1701                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212815                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       212815                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1816263                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1816263                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       377267                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       377267                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        78899                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4233                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1816263                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       590082                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2489477                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        78899                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4233                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1816263                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       590082                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2489477                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          767                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          105                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          872                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27843                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        27843                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19534                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19534                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44100                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44100                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        64005                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        64005                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101018                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101018                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          767                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          105                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        64005                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       145118                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       209995                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          767                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          105                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        64005                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       145118                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       209995                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     26175500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2558000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     28733500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    514961000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    514961000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    395123500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    395123500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       417500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       417500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2206381000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2206381000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2858183000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2858183000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2907472497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2907472497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     26175500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2558000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2858183000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5113853497                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8000769997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     26175500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2558000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2858183000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5113853497                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8000769997                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        79666                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4338                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        84004                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       493050                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       493050                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56043                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56043                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21235                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21235                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       256915                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       256915                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1880268                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1880268                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       478285                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       478285                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        79666                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4338                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1880268                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       735200                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2699472                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        79666                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4338                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1880268                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       735200                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2699472                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.010380                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.496815                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.496815                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.919896                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.919896                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171652                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171652                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034040                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034040                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211209                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211209                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034040                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197386                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.077791                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034040                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197386                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.077791                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       417500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       417500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           60                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       195910                       # number of writebacks
system.cpu0.l2cache.writebacks::total          195910                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2609                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2609                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           70                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           70                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          363                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          363                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           70                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         2972                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3042                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           70                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         2972                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3042                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          767                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          105                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          872                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9288                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total         9288                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       233934                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27843                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27843                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19534                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19534                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41491                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41491                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        63935                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        63935                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100655                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100655                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          767                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          105                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63935                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142146                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       206953                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          767                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          105                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63935                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142146                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       440887                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        21427                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        38183                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     23501500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13851204796                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    554776500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    554776500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298118500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298118500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       351500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       351500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1669946000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1669946000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2472260000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2472260000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2283319997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2283319997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2472260000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3953265997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6449027497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2472260000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3953265997                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  20300232293                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3607256500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3894127000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2599622000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2599622000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6206878500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6493749000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010380                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.496815                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.496815                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.919896                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.919896                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.161497                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.161497                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034003                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210450                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.210450                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076664                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163323                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       351500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       351500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq        136175                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2526619                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        16756                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       865136                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2178805                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       280675                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        92865                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43660                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114593                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       285252                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       271172                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1880268                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       604912                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5613549                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2467613                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11765                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       169746                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          8262673                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120556352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82765674                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       318664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         203658042                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1202366                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      6476462                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.183069                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.386723                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           5290820     81.69%     81.69% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           1185642     18.31%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       6476462                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3195593995                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113765999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2825774529                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1168364927                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7430992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     90084491                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               20439224                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7037667                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           906738                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            10483361                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                7695105                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            73.403034                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                8822837                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            629691                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    30282                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               30282                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22625                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7657                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        30282                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          30282    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        30282                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2657                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9441.717442                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7245.373074                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         2512     94.54%     94.54% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          130      4.89%     99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            7      0.26%     99.70% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-98303            5      0.19%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-114687            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2657                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1594102264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1594102264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1594102264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1972     74.22%     74.22% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          685     25.78%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2657                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30282                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30282                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2657                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2657                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        32939                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12124185                       # DTB read hits
system.cpu1.dtb.read_misses                     27903                       # DTB read misses
system.cpu1.dtb.write_hits                    7716793                       # DTB write hits
system.cpu1.dtb.write_misses                     2379                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2053                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      374                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   549                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      291                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12152088                       # DTB read accesses
system.cpu1.dtb.write_accesses                7719172                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         19840978                       # DTB hits
system.cpu1.dtb.misses                          30282                       # DTB misses
system.cpu1.dtb.accesses                     19871260                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2290                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2290                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2108                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2290                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2290                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1123                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9754.511529                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5025.096618                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          329     29.30%     29.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          526     46.84%     76.14% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          229     20.39%     96.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     96.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           14      1.25%     97.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           21      1.87%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1123                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1593536764                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1593536764    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1593536764                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          954     84.95%     84.95% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          169     15.05%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1123                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1123                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1123                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3413                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    41919801                       # ITB inst hits
system.cpu1.itb.inst_misses                      2290                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1161                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1868                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                41922091                       # ITB inst accesses
system.cpu1.itb.hits                         41919801                       # DTB hits
system.cpu1.itb.misses                           2290                       # DTB misses
system.cpu1.itb.accesses                     41922091                       # DTB accesses
system.cpu1.numCycles                       125017818                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   51886096                       # Number of instructions committed
system.cpu1.committedOps                     63386159                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      5353179                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2738                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5566469050                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.409467                       # CPI: cycles per instruction
system.cpu1.ipc                              0.415030                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
system.cpu1.tickCycles                      105304281                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       19713537                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           231375                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          483.037999                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           19321104                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           231701                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            83.388091                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90467560500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   483.037999                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.943434                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.943434                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          326                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          253                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           73                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.636719                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         39693132                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        39693132                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     11664966                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       11664966                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      7379255                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       7379255                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66113                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        66113                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88582                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        88582                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80498                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        80498                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     19044221                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        19044221                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     19110334                       # number of overall hits
system.cpu1.dcache.overall_hits::total       19110334                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       184342                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       184342                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       167268                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       167268                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34982                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        34982                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17676                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17676                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23450                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23450                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       351610                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        351610                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       386592                       # number of overall misses
system.cpu1.dcache.overall_misses::total       386592                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2719374500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2719374500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4153510500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4153510500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325753000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    325753000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548137000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    548137000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       684500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       684500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6872885000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6872885000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6872885000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6872885000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     11849308                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     11849308                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      7546523                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      7546523                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101095                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       101095                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106258                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       106258                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103948                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       103948                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     19395831                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     19395831                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     19496926                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     19496926                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015557                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.015557                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022165                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.022165                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.346031                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.346031                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166350                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166350                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225594                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225594                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018128                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.018128                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019828                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.019828                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       138377                       # number of writebacks
system.cpu1.dcache.writebacks::total           138377                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18221                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        18221                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62038                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        62038                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12225                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12225                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        80259                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        80259                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        80259                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        80259                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166121                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       166121                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105230                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       105230                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33463                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        33463                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5451                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5451                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23450                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23450                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       271351                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       271351                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       304814                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       304814                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17128                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31533                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2295109000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2295109000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2517034000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2517034000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    544638000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    544638000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     92810500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     92810500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524700000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524700000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       671500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       671500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4812143000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4812143000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5356781000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5356781000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2934873000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2934873000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2446602500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2446602500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5381475500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5381475500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014019                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014019                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013944                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013944                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331005                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331005                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051300                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051300                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225594                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225594                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013990                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.013990                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015634                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.015634                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          1042125                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.329120                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           40875126                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          1042637                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            39.203602                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72106351500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.329120                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975252                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975252                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         84878163                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        84878163                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     40875126                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       40875126                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     40875126                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        40875126                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     40875126                       # number of overall hits
system.cpu1.icache.overall_hits::total       40875126                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      1042637                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      1042637                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      1042637                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       1042637                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      1042637                       # number of overall misses
system.cpu1.icache.overall_misses::total      1042637                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9237616500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9237616500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9237616500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9237616500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9237616500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9237616500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     41917763                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     41917763                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     41917763                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     41917763                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     41917763                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     41917763                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024873                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024873                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024873                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024873                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024873                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024873                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8859.858704                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8859.858704                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8859.858704                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8859.858704                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1042637                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      1042637                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      1042637                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      1042637                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      1042637                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      1042637                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          113                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          113                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8716298000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   8716298000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8716298000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   8716298000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8716298000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   8716298000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10126000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10126000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024873                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024873                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024873                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8359.858704                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       270674                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       270706                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        70190                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           69559                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15624.003278                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           2421583                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           84278                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           28.733276                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6091.947681                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    59.671167                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.103493                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5612.930096                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2321.677903                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1537.672938                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.371823                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003642                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.342586                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.141704                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.093852                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.953613                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1225                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13444                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          697                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          522                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          327                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5775                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7342                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074768                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.820557                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        42869923                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       42869923                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33040                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2583                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         35623                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       138377                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       138377                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2042                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         2042                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1012                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total         1012                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37732                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        37732                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1015029                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      1015029                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131048                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       131048                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33040                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2583                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1015029                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       168780                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1219432                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33040                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2583                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1015029                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       168780                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1219432                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          727                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          221                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          948                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29373                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29373                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22436                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22436                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36088                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        36088                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27608                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        27608                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73984                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        73984                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          727                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          221                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        27608                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       110072                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       138628                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          727                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          221                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        27608                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       110072                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       138628                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     18603000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4457500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     23060500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    554124000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    554124000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449909000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449909000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       652000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       652000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1418232500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1418232500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1071283000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1071283000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1763586495                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1763586495                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     18603000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4457500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1071283000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3181818995                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4276162495                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     18603000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4457500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1071283000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3181818995                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4276162495                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33767                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2804                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        36571                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       138377                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       138377                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31415                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        31415                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23448                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23448                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73820                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        73820                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1042637                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      1042637                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205032                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       205032                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33767                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2804                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1042637                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       278852                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1358060                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33767                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2804                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1042637                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       278852                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1358060                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.025922                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.934999                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.934999                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.956841                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.956841                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.488865                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.488865                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026479                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026479                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360841                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360841                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026479                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.394733                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.102078                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026479                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.394733                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.102078                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       326000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       326000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        36799                       # number of writebacks
system.cpu1.l2cache.writebacks::total           36799                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          302                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          302                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           26                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          134                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          134                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           26                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          436                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          462                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           26                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          436                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          462                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          727                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          221                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          948                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3205                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total         3205                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        35196                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29373                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29373                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22436                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22436                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35786                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        35786                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27582                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27582                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73850                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73850                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          727                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          221                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27582                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109636                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       138166                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          727                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          221                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27582                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109636                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       173362                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17241                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31646                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     17372500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1238467331                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    502709499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    502709499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348029000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348029000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       574000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       574000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1167759000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1167759000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    904893000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    904893000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1316095995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1316095995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    904893000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2483854995                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3406120495                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    904893000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2483854995                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4644587826                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2797805500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2807027500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2338455000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2338455000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5136260500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5145482500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025922                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.934999                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.934999                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.956841                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.956841                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.484774                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.484774                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026454                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.360188                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.360188                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101738                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.127654                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       287000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       287000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq         81005                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1348099                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        14405                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       510462                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1265020                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        43516                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        77320                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42972                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89288                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        97251                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        79776                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1042637                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       559861                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3108261                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1040223                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7202                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        71706                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          4227392                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66736000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29812791                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       135068                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          96695075                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    1172897                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      3809713                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.296141                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.456554                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2681500     70.39%     70.39% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           1128213     29.61%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       3809713                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1507501992                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     87443999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1564193862                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    470956198                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4398499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     37948980                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31013                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31013                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180870                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162793                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484073                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187545199                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84712000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36462                       # number of replacements
system.iocache.tags.tagsinuse               14.479963                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270370198000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.479963                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904998                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904998                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
system.iocache.tags.data_accesses              328320                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          256                       # number of demand (read+write) misses
system.iocache.demand_misses::total               256                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          256                       # number of overall misses
system.iocache.overall_misses::total              256                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32688877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32688877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4277206322                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4277206322                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32688877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32688877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32688877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32688877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          256                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             256                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          256                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            256                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 127690.925781                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 127690.925781                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 127690.925781                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            21                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          256                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          256                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          256                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19888877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19888877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2466006322                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2466006322                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     19888877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     19888877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     19888877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     19888877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   134724                       # number of replacements
system.l2c.tags.tagsinuse                64068.233504                       # Cycle average of tags in use
system.l2c.tags.total_refs                     443602                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   199053                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.228562                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12835.902941                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.531822                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.025215                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7257.127456                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2101.817094                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    30.126345                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4045.876721                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1535.093827                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4184.707478                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.195860                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001046                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.110735                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.032071                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.488419                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000460                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.061735                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.023424                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.063854                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.977604                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29296                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34966                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          113                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5383                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23800                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          313                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2923                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        31711                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.447021                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001022                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.533539                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5827626                       # Number of tag accesses
system.l2c.tags.data_accesses                 5827626                       # Number of data accesses
system.l2c.Writeback_hits::writebacks          232709                       # number of Writeback hits
system.l2c.Writeback_hits::total               232709                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3025                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             939                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3964                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           257                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            83                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               340                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4055                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2183                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 6238                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          387                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           52                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        44381                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        47292                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46189                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          171                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           33                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        21681                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11241                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8230                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           179657                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           387                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            52                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               44381                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51347                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46189                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           171                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            33                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               21681                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               13424                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         8230                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  185895                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          387                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           52                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              44381                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51347                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46189                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          171                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           33                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              21681                       # number of overall hits
system.l2c.overall_hits::cpu1.data              13424                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         8230                       # number of overall hits
system.l2c.overall_hits::total                 185895                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          8753                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4074                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12827                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          797                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1213                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2010                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          10969                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8454                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19423                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19546                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8542                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         5890                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2696                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         174531                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          121                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19546                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19511                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           43                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5890                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             11150                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) misses
system.l2c.demand_misses::total                193954                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          121                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19546                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19511                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       128715                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           43                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5890                       # number of overall misses
system.l2c.overall_misses::cpu1.data            11150                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         8977                       # number of overall misses
system.l2c.overall_misses::total               193954                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      9167000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5104000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14271000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1330000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1451500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2781500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1087997000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    696148000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1784145000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10392000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       303000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1558395000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    749223000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3962000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    483846500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    240245000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  17184117504                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     10392000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       303000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1558395000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1837220000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      3962000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    483846500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    936393000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     18968262504                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     10392000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       303000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1558395000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1837220000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      3962000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    483846500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    936393000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    18968262504                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks       232709                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           232709                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11778                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5013                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           16791                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1054                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1296                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2350                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15024                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10637                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25661                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          508                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           53                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        63927                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55834                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       174904                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          214                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           33                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        27571                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        13937                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17207                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       354188                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          508                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           53                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           63927                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           70858                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       174904                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          214                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           33                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           27571                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           24574                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17207                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              379849                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          508                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           53                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          63927                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          70858                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       174904                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          214                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           33                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          27571                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          24574                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17207                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             379849                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.743165                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.812687                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.763921                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.756167                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.935957                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.855319                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.730099                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.794773                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.756907                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.305755                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.152989                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.213630                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.193442                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.492764                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.305755                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.275354                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.213630                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.453732                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.510608                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.305755                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.275354                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.213630                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.453732                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.510608                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1047.298069                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1252.822779                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1112.575037                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1668.757842                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1196.619951                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1383.830846                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 91857.334088                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       303000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 97797.738144                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 97797.738144                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               442                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           221                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              103131                       # number of writebacks
system.l2c.writebacks::total                   103131                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3812                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3812                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8753                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4074                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12827                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          797                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1213                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2010                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        10969                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8454                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19423                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19541                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8542                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5886                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2696                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       174522                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          121                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19541                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19511                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           43                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5886                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        11150                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           193945                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          121                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19541                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19511                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           43                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5886                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        11150                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          193945                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17124                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38664                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31161                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31529                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69825                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    181795500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     84589501                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    266385001                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16646000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25174500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     41820500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    978307000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    611608000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1589915000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       293000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1362728000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    663803000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    424750500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    213285000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  15438404504                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       293000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1362728000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1642110000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    424750500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    824893000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17028319504                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       293000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1362728000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1642110000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    424750500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    824893000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17028319504                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3283233500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2489515500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5994522000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2314676500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2093562500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4408239000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5597910000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4583078000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10402761000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.743165                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.812687                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.763921                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.756167                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935957                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.855319                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.730099                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.794773                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.756907                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.152989                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.193442                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.492738                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.510584                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.510584                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               38664                       # Transaction distribution
system.membus.trans_dist::ReadResp             213442                       # Transaction distribution
system.membus.trans_dist::WriteReq              31161                       # Transaction distribution
system.membus.trans_dist::WriteResp             31161                       # Transaction distribution
system.membus.trans_dist::Writeback            139337                       # Transaction distribution
system.membus.trans_dist::CleanEvict            18210                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            78893                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41609                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14967                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39746                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19293                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        174778                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14714                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       681524                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       804190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108938                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108938                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 913128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162793                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29428                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19228072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19421637                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21739781                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           126569                       # Total snoops (count)
system.membus.snoop_fanout::samples            598906                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  598906    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              598906                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91147500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12904500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1003618732                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1163956699                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64493538                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq              38668                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            519865                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31161                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31161                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           372085                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           99404                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           82727                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41949                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         124676                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           24                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51768                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51768                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       481212                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1091980                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       404567                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1496547                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32727326                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6930535                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39657861                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          466410                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1287380                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.161360                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.367862                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1079649     83.86%     83.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 207731     16.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1287380                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          861414818                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           361500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         631551677                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         286263459                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------