path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.852200                       # Number of seconds simulated
sim_ticks                                2852200332000                       # Number of ticks simulated
final_tick                               2852200332000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 169178                       # Simulator instruction rate (inst/s)
host_op_rate                                   204545                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4322499487                       # Simulator tick rate (ticks/s)
host_mem_usage                                 558640                       # Number of bytes of host memory used
host_seconds                                   659.85                       # Real time elapsed on the host
sim_insts                                   111631963                       # Number of instructions simulated
sim_ops                                     134968701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         6592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10875428                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10883108                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1665536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1665536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5669632                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8005492                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker          103                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             170448                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170568                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           88588                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               129193                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           2311                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst              3812996                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3815688                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          583948                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             583948                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1987810                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          812824                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.inst                6144                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2806778                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1987810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          813160                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2311                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             3819140                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6622466                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170568                       # Number of read requests accepted
system.physmem.writeReqs                       129193                       # Number of write requests accepted
system.physmem.readBursts                      170568                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     129193                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10907008                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8019264                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10883108                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8005492                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4599                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10529                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10427                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10726                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10519                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13519                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10191                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11164                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10885                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10359                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10882                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10112                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9441                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10326                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11222                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10031                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10089                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7745                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7827                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8372                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8091                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7875                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7401                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8203                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8042                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7896                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8173                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7527                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7251                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7760                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8405                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7350                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7383                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
system.physmem.totGap                    2852199845000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  170013                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124812                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163493                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6879                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6615                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7435                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60576                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      312.437401                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     184.644234                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.251922                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22086     36.46%     36.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14485     23.91%     60.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6694     11.05%     71.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3534      5.83%     77.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2501      4.13%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1624      2.68%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1087      1.79%     85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1062      1.75%     87.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7503     12.39%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60576                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6291                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.088221                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      577.877413                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6289     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6291                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6291                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.917501                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.380102                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.942111                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5514     87.65%     87.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              46      0.73%     88.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              31      0.49%     88.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             207      3.29%     92.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             183      2.91%     95.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              14      0.22%     95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              17      0.27%     95.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              17      0.27%     95.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              30      0.48%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               7      0.11%     96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               3      0.05%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             154      2.45%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               3      0.05%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.06%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              21      0.33%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               6      0.10%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.05%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             6      0.10%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6291                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1680738000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4876150500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    852110000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9862.21                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28612.21                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.82                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.81                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140727                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94419                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.58                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.34                       # Row buffer hit rate for writes
system.physmem.avgGap                      9514913.03                       # Average gap between requests
system.physmem.pageHitRate                      79.51                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2713226080000                       # Time in different power states
system.physmem.memoryStateTime::REF       95241120000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       43733042000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 234125640                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 223828920                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 127747125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 122128875                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                686088000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                643195800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               411842880                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               400107600                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          186291630720                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          186291630720                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           82872817560                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           82165704345                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1638622788000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1639243062750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1909247039925                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1909089659010                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.395204                       # Core power per rank (mW)
system.physmem.averagePower::1             669.340025                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             180                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq               71824                       # Transaction distribution
system.membus.trans_dist::ReadResp              71824                       # Transaction distribution
system.membus.trans_dist::WriteReq              27607                       # Transaction distribution
system.membus.trans_dist::WriteResp             27607                       # Transaction distribution
system.membus.trans_dist::Writeback             88588                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4597                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4599                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129554                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129554                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447654                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       555288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 627985                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16569304                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16733149                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19052445                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              219                       # Total snoops (count)
system.membus.snoop_fanout::samples            296652                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  296652    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              296652                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87220000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               11500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1713500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1383760500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1715299901                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38332500                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178466                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480301                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326584349                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36805500                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                30761849                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16759561                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2494541                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18376022                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13249221                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.100594                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7712174                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1491943                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24631139                       # DTB read hits
system.cpu.dtb.read_misses                      58263                       # DTB read misses
system.cpu.dtb.write_hits                    19400231                       # DTB write hits
system.cpu.dtb.write_misses                      6058                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4344                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1249                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1789                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       740                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24689402                       # DTB read accesses
system.cpu.dtb.write_accesses                19406289                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44031370                       # DTB hits
system.cpu.dtb.misses                           64321                       # DTB misses
system.cpu.dtb.accesses                      44095691                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                     57062578                       # ITB inst hits
system.cpu.itb.inst_misses                       5424                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2982                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8630                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57068002                       # ITB inst accesses
system.cpu.itb.hits                          57062578                       # DTB hits
system.cpu.itb.misses                            5424                       # DTB misses
system.cpu.itb.accesses                      57068002                       # DTB accesses
system.cpu.numCycles                        313219225                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   111631963                       # Number of instructions committed
system.cpu.committedOps                     134968701                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7932752                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5391228164                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.805820                       # CPI: cycles per instruction
system.cpu.ipc                               0.356402                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
system.cpu.tickCycles                       224159041                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        89060184                       # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements           2896816                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.427908                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54156207                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2897328                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.691776                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15213008250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.427908                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998883                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998883                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          59950884                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         59950884                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54156207                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54156207                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54156207                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54156207                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54156207                       # number of overall hits
system.cpu.icache.overall_hits::total        54156207                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2897339                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2897339                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2897339                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2897339                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2897339                       # number of overall misses
system.cpu.icache.overall_misses::total       2897339                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39126605503                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39126605503                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39126605503                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39126605503                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39126605503                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39126605503                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57053546                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57053546                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57053546                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57053546                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57053546                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57053546                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050783                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050783                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050783                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050783                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050783                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050783                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13504.324314                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13504.324314                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897339                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2897339                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2897339                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2897339                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2897339                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2897339                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33322439497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  33322439497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33322439497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  33322439497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33322439497                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  33322439497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    222173750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    222173750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    222173750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    222173750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050783                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050783                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050783                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050783                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050783                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050783                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11501.049583                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11501.049583                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11501.049583                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11501.049583                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11501.049583                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11501.049583                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3575425                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3575329                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       697864                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2819                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2821                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295691                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295691                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5800652                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2504517                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15250                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       156288                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8476707                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185619904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98723549                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18892                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       276412                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284638757                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       60515                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4573888                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.007972                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.088927                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            4537427     99.20%     99.20% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6              36461      0.80%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4573888                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3011299661                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       208500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4355950753                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1340010456                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10527250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      87188750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements            97184                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65075.712435                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4041226                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162444                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.877656                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      93442219500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47462.018914                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    55.401726                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009455                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 17558.282340                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.724213                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000845                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.267918                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992977                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65213                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           47                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2308                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6976                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55798                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000717                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995071                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         36570721                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        36570721                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69000                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4721                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      3405800                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        3479521                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       697864                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       697864                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.inst           45                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst       164314                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164314                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        69000                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4721                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      3570114                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3643835                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        69000                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4721                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      3570114                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3643835                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          103                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        37510                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        37615                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2774                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2774                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       131377                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131377                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          103                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       168887                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168992                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          103                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       168887                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168992                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      7796000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       163250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2760094000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2768053250                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       998957                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       998957                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst        46498                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        46498                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9221968427                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9221968427                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      7796000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       163250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11982062427                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11990021677                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      7796000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       163250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11982062427                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11990021677                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        69103                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4723                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      3443310                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      3517136                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       697864                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       697864                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2819                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2819                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       295691                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295691                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69103                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4723                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      3739001                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3812827                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69103                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4723                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      3739001                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3812827                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001491                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000423                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010894                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.010695                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.984037                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984037                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.444305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.444305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001491                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000423                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.045169                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044322                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001491                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000423                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.045169                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044322                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 75689.320388                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        81625                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73582.884564                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73589.080154                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   360.114275                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   360.114275                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        23249                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        23249                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70194.694863                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70194.694863                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 75689.320388                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        81625                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70947.215754                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70950.232419                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 75689.320388                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        81625                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70947.215754                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70950.232419                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88588                       # number of writebacks
system.cpu.l2cache.writebacks::total            88588                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          165                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          165                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst          165                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst          165                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          103                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37345                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        37450                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2774                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2774                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131377                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131377                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          103                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       168722                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168827                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          103                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       168722                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168827                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      6531000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       138750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2281377500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2288047250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27781774                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27781774                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst        20002                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7543603073                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7543603073                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      6531000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       138750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9824980573                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9831650323                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      6531000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       138750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9824980573                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9831650323                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545609250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545609250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4106796000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4106796000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652405250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652405250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001491                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000423                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010846                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010648                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.984037                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984037                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.444305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001491                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000423                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.045125                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044279                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001491                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000423                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.045125                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044279                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        69375                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61089.235507                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61096.054740                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.059120                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.059120                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57419.510820                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57419.510820                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        69375                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58231.769259                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58235.059102                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        69375                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58231.769259                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58235.059102                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            841153                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.953397                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42536757                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            841665                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.538821                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         279806250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953397                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          350                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         175509435                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        175509435                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst     23374617                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23374617                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst     18241170                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18241170                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457775                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       457775                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst       460281                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460281                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst      41615787                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41615787                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst     41615787                       # number of overall hits
system.cpu.dcache.overall_hits::total        41615787                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       583566                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        583566                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst       541192                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       541192                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8333                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         8333                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.inst      1124758                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1124758                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst      1124758                       # number of overall misses
system.cpu.dcache.overall_misses::total       1124758                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8637456588                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8637456588                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21531074313                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21531074313                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    117993250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    117993250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst        52502                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        52502                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  30168530901                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  30168530901                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  30168530901                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  30168530901                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst     23958183                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23958183                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst     18782362                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18782362                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466108                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466108                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst       460283                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460283                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst     42740545                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42740545                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst     42740545                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42740545                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024358                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.024358                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028814                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.028814                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017878                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017878                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.026316                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.026316                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.026316                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.026316                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14801.164886                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14801.164886                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39784.539152                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39784.539152                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.756390                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.756390                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        26251                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26251                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26822.241674                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26822.241674                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26822.241674                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26822.241674                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       697864                       # number of writebacks
system.cpu.dcache.writebacks::total            697864                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45894                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45894                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242687                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       242687                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       288581                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       288581                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       288581                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       288581                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       537672                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       537672                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298505                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298505                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8333                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8333                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst       836177                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       836177                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst       836177                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       836177                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6873353393                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6873353393                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11227746403                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11227746403                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    101298750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    101298750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst        48498                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        48498                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18101099796                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  18101099796                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18101099796                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  18101099796                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5791247750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5791247750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439329000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439329000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230576750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230576750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022442                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022442                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015893                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015893                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017878                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017878                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019564                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.019564                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019564                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019564                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.543486                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.543486                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37613.260759                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37613.260759                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.336253                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        24249                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24249                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.031370                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         269945589000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.031370                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064461                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064461                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     27970377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     27970377                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     27970377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     27970377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     27970377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     27970377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119531.525641                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119531.525641                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119531.525641                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119531.525641                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119531.525641                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     15801377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     15801377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2215530472                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2215530472                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     15801377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     15801377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     15801377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     15801377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67527.252137                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67527.252137                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------