path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.854944                       # Number of seconds simulated
sim_ticks                                2854944380500                       # Number of ticks simulated
final_tick                               2854944380500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 264512                       # Simulator instruction rate (inst/s)
host_op_rate                                   319813                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6754449586                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588784                       # Number of bytes of host memory used
host_seconds                                   422.68                       # Real time elapsed on the host
sim_insts                                   111803105                       # Number of instructions simulated
sim_ops                                     135177203                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker         6784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1665024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9168492                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10841388                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1665024                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1665024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7956736                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7974260                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          106                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26016                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143779                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                169918                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124324                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128705                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2376                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               583207                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3211443                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3797408                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          583207                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             583207                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2787002                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6138                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2793140                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2787002                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2376                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              583207                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3217581                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6590548                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        169918                       # Number of read requests accepted
system.physmem.writeReqs                       128705                       # Number of write requests accepted
system.physmem.readBursts                      169918                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     128705                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10866560                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7986688                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10841388                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7974260                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10675                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10444                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10743                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10387                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13022                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10182                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10267                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10712                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10430                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10642                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10231                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9545                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10746                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11530                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10184                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10050                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7937                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7870                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8420                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7905                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7296                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7361                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7425                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7903                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7956                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8136                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7613                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7341                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8127                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8673                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7491                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7338                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          64                       # Number of times write queue was full causing retry
system.physmem.totGap                    2854943930000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169361                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124324                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    159846                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9630                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6616                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      166                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60346                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      312.418122                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     185.510807                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     328.995418                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21664     35.90%     35.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14701     24.36%     60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6745     11.18%     71.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3562      5.90%     77.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2510      4.16%     81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1679      2.78%     84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1014      1.68%     85.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1006      1.67%     87.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7465     12.37%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60346                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6177                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.486158                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      583.334644                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6176     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6177                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6177                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.202687                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.306581                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.265718                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5466     88.49%     88.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              67      1.08%     89.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              30      0.49%     90.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              47      0.76%     90.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             264      4.27%     95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              28      0.45%     95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              18      0.29%     95.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.10%     95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               9      0.15%     96.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               7      0.11%     96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.11%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             143      2.32%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.02%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.11%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               5      0.08%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            11      0.18%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             3      0.05%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.05%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.23%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             3      0.05%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.06%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             5      0.08%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             4      0.06%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6177                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4574555750                       # Total ticks spent queuing
system.physmem.totMemAccLat                7758118250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    848950000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26942.43                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45692.43                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.37                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140247                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93988                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.30                       # Row buffer hit rate for writes
system.physmem.avgGap                      9560361.83                       # Average gap between requests
system.physmem.pageHitRate                      79.51                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  217834260                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  115781655                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 617124480                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                324250740                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6010564560.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4580096490                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              375795840                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12507827490                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8401113600                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       671912403285                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             705065679060                       # Total energy per rank (pJ)
system.physmem_0.averagePower              246.963017                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2843582682250                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      706056250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2555890000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2794607920750                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21877952250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      7767045000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  27429516250                       # Time in different power states
system.physmem_1.actEnergy                  213043320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  113231415                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 595176120                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                327163500                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6093540960.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4507043580                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              367350240                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       12209497470                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        8677272480                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       672029778480                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             705136507095                       # Total energy per rank (pJ)
system.physmem_1.averagePower              246.987826                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2844096160000                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      691055750                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2591938000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2794723975250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  22596980000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      7565161250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  26775270250                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31068063                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16834819                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2474290                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18684214                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                10413110                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.732128                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7904720                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1504932                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3038151                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2849063                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           189088                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       109706                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                     67808                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                67808                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44545                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23263                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        67808                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           67808    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        67808                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7897                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 10074.838546                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8443.809763                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7240.808120                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         7014     88.82%     88.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767          876     11.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-212991            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::245760-262143            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7897                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       276581000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6507     82.40%     82.40% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1390     17.60%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7897                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        67808                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        67808                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7897                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7897                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        75705                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24693754                       # DTB read hits
system.cpu.dtb.read_misses                      60831                       # DTB read misses
system.cpu.dtb.write_hits                    19411318                       # DTB write hits
system.cpu.dtb.write_misses                      6977                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4277                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1491                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1775                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       779                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24754585                       # DTB read accesses
system.cpu.dtb.write_accesses                19418295                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44105072                       # DTB hits
system.cpu.dtb.misses                           67808                       # DTB misses
system.cpu.dtb.accesses                      44172880                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                      5860                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5860                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          319                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5541                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5860                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5860    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5860                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3216                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 10484.452736                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8664.992606                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  6927.635793                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1845     57.37%     57.37% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383          815     25.34%     82.71% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          549     17.07%     99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::24576-32767            6      0.19%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3216                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       276141500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2906     90.36%     90.36% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.64%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3216                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5860                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5860                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3216                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3216                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         9076                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57505769                       # ITB inst hits
system.cpu.itb.inst_misses                       5860                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2934                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8328                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57511629                       # ITB inst accesses
system.cpu.itb.hits                          57505769                       # DTB hits
system.cpu.itb.misses                            5860                       # DTB misses
system.cpu.itb.accesses                      57511629                       # DTB accesses
system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     887942089.664688                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17437807884.014717                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2969     97.89%     97.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           58      1.91%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499966671100                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    161816022547                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2693128357953                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        323634999                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   111803105                       # Number of instructions committed
system.cpu.committedOps                     135177203                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7783284                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5386318328                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.894687                       # CPI: cycles per instruction
system.cpu.ipc                               0.345460                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                90612203     67.03%     67.03% # Class of committed instruction
system.cpu.op_class_0::IntMult                 113141      0.08%     67.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc             8473      0.01%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::MemRead               24199534     17.90%     85.03% # Class of committed instruction
system.cpu.op_class_0::MemWrite              20230283     14.97%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead              2708      0.00%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite             8524      0.01%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                135177203                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       217984467                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       105650532                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            844606                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.945154                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42562338                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            845118                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.362598                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         330588500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.945154                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         175904316                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        175904316                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23049763                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23049763                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18249075                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18249075                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       357182                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        357182                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443419                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443419                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460030                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460030                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41298838                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41298838                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41656020                       # number of overall hits
system.cpu.dcache.overall_hits::total        41656020                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       464983                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        464983                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548530                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548530                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       169407                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       169407                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22402                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22402                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1013513                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1013513                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1182920                       # number of overall misses
system.cpu.dcache.overall_misses::total       1182920                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7335235000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7335235000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26749219979                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26749219979                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    303724500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    303724500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       169000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       169000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  34084454979                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34084454979                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  34084454979                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34084454979                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23514746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23514746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18797605                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18797605                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526589                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526589                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465821                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465821                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460032                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460032                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42312351                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42312351                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42838940                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42838940                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019774                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.019774                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029181                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029181                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321706                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.321706                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048091                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048091                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023953                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023953                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.027613                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.027613                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15775.275655                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15775.275655                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48765.281715                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48765.281715                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13557.918936                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13557.918936                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        84500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        84500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33630.012618                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33630.012618                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28813.829320                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28813.829320                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          813                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    36.954545                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       701993                       # number of writebacks
system.cpu.dcache.writebacks::total            701993                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45638                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45638                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249404                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249404                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14200                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14200                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       295042                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       295042                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       295042                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       295042                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419345                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       419345                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299126                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       299126                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121262                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121262                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8202                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8202                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       718471                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       718471                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       839733                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       839733                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6449852500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6449852500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14240256000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14240256000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1658671000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1658671000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    118600500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    118600500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       167000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       167000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20690108500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  20690108500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22348779500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22348779500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6305317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6305317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6305317500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6305317500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017833                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017833                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015913                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015913                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230278                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230278                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017608                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017608                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016980                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016980                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019602                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019602                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15380.778357                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15380.778357                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47606.212767                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47606.212767                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13678.407085                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13678.407085                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14459.948793                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14459.948793                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        83500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28797.416319                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28797.416319                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.149378                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.149378                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202547.944105                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202547.944105                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107390.358347                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107390.358347                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           2890432                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.371135                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54606166                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2890944                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.888697                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       16096310500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.371135                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998772                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998772                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60388077                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60388077                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     54606166                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54606166                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54606166                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54606166                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54606166                       # number of overall hits
system.cpu.icache.overall_hits::total        54606166                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2890956                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2890956                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2890956                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2890956                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2890956                       # number of overall misses
system.cpu.icache.overall_misses::total       2890956                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39801907000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39801907000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39801907000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39801907000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39801907000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39801907000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57497122                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57497122                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57497122                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57497122                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57497122                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57497122                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050280                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050280                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050280                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050280                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050280                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050280                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13767.731851                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13767.731851                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13767.731851                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13767.731851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13767.731851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13767.731851                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      2890432                       # number of writebacks
system.cpu.icache.writebacks::total           2890432                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2890956                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2890956                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2890956                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2890956                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2890956                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2890956                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36910952000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36910952000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36910952000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36910952000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36910952000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36910952000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050280                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050280                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050280                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050280                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050280                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050280                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12767.732197                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12767.732197                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12767.732197                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12767.732197                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12767.732197                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12767.732197                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            96713                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65145.108369                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7318914                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162108                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            45.148383                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     100163301000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.225039                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.032952                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12109.105789                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 52965.744589                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001072                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.184770                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.808193                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994035                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           46                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65349                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           45                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4579                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60686                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000702                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997147                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60066606                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60066606                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68164                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3376                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          71540                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       701993                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       701993                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      2839731                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      2839731                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         2785                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         2785                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       167030                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       167030                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2867992                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2867992                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534347                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       534347                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        68164                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3376                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2867992                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       701377                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3640909                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        68164                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3376                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2867992                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       701377                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3640909                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          106                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          108                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       129309                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       129309                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22923                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22923                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14458                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14458                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          106                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22923                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143767                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        166798                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          106                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22923                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143767                       # number of overall misses
system.cpu.l2cache.overall_misses::total       166798                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     35537000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       193500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     35730500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       172000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       172000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       164000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       164000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12000174000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12000174000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2393515000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2393515000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1752753500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1752753500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     35537000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       193500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2393515000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13752927500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  16182173000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     35537000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       193500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2393515000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13752927500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  16182173000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        68270                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3378                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        71648                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       701993                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       701993                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      2839731                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      2839731                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2791                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2791                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296339                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296339                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2890915                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2890915                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548805                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548805                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        68270                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3378                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2890915                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       845144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3807707                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        68270                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3378                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2890915                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       845144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3807707                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001553                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000592                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001507                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.002150                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.002150                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436355                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.436355                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007929                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007929                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026345                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026345                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001553                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000592                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007929                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.170109                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.043805                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001553                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000592                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007929                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.170109                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.043805                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 335254.716981                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        96750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 330837.962963                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28666.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28666.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92802.310744                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92802.310744                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104415.434280                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104415.434280                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121230.702725                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121230.702725                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 335254.716981                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        96750                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104415.434280                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95661.226151                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97016.588928                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 335254.716981                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        96750                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104415.434280                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95661.226151                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97016.588928                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        88134                       # number of writebacks
system.cpu.l2cache.writebacks::total            88134                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           15                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           15                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          143                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          143                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          143                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          158                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          143                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          158                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          106                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          108                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129309                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       129309                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22908                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22908                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14315                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14315                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          106                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22908                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143624                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166640                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          106                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22908                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143624                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       166640                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34249                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61833                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     34477000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       173500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34650500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       112000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       112000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       144000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       144000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10707084000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10707084000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2162492500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2162492500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1597831000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1597831000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     34477000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       173500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2162492500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12304915000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  14502058000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     34477000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       173500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2162492500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12304915000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14502058000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    216819500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5916117000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6132936500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    216819500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5916117000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6132936500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001553                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000592                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001507                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.002150                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.002150                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436355                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436355                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007924                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007924                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026084                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026084                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001553                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000592                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007924                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.169940                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.043764                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001553                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000592                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007924                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.169940                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.043764                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        86750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 320837.962963                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18666.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18666.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82802.310744                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82802.310744                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94399.009080                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94399.009080                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111619.350332                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111619.350332                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        86750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94399.009080                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85674.504261                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87026.272204                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        86750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94399.009080                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85674.504261                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87026.272204                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190045.518792                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179069.067710                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100761.607112                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99185.491566                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      7504755                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768676                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58052                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          184                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          184                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         136721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3576628                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       790127                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      2890432                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       151192                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2791                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2793                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296339                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296339                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2890956                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       549028                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq         4410                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp           13                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8678540                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2658068                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14779                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       159341                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11510728                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370205760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99209257                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       273080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          469701609                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      132371                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               5775904                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      4004544                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.022245                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.147479                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3915463     97.78%     97.78% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              89081      2.22%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4004544                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     7425335000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       287877                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4341709800                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1314266535                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      11403994                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      91100441                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46325500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               623000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6084500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            39097500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187729822                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.033985                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         272037045000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.033985                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064624                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064624                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     37405377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     37405377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4361655445                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4361655445                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4399060822                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4399060822                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4399060822                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4399060822                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 159852.038462                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 159852.038462                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.891039                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120407.891039                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120661.057162                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120661.057162                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120661.057162                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120661.057162                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     25705377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     25705377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2548589823                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2548589823                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2574295200                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2574295200                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2574295200                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2574295200                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109852.038462                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 109852.038462                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70356.388665                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70356.388665                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70609.885348                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70609.885348                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70609.885348                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70609.885348                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests        336307                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       137733                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          538                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               34249                       # Transaction distribution
system.membus.trans_dist::ReadResp              71814                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       124324                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8813                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129187                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129187                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37565                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4361                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       445694                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553262                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 626159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16498528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16662313                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                18979433                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             4865                       # Total snoops (count)
system.membus.snoopTraffic                      32128                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            264939                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.018563                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.134975                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  260021     98.14%     98.14% # Request fanout histogram
system.membus.snoop_fanout::1                    4918      1.86%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              264939                       # Request fanout histogram
system.membus.reqLayer0.occupancy            92843000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1694500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           903707925                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          987836250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            5807414                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------