path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.852648                       # Number of seconds simulated
sim_ticks                                2852648357500                       # Number of ticks simulated
final_tick                               2852648357500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 166579                       # Simulator instruction rate (inst/s)
host_op_rate                                   201414                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4236074446                       # Simulator tick rate (ticks/s)
host_mem_usage                                 625784                       # Number of bytes of host memory used
host_seconds                                   673.42                       # Real time elapsed on the host
sim_insts                                   112177181                       # Number of instructions simulated
sim_ops                                     135636113                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         8192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1670464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9187820                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10867564                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1670464                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1670464                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7983168                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8000692                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          128                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26101                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144081                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170327                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124737                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               129118                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               585584                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3220804                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3809640                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          585584                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             585584                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2798511                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2804654                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2798511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2872                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              585584                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3226947                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6614294                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170327                       # Number of read requests accepted
system.physmem.writeReqs                       129118                       # Number of write requests accepted
system.physmem.readBursts                      170327                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     129118                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10891072                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8012864                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10867564                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8000692                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40818                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10912                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10835                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10722                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10734                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13360                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10814                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11148                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10988                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10136                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10280                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10233                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9195                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10314                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10738                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10036                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9728                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8115                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8199                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8378                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8308                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7548                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7862                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8189                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8102                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7754                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7814                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7662                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7060                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7768                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7969                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7379                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7094                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
system.physmem.totGap                    2852647955000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169770                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124737                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163101                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6778                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60792                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      310.959863                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.660922                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.542835                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22288     36.66%     36.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14645     24.09%     60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6538     10.75%     71.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3485      5.73%     77.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2623      4.31%     81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1593      2.62%     84.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1118      1.84%     86.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1065      1.75%     87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7437     12.23%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60792                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6289                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.056766                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      539.634570                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6287     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6289                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6289                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.907934                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.344478                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.522535                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5503     87.50%     87.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              53      0.84%     88.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             178      2.83%     91.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              46      0.73%     91.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              61      0.97%     92.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             176      2.80%     95.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.30%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.10%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              12      0.19%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.16%     96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.13%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.08%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             165      2.62%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.08%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.06%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.27%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6289                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1698489250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4889233000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    850865000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9980.96                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28730.96                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.43                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140383                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94198                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.22                       # Row buffer hit rate for writes
system.physmem.avgGap                      9526450.45                       # Average gap between requests
system.physmem.pageHitRate                      79.41                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  240748200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  131360625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 698201400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                419262480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83613121875                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1638239679750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1909662992970                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.436876                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2725220726500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95255940000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32164219750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  218839320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  119406375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 629140200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                392040000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82051531065                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1639609496250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1909341071850                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.324025                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2727521283250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95255940000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     29871038250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31035995                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16848460                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2529330                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18616538                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13364370                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             71.787622                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7827743                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1524480                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     66851                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                66851                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44044                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22807                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        66851                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           66851    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        66851                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7848                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11969.673802                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  9947.704899                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7432.490287                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         6134     78.16%     78.16% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767         1708     21.76%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7848                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    260813000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       260813000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    260813000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6448     82.16%     82.16% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1400     17.84%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7848                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66851                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66851                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7848                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7848                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        74699                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24795366                       # DTB read hits
system.cpu.dtb.read_misses                      59924                       # DTB read misses
system.cpu.dtb.write_hits                    19459513                       # DTB write hits
system.cpu.dtb.write_misses                      6927                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4353                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1315                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1793                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       738                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24855290                       # DTB read accesses
system.cpu.dtb.write_accesses                19466440                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44254879                       # DTB hits
system.cpu.dtb.misses                           66851                       # DTB misses
system.cpu.dtb.accesses                      44321730                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5476                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5476                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5156                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5476                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5476    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5476                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3185                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12111.930926                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10073.036735                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7077.069157                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1309     41.10%     41.10% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383         1163     36.51%     77.61% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          712     22.35%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3185                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    260408500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       260408500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    260408500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2875     90.27%     90.27% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.73%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3185                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5476                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5476                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3185                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3185                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8661                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57644793                       # ITB inst hits
system.cpu.itb.inst_misses                       5476                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2975                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8375                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57650269                       # ITB inst accesses
system.cpu.itb.hits                          57644793                       # DTB hits
system.cpu.itb.misses                            5476                       # DTB misses
system.cpu.itb.accesses                      57650269                       # DTB accesses
system.cpu.numCycles                        315472495                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112177181                       # Number of instructions committed
system.cpu.committedOps                     135636113                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7815514                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5389884731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.812270                       # CPI: cycles per instruction
system.cpu.ipc                               0.355585                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       227521960                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        87950535                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            843739                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.948229                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42652951                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            844251                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.521647                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         310642500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.948229                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999899                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999899                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176384491                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176384491                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23097762                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23097762                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18292469                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18292469                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356103                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356103                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460142                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460142                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41390231                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41390231                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41746334                       # number of overall hits
system.cpu.dcache.overall_hits::total        41746334                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       493938                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        493938                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548534                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548534                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       170153                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       170153                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22409                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22409                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1042472                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1042472                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1212625                       # number of overall misses
system.cpu.dcache.overall_misses::total       1212625                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7285426000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7285426000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  23290524980                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  23290524980                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    282897500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    282897500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  30575950980                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  30575950980                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  30575950980                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  30575950980                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23591700                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23591700                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18841003                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18841003                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526256                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526256                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460144                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460144                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42432703                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42432703                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42958959                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42958959                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020937                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020937                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029114                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029114                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323327                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.323327                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048093                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048093                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024568                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024568                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028228                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028228                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14749.677085                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14749.677085                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42459.583143                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42459.583143                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12624.280423                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12624.280423                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29330.237148                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29330.237148                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25214.679707                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25214.679707                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          276                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.545455                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       699258                       # number of writebacks
system.cpu.dcache.writebacks::total            699258                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75585                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        75585                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249712                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249712                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14175                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14175                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       325297                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       325297                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       325297                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       325297                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418353                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       418353                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298822                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298822                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121703                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121703                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8234                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8234                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       717175                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       717175                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       838878                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       838878                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5919321500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5919321500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12456778000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12456778000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1615525000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1615525000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109204500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109204500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18376099500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  18376099500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19991624500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19991624500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5909109000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5909109000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4568792500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4568792500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10477901500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10477901500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017733                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017733                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015860                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015860                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231262                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231262                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017671                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017671                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016901                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016901                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019527                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019527                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14149.107333                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14149.107333                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41686.281465                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41686.281465                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13274.323558                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13274.323558                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13262.630556                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13262.630556                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25622.894691                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25622.894691                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23831.384897                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23831.384897                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189832.594449                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189832.594449                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165637.983541                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165637.983541                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.730442                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.730442                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2894405                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.404377                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54741020                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2894917                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.909357                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15461690500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.404377                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998837                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998837                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60530877                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60530877                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54741020                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54741020                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54741020                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54741020                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54741020                       # number of overall hits
system.cpu.icache.overall_hits::total        54741020                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2894929                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2894929                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2894929                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2894929                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2894929                       # number of overall misses
system.cpu.icache.overall_misses::total       2894929                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39235778500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39235778500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39235778500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39235778500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39235778500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39235778500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57635949                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57635949                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57635949                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57635949                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57635949                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57635949                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050228                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050228                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050228                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050228                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050228                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050228                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.278336                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13553.278336                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13553.278336                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13553.278336                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894929                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2894929                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2894929                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2894929                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2894929                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2894929                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3191                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3191                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36340850500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36340850500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36340850500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36340850500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36340850500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36340850500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    248718500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    248718500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    248718500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    248718500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050228                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050228                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050228                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.278681                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.278681                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.278681                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            97027                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65057.378732                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7025854                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162288                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            43.292505                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47465.165488                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.060465                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009465                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12271.489149                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5249.654166                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.724261                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001084                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187248                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.080103                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992697                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           65                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2298                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55841                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000992                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60441725                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60441725                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        70902                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4431                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          75333                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       699258                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       699258                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           51                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           51                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164486                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164486                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2871960                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2871960                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534033                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       534033                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        70902                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4431                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2871960                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       698519                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3645812                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        70902                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4431                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2871960                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       698519                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3645812                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          128                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          130                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2782                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2782                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131508                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131508                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22945                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22945                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14252                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14252                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          128                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22945                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145760                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168835                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          128                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22945                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145760                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168835                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     11086500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       371000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     11457500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1074500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1074500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10184937000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10184937000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1831389500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1831389500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1184928500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1184928500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     11086500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       371000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1831389500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11369865500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13212712500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     11086500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       371000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1831389500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11369865500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13212712500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        71030                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4433                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        75463                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       699258                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       699258                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2833                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2833                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295994                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295994                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2894905                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2894905                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548285                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548285                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        71030                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4433                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2894905                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       844279                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3814647                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        71030                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4433                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2894905                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       844279                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3814647                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000451                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001723                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.981998                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981998                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.444293                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.444293                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007926                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007926                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.025994                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.025994                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000451                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007926                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172644                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044260                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000451                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007926                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172644                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044260                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       185500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88134.615385                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   386.232926                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   386.232926                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77447.280774                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77447.280774                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79816.495969                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79816.495969                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83141.208251                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83141.208251                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       185500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78004.016877                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78258.136642                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       185500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78004.016877                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78258.136642                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88547                       # number of writebacks
system.cpu.l2cache.writebacks::total            88547                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           24                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           24                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          128                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          130                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2782                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2782                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131508                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131508                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22921                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22921                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14111                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14111                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          128                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22921                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145619                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168670                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          128                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22921                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145619                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168670                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34319                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61902                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       351000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     10157500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     57758000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     57758000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8869857000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8869857000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1601051500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1601051500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1033348500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1033348500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       351000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1601051500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9903205500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11514414500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       351000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1601051500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9903205500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11514414500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    199170000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519970000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5719140000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4251529500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4251529500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    199170000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771499500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9970669500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001723                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.981998                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981998                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444293                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007918                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025737                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025737                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044216                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044216                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78134.615385                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20761.322789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20761.322789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67447.280774                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67447.280774                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69850.857292                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73229.997874                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73229.997874                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177331.341557                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166646.464058                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154135.862669                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154135.862669                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.879512                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.847436                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         134609                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3577964                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       824000                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2989342                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2833                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2835                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295994                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295994                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894929                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       548519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8639925                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2647968                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15065                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160688                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11463646                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185478080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98978525                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17732                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       284120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284758457                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      194907                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      7812293                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.034587                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.182731                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            7542089     96.54%     96.54% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             270204      3.46%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        7812293                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4534239000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       213000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4347433988                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1312866777                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10632499                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      89658000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187463964                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.030996                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270425383000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.030996                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064437                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064437                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29161877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29161877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4271869087                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4271869087                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29161877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29161877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29161877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29161877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124623.405983                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117929.248206                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117929.248206                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124623.405983                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124623.405983                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17461877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17461877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460669087                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2460669087                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17461877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17461877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17461877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17461877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67929.248206                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67929.248206                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               34319                       # Transaction distribution
system.membus.trans_dist::ReadResp              71715                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::Writeback            124737                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8493                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4596                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129696                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129696                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37396                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455889                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       563451                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 672351                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16551136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16714909                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19032029                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              507                       # Total snoops (count)
system.membus.snoop_fanout::samples            403270                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  403270    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              403270                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87538000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1706000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           881842801                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          999291900                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64464474                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------