path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.852655                       # Number of seconds simulated
sim_ticks                                2852654988500                       # Number of ticks simulated
final_tick                               2852654988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 116178                       # Simulator instruction rate (inst/s)
host_op_rate                                   140471                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2957977243                       # Simulator tick rate (ticks/s)
host_mem_usage                                 618900                       # Number of bytes of host memory used
host_seconds                                   964.39                       # Real time elapsed on the host
sim_insts                                   112040950                       # Number of instructions simulated
sim_ops                                     135468925                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         8064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1669952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9187372                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10866412                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1669952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1669952                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7981376                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7998900                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          126                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26093                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144074                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170309                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124709                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               129090                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2827                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               585403                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3220639                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3809228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          585403                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             585403                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2797876                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2804019                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2797876                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2827                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              585403                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3226782                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6613247                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170309                       # Number of read requests accepted
system.physmem.writeReqs                       129090                       # Number of write requests accepted
system.physmem.readBursts                      170309                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     129090                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10890880                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8010944                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10866412                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7998900                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40828                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10905                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10842                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10713                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10735                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13349                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10818                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11158                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10982                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10119                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10274                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10247                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9187                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10322                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10753                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10041                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9725                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8109                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8208                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8370                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8304                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7540                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7865                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8185                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8104                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7740                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7807                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7671                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7052                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7765                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7977                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7383                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7091                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    2852654585000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169752                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124709                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6752                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60691                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      311.442553                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     184.035683                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.553660                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22186     36.56%     36.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14675     24.18%     60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6464     10.65%     71.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3592      5.92%     77.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2485      4.09%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1671      2.75%     84.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1111      1.83%     85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1120      1.85%     87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7387     12.17%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60691                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6290                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.051669                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      539.627643                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6288     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6290                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6290                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.900000                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.361154                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.375647                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5497     87.39%     87.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              61      0.97%     88.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             183      2.91%     91.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              46      0.73%     92.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              63      1.00%     93.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             171      2.72%     95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.30%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.13%     96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              10      0.16%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.16%     96.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               3      0.05%     96.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.03%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             171      2.72%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.03%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.08%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               3      0.05%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.06%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.24%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6290                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1692148250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4882835750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    850850000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9943.87                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28693.87                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140376                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94273                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.30                       # Row buffer hit rate for writes
system.physmem.avgGap                      9527936.25                       # Average gap between requests
system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  240143400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  131030625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 698115600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                419158800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186321127200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83459244105                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1638379332000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1909648151730                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.429846                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2725453951250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95256200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31938521250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  218680560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  119319750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 629202600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                391949280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186321127200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82079606700                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1639589540250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1909349426340                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.325127                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2727485699500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95256200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     29912992000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31017301                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16826801                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2510748                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18518050                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13329905                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             71.983308                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7858653                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1517345                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     65935                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                65935                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43131                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22804                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        65935                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           65935    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        65935                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7817                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11967.954458                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  9949.329384                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7404.205030                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         6115     78.23%     78.23% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767         1696     21.70%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7817                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    260813000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       260813000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    260813000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6422     82.15%     82.15% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1395     17.85%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7817                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65935                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65935                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7817                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7817                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        73752                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24760096                       # DTB read hits
system.cpu.dtb.read_misses                      58949                       # DTB read misses
system.cpu.dtb.write_hits                    19444061                       # DTB write hits
system.cpu.dtb.write_misses                      6986                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4353                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1337                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1780                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       739                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24819045                       # DTB read accesses
system.cpu.dtb.write_accesses                19451047                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44204157                       # DTB hits
system.cpu.dtb.misses                           65935                       # DTB misses
system.cpu.dtb.accesses                      44270092                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5452                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5452                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          318                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5134                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5452                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5452    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5452                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3184                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12119.032663                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10076.122020                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7085.501487                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1309     41.11%     41.11% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383         1160     36.43%     77.54% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          714     22.42%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3184                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    260408500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       260408500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    260408500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2874     90.26%     90.26% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.74%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3184                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5452                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5452                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3184                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3184                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8636                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57598025                       # ITB inst hits
system.cpu.itb.inst_misses                       5452                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2973                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8340                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57603477                       # ITB inst accesses
system.cpu.itb.hits                          57598025                       # DTB hits
system.cpu.itb.misses                            5452                       # DTB misses
system.cpu.itb.accesses                      57603477                       # DTB accesses
system.cpu.numCycles                        315393196                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112040950                       # Number of instructions committed
system.cpu.committedOps                     135468925                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7774524                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5389977386                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.814981                       # CPI: cycles per instruction
system.cpu.ipc                               0.355242                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       227419103                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        87974093                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            843754                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.948230                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42602633                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            844266                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.461150                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         310642500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.948230                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999899                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999899                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176183318                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176183318                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23061882                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23061882                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18277764                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18277764                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356325                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356325                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443565                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443565                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460145                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460145                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41339646                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41339646                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41695971                       # number of overall hits
system.cpu.dcache.overall_hits::total        41695971                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       494235                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        494235                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548281                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548281                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       170165                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       170165                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22392                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22392                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1042516                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1042516                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1212681                       # number of overall misses
system.cpu.dcache.overall_misses::total       1212681                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7291153500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7291153500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  23268838480                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  23268838480                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    283155000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    283155000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  30559991980                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  30559991980                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  30559991980                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  30559991980                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23556117                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23556117                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18826045                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18826045                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526490                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526490                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465957                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465957                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460147                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460147                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42382162                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42382162                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42908652                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42908652                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020981                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020981                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029124                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029124                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323207                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.323207                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048056                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048056                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024598                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024598                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028262                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028262                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14752.402197                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14752.402197                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42439.622165                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42439.622165                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12645.364416                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12645.364416                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29313.691090                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29313.691090                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25200.355229                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25200.355229                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          269                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.809524                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       699241                       # number of writebacks
system.cpu.dcache.writebacks::total            699241                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75816                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        75816                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249572                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249572                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14161                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14161                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       325388                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       325388                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       325388                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       325388                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418419                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       418419                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298709                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298709                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121784                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121784                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8231                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8231                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       717128                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       717128                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       838912                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       838912                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5922558000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5922558000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12450120000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12450120000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1618736500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1618736500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109455500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109455500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18372678000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  18372678000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19991414500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19991414500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5909069000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5909069000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4568816000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4568816000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10477885000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10477885000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017763                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017763                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015867                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015867                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231313                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231313                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017665                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017665                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016921                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016921                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019551                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019551                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14154.610570                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14154.610570                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41679.761909                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41679.761909                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13291.865105                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13291.865105                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13297.958936                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13297.958936                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25619.802880                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25619.802880                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23830.168719                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23830.168719                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189831.309432                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189831.309432                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165638.835515                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165638.835515                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.449405                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.449405                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2895998                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.404759                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54692690                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2896510                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.882272                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15448784500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.404759                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998837                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998837                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          196                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60485733                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60485733                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54692690                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54692690                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54692690                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54692690                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54692690                       # number of overall hits
system.cpu.icache.overall_hits::total        54692690                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2896522                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2896522                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2896522                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2896522                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2896522                       # number of overall misses
system.cpu.icache.overall_misses::total       2896522                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39250501500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39250501500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39250501500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39250501500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39250501500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39250501500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57589212                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57589212                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57589212                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57589212                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57589212                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57589212                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050296                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050296                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050296                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050296                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050296                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050296                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.907433                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13550.907433                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.907433                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13550.907433                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.907433                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13550.907433                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2896522                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2896522                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2896522                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2896522                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2896522                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2896522                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3191                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3191                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36353980500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36353980500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36353980500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36353980500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36353980500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36353980500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    248718500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    248718500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    248718500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    248718500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050296                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050296                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050296                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.907778                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.907778                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.907778                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            97004                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65057.313836                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7028000                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162262                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            43.312667                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47442.808035                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.645866                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000381                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12256.178987                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5286.680567                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.723920                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001093                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187014                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.080668                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992696                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           62                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           62                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2294                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6931                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55849                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000946                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60457516                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60457516                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        70014                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4411                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          74425                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       699241                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       699241                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           51                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           51                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164459                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164459                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2873562                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2873562                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534090                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       534090                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        70014                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4411                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2873562                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       698549                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3646536                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        70014                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4411                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2873562                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       698549                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3646536                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          126                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          127                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2798                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2798                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131405                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131405                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22938                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22938                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14340                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14340                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          126                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22938                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145745                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168810                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          126                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22938                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145745                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168810                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     11282500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        82500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     11365000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1076000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1076000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10178186000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10178186000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1825056000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1825056000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1190867500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1190867500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     11282500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        82500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1825056000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11369053500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13205474500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     11282500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        82500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1825056000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11369053500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13205474500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        70140                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4412                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        74552                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       699241                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       699241                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2849                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2849                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295864                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295864                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2896500                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2896500                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548430                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548430                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        70140                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4412                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2896500                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       844294                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3815346                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        70140                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4412                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2896500                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       844294                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3815346                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000227                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001704                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982099                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982099                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.444140                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.444140                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007919                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007919                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026147                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026147                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000227                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007919                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172624                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044245                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000227                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007919                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172624                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044245                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        82500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 89488.188976                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   384.560400                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   384.560400                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77456.611240                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77456.611240                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79564.739733                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79564.739733                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83045.153417                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83045.153417                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79564.739733                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78006.473635                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78226.849713                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79564.739733                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78006.473635                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78226.849713                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88519                       # number of writebacks
system.cpu.l2cache.writebacks::total            88519                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          140                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          140                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          126                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2798                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2798                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131405                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131405                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22913                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22913                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14200                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14200                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          126                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22913                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145605                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168645                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          126                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22913                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145605                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168645                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34319                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61902                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        72500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     10095000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     58085500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     58085500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8864136000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8864136000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1594702500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1594702500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1038186000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1038186000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        72500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1594702500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9902322000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11507119500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        72500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1594702500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9902322000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11507119500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    199170000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519931000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5719101000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4251556500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4251556500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    199170000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771487500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9970657500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001704                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982099                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982099                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444140                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444140                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007911                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025892                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025892                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172458                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044202                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172458                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044202                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79488.188976                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20759.649750                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.649750                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67456.611240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67456.611240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69598.153886                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73111.690141                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73111.690141                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68008.117853                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68232.793738                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68008.117853                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68232.793738                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177330.088666                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166645.327661                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154136.841533                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154136.841533                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.675121                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.653581                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         133644                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3578737                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       823959                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2990642                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2849                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2851                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295864                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295864                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2896522                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       548664                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8644384                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2648037                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14998                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       158879                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11466298                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185580160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98978397                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       280560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284856765                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      194832                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      7814541                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.034451                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.182385                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            7545321     96.55%     96.55% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             269220      3.45%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        7814541                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4535355500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       213000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4349852430                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1312899273                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10586000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      88739000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187477706                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.030922                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270445541000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.030922                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064433                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064433                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29161877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29161877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4273547829                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4273547829                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29161877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29161877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29161877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29161877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124623.405983                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117975.591569                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117975.591569                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124623.405983                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124623.405983                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             9                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17461877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17461877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2462347829                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2462347829                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17461877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17461877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17461877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17461877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67975.591569                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67975.591569                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               34319                       # Transaction distribution
system.membus.trans_dist::ReadResp              71793                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::Writeback            124709                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8498                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4604                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4606                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129599                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129599                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37474                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455849                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       563411                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 672311                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16548192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16711965                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19029085                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              506                       # Total snoops (count)
system.membus.snoop_fanout::samples            403242                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  403242    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              403242                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87534500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1700500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           881620222                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          999181641                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64440498                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------