path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.858505                       # Number of seconds simulated
sim_ticks                                2858505242500                       # Number of ticks simulated
final_tick                               2858505242500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 171882                       # Simulator instruction rate (inst/s)
host_op_rate                                   207819                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4390877747                       # Simulator tick rate (ticks/s)
host_mem_usage                                 578076                       # Number of bytes of host memory used
host_seconds                                   651.01                       # Real time elapsed on the host
sim_insts                                   111897168                       # Number of instructions simulated
sim_ops                                     135292215                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1705984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9156972                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10871852                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1705984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1705984                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7955328                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7972852                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26656                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143599                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170394                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124302                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128683                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2754                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               596810                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3203413                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3803335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          596810                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             596810                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2783038                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6130                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2789168                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2783038                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2754                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              596810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3209543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6592503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170394                       # Number of read requests accepted
system.physmem.writeReqs                       128683                       # Number of write requests accepted
system.physmem.readBursts                      170394                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     128683                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10896320                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7985280                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10871852                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7972852                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10648                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11113                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10810                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10613                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13551                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10292                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10857                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10932                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10292                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10622                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10100                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9078                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10356                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10810                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10110                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10071                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7962                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8429                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8465                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8172                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7181                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7509                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7876                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8019                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7862                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8101                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7665                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6948                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7780                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7432                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7363                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    2858504798000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169837                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124302                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    162916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      7039                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61459                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      307.217495                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.591879                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.526171                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22578     36.74%     36.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14767     24.03%     60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6693     10.89%     71.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3646      5.93%     77.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2555      4.16%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2031      3.30%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1005      1.64%     86.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1119      1.82%     88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7065     11.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61459                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6091                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.951896                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      574.936120                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6090     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6091                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6090                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.486535                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.508732                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.308920                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5400     88.67%     88.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             109      1.79%     90.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              32      0.53%     90.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              43      0.71%     91.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              35      0.57%     92.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              14      0.23%     92.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              47      0.77%     93.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              15      0.25%     93.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             145      2.38%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               5      0.08%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.08%     96.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.23%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              63      1.03%     97.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.15%     97.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.08%     97.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              27      0.44%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              95      1.56%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.11%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6090                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1821948750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5014230000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    851275000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10701.29                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29451.29                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.82                       # Average write queue length when enqueuing
system.physmem.readRowHits                     139699                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93863                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.21                       # Row buffer hit rate for writes
system.physmem.avgGap                      9557755.35                       # Average gap between requests
system.physmem.pageHitRate                      79.16                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  240408000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  131175000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 692764800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                412173360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186703564320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86549850225                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1639181430000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1913911365705                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.550023                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2726766742000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95451720000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     36286757000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  224214480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  122339250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 635216400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                396290880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186703564320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85109194890                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1640445162750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1913635982970                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.453685                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2728879759500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95451720000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     34173617000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                30988279                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16810499                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2467893                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18543680                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                10372624                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.936168                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7863209                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1506080                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3044381                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2857246                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           187135                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       108257                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     66151                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                66151                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43510                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22641                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        66151                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           66151    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        66151                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7866                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  8425.510925                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767         7859     99.91%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7866                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    517922000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       517922000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    517922000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6508     82.74%     82.74% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1358     17.26%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7866                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66151                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66151                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7866                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7866                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        74017                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24710832                       # DTB read hits
system.cpu.dtb.read_misses                      59358                       # DTB read misses
system.cpu.dtb.write_hits                    19424403                       # DTB write hits
system.cpu.dtb.write_misses                      6793                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4350                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1526                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1789                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       754                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24770190                       # DTB read accesses
system.cpu.dtb.write_accesses                19431196                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44135235                       # DTB hits
system.cpu.dtb.misses                           66151                       # DTB misses
system.cpu.dtb.accesses                      44201386                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5761                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5761                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          327                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5434                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5761                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5761                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3206                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12829.694323                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7417.860411                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383         2464     76.86%     76.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767          741     23.11%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3206                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    517267500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       517267500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    517267500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2896     90.33%     90.33% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.67%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3206                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5761                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5761                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3206                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3206                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8967                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57333922                       # ITB inst hits
system.cpu.itb.inst_misses                       5761                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2992                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8365                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57339683                       # ITB inst accesses
system.cpu.itb.hits                          57333922                       # DTB hits
system.cpu.itb.misses                            5761                       # DTB misses
system.cpu.itb.accesses                      57339683                       # DTB accesses
system.cpu.numCycles                        332822103                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   111897168                       # Number of instructions committed
system.cpu.committedOps                     135292215                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7734017                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5384249089                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.974357                       # CPI: cycles per instruction
system.cpu.ipc                               0.336207                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                90691008     67.03%     67.04% # Class of committed instruction
system.cpu.op_class_0::IntMult                 113025      0.08%     67.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc             8533      0.01%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::MemRead               24225299     17.91%     85.03% # Class of committed instruction
system.cpu.op_class_0::MemWrite              20252013     14.97%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                135292215                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       228131430                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       104690673                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            842468                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.899803                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42541757                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            842980                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.465915                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.899803                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         175934547                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        175934547                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23016254                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23016254                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18262412                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18262412                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356302                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356302                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443705                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443705                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460205                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460205                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41278666                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41278666                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41634968                       # number of overall hits
system.cpu.dcache.overall_hits::total        41634968                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       493842                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        493842                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       547981                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       547981                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       169870                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       169870                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22311                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22311                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1041823                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1041823                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1211693                       # number of overall misses
system.cpu.dcache.overall_misses::total       1211693                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   8047572500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8047572500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  35605363979                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  35605363979                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292635500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    292635500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  43652936479                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  43652936479                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  43652936479                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  43652936479                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23510096                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23510096                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18810393                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18810393                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526172                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526172                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466016                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466016                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460207                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460207                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42320489                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42320489                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42846661                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42846661                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021006                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.021006                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029132                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029132                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322841                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.322841                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047876                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047876                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024617                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024617                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028280                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028280                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16295.844622                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16295.844622                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64975.544734                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64975.544734                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13116.198288                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13116.198288                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41900.530588                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41900.530588                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36026.399822                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          306                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.304348                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       699681                       # number of writebacks
system.cpu.dcache.writebacks::total            699681                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76216                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        76216                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249477                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249477                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14071                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14071                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       325693                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       325693                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       325693                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       325693                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417626                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       417626                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298504                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298504                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121419                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121419                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8240                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8240                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       716130                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       716130                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       837549                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       837549                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6547764500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6547764500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19179621500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19179621500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1710969500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1710969500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114416000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114416000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25727386000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25727386000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27438355500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27438355500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277881000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277881000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6277881000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6277881000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017764                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017764                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015869                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015869                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230759                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230759                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017682                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017682                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016922                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016922                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019548                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019548                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.536537                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280                       # average overall mshr uncacheable latency
system.cpu.icache.tags.replacements           2894371                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.208818                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54430342                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2894883                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.802260                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18407091500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.208818                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998455                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998455                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          201                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60220131                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60220131                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54430342                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54430342                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54430342                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54430342                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54430342                       # number of overall hits
system.cpu.icache.overall_hits::total        54430342                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2894895                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2894895                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2894895                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2894895                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2894895                       # number of overall misses
system.cpu.icache.overall_misses::total       2894895                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  40452971500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  40452971500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  40452971500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  40452971500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  40452971500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  40452971500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57325237                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57325237                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57325237                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57325237                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57325237                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57325237                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050499                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050499                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050499                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050499                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050499                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050499                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.899399                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13973.899399                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.899399                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13973.899399                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13973.899399                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      2894371                       # number of writebacks
system.cpu.icache.writebacks::total           2894371                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894895                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2894895                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2894895                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2894895                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2894895                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2894895                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3763                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3763                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37558077500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  37558077500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37558077500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  37558077500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37558077500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  37558077500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485921500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    485921500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    485921500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    485921500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050499                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050499                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050499                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050499                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050499                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050499                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.899744                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.899744                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.replacements            96490                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65016.669962                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7024998                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           161737                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            43.434700                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    66.002490                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000511                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12184.043868                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5484.988939                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.721460                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001007                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.185914                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.083694                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992076                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65193                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2277                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6859                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55942                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000824                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994766                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60430282                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60430282                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        71969                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4812                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          76781                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       699681                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       699681                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      2843248                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      2843248                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           49                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164802                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164802                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2871936                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2871936                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       532893                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       532893                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        71969                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4812                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2871936                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       697695                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3646412                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        71969                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4812                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2871936                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       697695                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3646412                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          123                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          124                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2729                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2729                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130929                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130929                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22929                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22929                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14387                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14387                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          123                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22929                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145316                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168369                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          123                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22929                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145316                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168369                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     17201000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       132500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     17333500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2805500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      2805500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16777223500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16777223500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2992993000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2992993000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1908318000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1908318000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     17201000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       132500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2992993000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18685541500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  21695868000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     17201000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       132500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2992993000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18685541500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  21695868000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        72092                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4813                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        76905                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       699681                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       699681                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      2843248                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      2843248                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2778                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2778                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295731                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295731                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2894865                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2894865                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       547280                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       547280                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        72092                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4813                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2894865                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       843011                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3814781                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        72092                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4813                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2894865                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       843011                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3814781                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001706                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000208                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001612                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982361                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982361                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.442730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.442730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007921                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007921                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026288                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026288                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001706                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000208                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007921                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172377                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044136                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001706                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000208                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007921                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172377                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044136                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139845.528455                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 139786.290323                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1028.032246                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1028.032246                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128139.858244                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128139.858244                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130533.080379                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130533.080379                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132641.829429                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132641.829429                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139845.528455                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130533.080379                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128585.575573                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128859.041748                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139845.528455                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130533.080379                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128585.575573                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128859.041748                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        88112                       # number of writebacks
system.cpu.l2cache.writebacks::total            88112                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          140                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          140                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          123                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          124                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2729                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2729                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130929                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130929                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22904                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22904                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14247                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14247                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          123                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22904                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145176                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168204                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          123                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22904                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145176                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168204                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34891                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62474                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16093500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    185652500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    185652500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15467933500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15467933500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2761977000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2761977000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1748121000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1748121000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2761977000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17216054500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  19994125000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       122500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2761977000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17216054500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  19994125000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    427218000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888707000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315925000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    427218000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5888707000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6315925000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982361                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982361                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442730                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442730                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007912                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026032                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026032                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172211                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044093                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172211                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044093                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129786.290323                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      7506242                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768367                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58373                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          592                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          592                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         134878                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3577264                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       823992                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      2894371                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       151399                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2778                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2780                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295731                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295731                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894895                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       547514                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8691656                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2651684                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16008                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160884                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11520232                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370751872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98928925                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        19252                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       288368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          469988417                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      192705                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4072528                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.021538                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.145168                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3984815     97.85%     97.85% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              87713      2.15%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4072528                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     7427836500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       378877                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4348460548                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1310984681                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      11196996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      88824919                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46452000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               104000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               331500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                85500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6139500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            34107000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187147502                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.037066                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         274806935000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.037066                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064817                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064817                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29059377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29059377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4548977125                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4548977125                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4578036502                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4578036502                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4578036502                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4578036502                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124185.371795                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125570.149268                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125570.149268                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125570.149268                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125570.149268                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17359377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17359377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736351620                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2736351620                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2753710997                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2753710997                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2753710997                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2753710997                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75531.049344                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75531.049344                       # average overall mshr miss latency
system.membus.trans_dist::ReadReq               34891                       # Transaction distribution
system.membus.trans_dist::ReadResp              72400                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       124302                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8612                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4581                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129077                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129077                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37509                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450878                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558440                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 631337                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16527584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16691357                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19008477                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              506                       # Total snoops (count)
system.membus.snoop_fanout::samples            402790                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  402790    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              402790                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87987000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1702000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           879699870                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          990225250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1263123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------