path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.858301                       # Number of seconds simulated
sim_ticks                                2858301146500                       # Number of ticks simulated
final_tick                               2858301146500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 158663                       # Simulator instruction rate (inst/s)
host_op_rate                                   191838                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4049033168                       # Simulator tick rate (ticks/s)
host_mem_usage                                 629392                       # Number of bytes of host memory used
host_seconds                                   705.92                       # Real time elapsed on the host
sim_insts                                   112003872                       # Number of instructions simulated
sim_ops                                     135422492                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         7936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1692928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9156716                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10858604                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1692928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1692928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7945984                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7963508                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          124                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26452                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143595                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170187                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124156                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128537                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2776                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               592285                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3203552                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3798971                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          592285                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             592285                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2779967                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6131                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2786098                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2779967                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2776                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              592285                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3209683                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6585070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170187                       # Number of read requests accepted
system.physmem.writeReqs                       128537                       # Number of write requests accepted
system.physmem.readBursts                      170187                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     128537                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10884288                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7975936                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10858604                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7963508                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40806                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10600                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10887                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11108                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10980                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13553                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10410                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10585                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10816                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10327                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10604                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9912                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9123                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10363                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10770                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10067                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9962                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7842                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8249                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8721                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8464                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7420                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7583                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7625                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7909                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7872                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8104                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7451                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6976                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7788                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7975                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7387                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7258                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
system.physmem.totGap                    2858300743000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169630                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124156                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6497                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7541                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61607                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      306.136640                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.409953                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.199512                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22530     36.57%     36.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14842     24.09%     60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6878     11.16%     71.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3579      5.81%     77.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2575      4.18%     81.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2036      3.30%     85.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1091      1.77%     86.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1049      1.70%     88.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7027     11.41%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61607                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6204                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.410058                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      569.248357                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6203     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6204                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6204                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.087685                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.454852                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.723718                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5415     87.28%     87.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              82      1.32%     88.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              29      0.47%     89.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             170      2.74%     91.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              36      0.58%     92.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             140      2.26%     94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              51      0.82%     95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.15%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              26      0.42%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.27%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.13%     96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             160      2.58%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.03%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              20      0.32%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.06%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.05%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.13%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.05%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6204                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1827154250                       # Total ticks spent queuing
system.physmem.totMemAccLat                5015910500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    850335000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10743.73                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29493.73                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.50                       # Average write queue length when enqueuing
system.physmem.readRowHits                     139389                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93694                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.17                       # Row buffer hit rate for writes
system.physmem.avgGap                      9568366.60                       # Average gap between requests
system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  240959880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  131476125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 693724200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                413508240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186689833200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86986692810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1638672097500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1913828291955                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.570205                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2725916009250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95444700000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     36932994500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  224789040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  122652750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 632790600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                394055280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186689833200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85302372735                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1640149571250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1913516064855                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.460970                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2728391286000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95444700000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     34465013500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31040865                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16831531                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2506988                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18486474                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13317466                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.038973                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7868005                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1514854                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     66489                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                66489                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43580                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22909                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        66489                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           66489    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        66489                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7766                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  8498.851872                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767         7759     99.91%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7766                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    513949000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       513949000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    513949000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6383     82.19%     82.19% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1383     17.81%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7766                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66489                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66489                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7766                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7766                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        74255                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24754555                       # DTB read hits
system.cpu.dtb.read_misses                      59253                       # DTB read misses
system.cpu.dtb.write_hits                    19441053                       # DTB write hits
system.cpu.dtb.write_misses                      7236                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4351                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1268                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1795                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       764                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24813808                       # DTB read accesses
system.cpu.dtb.write_accesses                19448289                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44195608                       # DTB hits
system.cpu.dtb.misses                           66489                       # DTB misses
system.cpu.dtb.accesses                      44262097                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5448                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5448                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5128                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5448                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5448                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3191                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12717.173300                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7372.723577                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383         2455     76.94%     76.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767          735     23.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3191                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    513294500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       513294500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    513294500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2881     90.29%     90.29% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.71%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3191                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5448                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5448                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3191                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3191                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8639                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57598121                       # ITB inst hits
system.cpu.itb.inst_misses                       5448                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2979                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8499                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57603569                       # ITB inst accesses
system.cpu.itb.hits                          57598121                       # DTB hits
system.cpu.itb.misses                            5448                       # DTB misses
system.cpu.itb.accesses                      57603569                       # DTB accesses
system.cpu.numCycles                        332010047                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112003872                       # Number of instructions committed
system.cpu.committedOps                     135422492                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7777324                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3034                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5384653012                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.964273                       # CPI: cycles per instruction
system.cpu.ipc                               0.337351                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3034                       # number of quiesce instructions executed
system.cpu.tickCycles                       227998615                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       104011432                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            840949                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.900791                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42597434                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            841461                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.623183                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         590729500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.900791                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999806                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999806                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176149332                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176149332                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23058407                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23058407                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18275243                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18275243                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356879                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356879                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443776                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443776                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460246                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460246                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41333650                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41333650                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41690529                       # number of overall hits
system.cpu.dcache.overall_hits::total        41690529                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       492651                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        492651                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       547770                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       547770                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       169693                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       169693                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22295                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22295                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1040421                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1040421                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1210114                       # number of overall misses
system.cpu.dcache.overall_misses::total       1210114                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   8002189000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8002189000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  35630203980                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  35630203980                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292207000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    292207000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  43632392980                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  43632392980                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  43632392980                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  43632392980                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23551058                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23551058                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18823013                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18823013                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526572                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526572                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466071                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466071                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460248                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460248                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42374071                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42374071                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42900643                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42900643                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020918                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020918                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029101                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029101                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322260                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.322260                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047836                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047836                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024553                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024553                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028207                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028207                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.119368                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.119368                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65045.920697                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65045.920697                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13106.391568                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13106.391568                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41937.247499                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41937.247499                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36056.431857                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36056.431857                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          277                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.043478                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       698521                       # number of writebacks
system.cpu.dcache.writebacks::total            698521                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76580                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        76580                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249277                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249277                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14066                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14066                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       325857                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       325857                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       325857                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       325857                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       416071                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       416071                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298493                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298493                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121470                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121470                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8229                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8229                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       714564                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       714564                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       836034                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       836034                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6493922500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6493922500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19218375500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19218375500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1715298500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1715298500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114624000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114624000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25712298000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25712298000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27427596500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27427596500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5937313500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5937313500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4787315000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4787315000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10724628500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10724628500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017667                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017667                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015858                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015858                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230681                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230681                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017656                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017656                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016863                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016863                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019488                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019488                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15607.726806                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15607.726806                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64384.677363                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64384.677363                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14121.169836                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14121.169836                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13929.274517                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13929.274517                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35983.198146                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35983.198146                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32806.795537                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32806.795537                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190738.675790                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190738.675790                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173560.345140                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173560.345140                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182668.128630                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182668.128630                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2897329                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.212489                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54691304                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2897841                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.873121                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18295812500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.212489                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998462                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998462                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60487009                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60487009                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54691304                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54691304                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54691304                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54691304                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54691304                       # number of overall hits
system.cpu.icache.overall_hits::total        54691304                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2897853                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2897853                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2897853                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2897853                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2897853                       # number of overall misses
system.cpu.icache.overall_misses::total       2897853                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  40491792500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  40491792500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  40491792500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  40491792500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  40491792500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  40491792500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57589157                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57589157                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57589157                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57589157                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57589157                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57589157                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050319                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050319                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050319                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050319                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050319                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050319                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.031931                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13973.031931                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.031931                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13973.031931                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.031931                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13973.031931                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897853                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2897853                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2897853                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2897853                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2897853                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2897853                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3490                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3490                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3490                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3490                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37593940500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  37593940500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37593940500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  37593940500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37593940500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  37593940500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    450883500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    450883500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    450883500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    450883500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050319                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050319                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050319                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.032276                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.032276                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.032276                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129192.979943                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129192.979943                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129192.979943                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129192.979943                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            96606                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65026.172791                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7027132                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           161852                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            43.417023                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47537.333831                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    67.598904                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000505                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12131.683782                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5289.555770                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.725362                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001031                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.185115                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.080712                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992221                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           50                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2273                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6868                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55936                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000763                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60448944                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60448944                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        72083                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4650                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          76733                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       698521                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       698521                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           47                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           47                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164594                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164594                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2874830                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2874830                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       531579                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       531579                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        72083                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4650                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2874830                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       696173                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3647736                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        72083                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4650                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2874830                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       696173                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3647736                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          124                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          125                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2732                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2732                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131125                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131125                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22992                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22992                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14186                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14186                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          124                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22992                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145311                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168428                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          124                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22992                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145311                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168428                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     16852000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       132500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     16984500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      3066500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      3066500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16810889000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16810889000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   3007737500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   3007737500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1878016500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1878016500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     16852000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       132500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   3007737500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18688905500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  21713627500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     16852000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       132500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   3007737500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18688905500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  21713627500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        72207                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4651                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        76858                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       698521                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       698521                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2779                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2779                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295719                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295719                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2897822                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2897822                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       545765                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       545765                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        72207                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4651                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2897822                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       841484                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3816164                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        72207                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4651                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2897822                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       841484                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3816164                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000215                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001626                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.983087                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.983087                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.443411                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.443411                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007934                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007934                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.025993                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.025993                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000215                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007934                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172684                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044135                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000215                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007934                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172684                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044135                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135903.225806                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total       135876                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1122.437775                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1122.437775                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128205.063870                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128205.063870                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130816.697112                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130816.697112                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132385.203722                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132385.203722                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135903.225806                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.697112                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128613.150415                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128919.345358                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135903.225806                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.697112                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128613.150415                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128919.345358                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        87966                       # number of writebacks
system.cpu.l2cache.writebacks::total            87966                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           19                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          160                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          124                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          125                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2732                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2732                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131125                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131125                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22973                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22973                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14045                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14045                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          124                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22973                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145170                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168268                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          124                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22973                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145170                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168268                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3490                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34618                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3490                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62201                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     15612000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15734500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    193275000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    193275000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15499639000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15499639000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2776629500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2776629500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1720074500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1720074500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     15612000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2776629500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17219713500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20012077500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     15612000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       122500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2776629500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17219713500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20012077500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    396548000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5548169500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5944717500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4470099000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4470099000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    396548000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10018268500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10414816500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001626                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.983087                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.983087                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.443411                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443411                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007928                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025735                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025735                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172517                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044093                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172517                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044093                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       125876                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      7509435                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770131                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58870                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          575                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          575                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         134592                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3578420                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       822692                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2989768                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2779                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2781                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295719                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295719                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897853                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       545999                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8648477                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2639755                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15227                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161605                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11465064                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185683904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98756893                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18604                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       288828                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284748229                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      192861                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      7812074                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.018867                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.136054                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            7664687     98.11%     98.11% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             147387      1.89%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        7812074                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4533598000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       377377                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4352382759                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1308632806                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10576000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      89410974                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186368011                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.036757                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         274667845000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.036757                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064797                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064797                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29104877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29104877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4697807134                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4697807134                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29104877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29104877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29104877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29104877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124379.816239                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124379.816239                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124379.816239                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124379.816239                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124379.816239                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17404877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17404877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886607134                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2886607134                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17404877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17404877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17404877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17404877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74379.816239                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74379.816239                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               34618                       # Transaction distribution
system.membus.trans_dist::ReadResp              71995                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::Writeback            124156                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8653                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4582                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4584                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129275                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129275                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37377                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455163                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562725                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 671625                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16504992                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16668765                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                18985885                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              506                       # Total snoops (count)
system.membus.snoop_fanout::samples            402707                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  402707    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              402707                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87547000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1701500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           878616291                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          998538415                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64594078                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------