path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.858997                       # Number of seconds simulated
sim_ticks                                2858997339500                       # Number of ticks simulated
final_tick                               2858997339500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 120078                       # Simulator instruction rate (inst/s)
host_op_rate                                   145187                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3059253370                       # Simulator tick rate (ticks/s)
host_mem_usage                                 579060                       # Number of bytes of host memory used
host_seconds                                   934.54                       # Real time elapsed on the host
sim_insts                                   112217626                       # Number of instructions simulated
sim_ops                                     135683579                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker         8000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1706880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9150764                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10866732                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1706880                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1706880                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7954240                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7971764                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          125                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26670                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143502                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170314                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124285                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128666                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2798                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               597020                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3200690                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3800889                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          597020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             597020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2782178                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6129                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2788308                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2782178                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2798                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              597020                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3206819                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6589197                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170314                       # Number of read requests accepted
system.physmem.writeReqs                       128666                       # Number of write requests accepted
system.physmem.readBursts                      170314                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     128666                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10892160                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7936                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7984576                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10866732                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7971764                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      124                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10846                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10861                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10970                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10944                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13948                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10354                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10606                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10917                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10091                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10226                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9938                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9330                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10171                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10932                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10237                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9819                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8179                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8215                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8623                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8456                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7543                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7549                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7648                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8016                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7706                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7733                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7506                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7211                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7604                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8124                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7522                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7124                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
system.physmem.totGap                    2858996896000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169757                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124285                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    162889                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      7005                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7032                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6488                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7541                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61663                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      306.126397                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.384465                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.388642                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22560     36.59%     36.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14992     24.31%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6700     10.87%     71.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3651      5.92%     77.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2898      4.70%     82.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1667      2.70%     85.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1045      1.69%     86.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1093      1.77%     88.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7057     11.44%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61663                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6083                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.977314                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      575.322656                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6082     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6083                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6083                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.509453                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.487861                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.653648                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5420     89.10%     89.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              90      1.48%     90.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              39      0.64%     91.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              27      0.44%     91.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              35      0.58%     92.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              16      0.26%     92.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              41      0.67%     93.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               7      0.12%     93.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             151      2.48%     95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.10%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.13%     96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              13      0.21%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              69      1.13%     97.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.07%     97.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.05%     97.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              36      0.59%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              90      1.48%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.16%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             3      0.05%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6083                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1877618250                       # Total ticks spent queuing
system.physmem.totMemAccLat                5068680750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    850950000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11032.48                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29782.48                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.79                       # Average write queue length when enqueuing
system.physmem.readRowHits                     139443                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93842                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.93                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.21                       # Row buffer hit rate for writes
system.physmem.avgGap                      9562502.16                       # Average gap between requests
system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  244104840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  133192125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 697678800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                416203920                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186735603600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86851227465                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1639211384250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1914289395000                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.567370                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2726812979000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95468100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     36713387250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  222067440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  121167750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 629795400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                392234400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186735603600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85246386480                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1640619139500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1913966394570                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.454393                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2729170897750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95468100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     34358196250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31086887                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16880230                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2489626                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18671153                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                10424859                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.834040                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7822517                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1524102                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3081262                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2891722                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           189540                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       109414                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                     67741                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                67741                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        45017                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22724                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        67741                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           67741    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        67741                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7842                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  8407.754568                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767         7835     99.91%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7842                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    517795000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       517795000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    517795000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6453     82.29%     82.29% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1389     17.71%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7842                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        67741                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        67741                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7842                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7842                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        75583                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24787454                       # DTB read hits
system.cpu.dtb.read_misses                      60877                       # DTB read misses
system.cpu.dtb.write_hits                    19460962                       # DTB write hits
system.cpu.dtb.write_misses                      6864                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4270                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1452                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1793                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       741                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24848331                       # DTB read accesses
system.cpu.dtb.write_accesses                19467826                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44248416                       # DTB hits
system.cpu.dtb.misses                           67741                       # DTB misses
system.cpu.dtb.accesses                      44316157                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                      5895                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5895                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5574                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5895                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5895    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5895                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3205                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12907.644306                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7322.763550                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383         2473     77.16%     77.16% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767          731     22.81%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3205                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    517140500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       517140500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    517140500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2896     90.36%     90.36% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           309      9.64%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3205                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5895                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5895                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3205                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3205                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         9100                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57517109                       # ITB inst hits
system.cpu.itb.inst_misses                       5895                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2926                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8405                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57523004                       # ITB inst accesses
system.cpu.itb.hits                          57517109                       # DTB hits
system.cpu.itb.misses                            5895                       # DTB misses
system.cpu.itb.accesses                      57523004                       # DTB accesses
system.cpu.numPwrStateTransitions                6068                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3034                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     887205873.057680                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17434832353.062756                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2969     97.86%     97.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.94%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499967463084                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3034                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    167214720643                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        334432391                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112217626                       # Number of instructions committed
system.cpu.committedOps                     135683579                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7838903                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3034                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5383627132                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.980213                       # CPI: cycles per instruction
system.cpu.ipc                               0.335547                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                90974393     67.05%     67.05% # Class of committed instruction
system.cpu.op_class_0::IntMult                 113069      0.08%     67.13% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc             8525      0.01%     67.14% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.14% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.14% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.14% # Class of committed instruction
system.cpu.op_class_0::MemRead               24296976     17.91%     85.05% # Class of committed instruction
system.cpu.op_class_0::MemWrite              20288279     14.95%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                135683579                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3034                       # number of quiesce instructions executed
system.cpu.tickCycles                       218593350                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       115839041                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            844257                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.899744                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42705909                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            844769                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.553357                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.899744                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176476854                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176476854                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23143905                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23143905                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18298058                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18298058                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356964                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356964                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443845                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443845                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460247                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460247                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41441963                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41441963                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41798927                       # number of overall hits
system.cpu.dcache.overall_hits::total        41798927                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       464900                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        464900                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548479                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548479                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       169396                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       169396                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22217                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22217                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1013379                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1013379                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1182775                       # number of overall misses
system.cpu.dcache.overall_misses::total       1182775                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7474682000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7474682000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  35725670480                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  35725670480                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    298069500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    298069500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  43200352480                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  43200352480                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  43200352480                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  43200352480                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23608805                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23608805                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18846537                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18846537                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526360                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526360                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466062                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466062                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460249                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460249                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42455342                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42455342                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42981702                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42981702                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019692                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.019692                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029102                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029102                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321825                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.321825                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047670                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047670                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023869                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023869                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.027518                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.027518                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42630.005635                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36524.573549                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          235                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.681818                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       701092                       # number of writebacks
system.cpu.dcache.writebacks::total            701092                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45747                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45747                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249493                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249493                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        13970                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        13970                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       295240                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       295240                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       295240                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       295240                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419153                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       419153                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298986                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298986                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121200                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121200                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8247                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8247                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       718139                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       718139                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       839339                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       839339                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6559792500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6559792500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19260233000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19260233000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701865000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701865000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115452000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115452000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25820025500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25820025500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27521890500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27521890500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6298878000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6298878000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6298878000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6298878000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017754                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017754                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015864                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015864                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230261                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230261                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017695                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017695                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016915                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016915                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019528                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019528                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15650.114636                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15650.114636                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64418.511235                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64418.511235                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14041.790429                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14041.790429                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13999.272463                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13999.272463                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35954.077832                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35954.077832                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32789.957931                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32789.957931                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202341.085769                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202341.085769                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107280.682631                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107280.682631                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           2894242                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.201941                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54613603                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2894754                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.866406                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18510731500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.201941                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998441                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998441                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          200                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60403134                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60403134                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     54613603                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54613603                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54613603                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54613603                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54613603                       # number of overall hits
system.cpu.icache.overall_hits::total        54613603                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2894766                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2894766                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2894766                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2894766                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2894766                       # number of overall misses
system.cpu.icache.overall_misses::total       2894766                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  40456280000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  40456280000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  40456280000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  40456280000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  40456280000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  40456280000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57508369                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57508369                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57508369                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57508369                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57508369                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57508369                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050336                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050336                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050336                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050336                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050336                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050336                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13975.665045                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13975.665045                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13975.665045                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13975.665045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13975.665045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13975.665045                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      2894242                       # number of writebacks
system.cpu.icache.writebacks::total           2894242                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894766                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2894766                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2894766                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2894766                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2894766                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2894766                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3758                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3758                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3758                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3758                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37561515000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  37561515000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37561515000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  37561515000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37561515000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  37561515000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485617000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    485617000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    485617000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    485617000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050336                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050336                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050336                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12975.665391                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12975.665391                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12975.665391                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129222.192656                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129222.192656                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129222.192656                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129222.192656                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            96413                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65014.111647                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7029815                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           161656                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            43.486261                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47147.953940                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    65.794382                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.010019                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12263.315434                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5537.037871                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.719421                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001004                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187123                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.084488                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992037                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65189                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2263                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6860                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55955                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000824                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994705                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60474648                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60474648                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        73812                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4869                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          78681                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       701092                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       701092                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      2843365                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      2843365                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           49                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       165406                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       165406                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2871798                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2871798                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534162                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       534162                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        73812                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4869                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2871798                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       699568                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3650047                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        73812                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4869                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2871798                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       699568                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3650047                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          125                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          127                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2735                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2735                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130801                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130801                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22943                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22943                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14433                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14433                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          125                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22943                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145234                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168304                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          125                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22943                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145234                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168304                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     17568500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       265500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     17834000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2884500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      2884500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16851679500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16851679500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2998117000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2998117000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1905130500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1905130500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     17568500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       265500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2998117000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18756810000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  21772761000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     17568500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       265500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2998117000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18756810000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  21772761000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        73937                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4871                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        78808                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       701092                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       701092                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      2843365                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      2843365                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2784                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2784                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296207                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296207                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2894741                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2894741                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548595                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548595                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        73937                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4871                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2894741                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       844802                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3818351                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        73937                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4871                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2894741                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       844802                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3818351                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001691                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000411                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001612                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982399                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982399                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.441586                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.441586                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007926                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007926                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026309                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026309                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001691                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000411                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007926                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.171915                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044078                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001691                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000411                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007926                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.171915                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044078                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker       140548                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 140425.196850                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1054.661792                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1054.661792                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128834.485210                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128834.485210                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130676.764155                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130676.764155                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131998.233216                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131998.233216                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       140548                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130676.764155                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129148.890756                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 129365.677583                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       140548                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130676.764155                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129148.890756                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 129365.677583                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        88095                       # number of writebacks
system.cpu.l2cache.writebacks::total            88095                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           20                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          161                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           20                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          161                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          125                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2735                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2735                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130801                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130801                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22923                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22923                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14292                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14292                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          125                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22923                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145093                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168143                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          125                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22923                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145093                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168143                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3758                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34888                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3758                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62472                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       245500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16564000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186014500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186014500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15543669500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15543669500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2767321000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2767321000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1745198500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1745198500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       245500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2767321000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17288868000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20072753000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       245500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2767321000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17288868000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20072753000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    426993000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5909675000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6336668000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    426993000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5909675000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6336668000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982399                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982399                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.441586                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.441586                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007919                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026052                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026052                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.171748                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044036                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.171748                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044036                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130425.196850                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.614260                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.614260                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      7509695                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770160                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58111                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          594                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          594                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         136822                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3580395                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       825389                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      2894242                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       151717                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2784                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2786                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296207                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296207                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894766                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       548829                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8691264                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2657074                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16340                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       164402                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11529080                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370735360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99133929                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        19484                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       295748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          470184521                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      192671                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               8062744                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      4076067                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.021486                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.144999                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3988487     97.85%     97.85% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              87580      2.15%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4076067                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     7431755500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4348377811                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1313662211                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      11470497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      90488952                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46348000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               107000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               330500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                85500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               623500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               51000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6076000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38906500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187130005                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.038429                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         275018797000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.038429                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064902                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064902                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29054877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29054877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4548884128                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4548884128                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4577939005                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4577939005                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4577939005                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4577939005                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124166.141026                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125567.475040                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125567.475040                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125567.475040                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125567.475040                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17354877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17354877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736261614                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2736261614                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2753616491                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2753616491                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2753616491                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2753616491                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75528.457156                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75528.457156                       # average overall mshr miss latency
system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               34888                       # Transaction distribution
system.membus.trans_dist::ReadResp              72464                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       124285                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4603                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            128933                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128933                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37576                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450661                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558229                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 631126                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16521376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16685161                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19002281                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              504                       # Total snoops (count)
system.membus.snoopTraffic                      32128                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            402659                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  402659    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              402659                       # Request fanout histogram
system.membus.reqLayer0.occupancy            92669500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1708000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           910164615                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          990045000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1264123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------