path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.852850                       # Number of seconds simulated
sim_ticks                                2852849954000                       # Number of ticks simulated
final_tick                               2852849954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 160685                       # Simulator instruction rate (inst/s)
host_op_rate                                   194286                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4092855045                       # Simulator tick rate (ticks/s)
host_mem_usage                                 562916                       # Number of bytes of host memory used
host_seconds                                   697.03                       # Real time elapsed on the host
sim_insts                                   112002684                       # Number of instructions simulated
sim_ops                                     135423332                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10823844                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10832740                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1658560                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1658560                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7967296                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7984820                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             169642                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                169781                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124489                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128870                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2759                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst              3794046                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3797164                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          581370                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             581370                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2792750                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.inst                6143                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2798892                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2792750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2759                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             3800189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6596057                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        169781                       # Number of read requests accepted
system.physmem.writeReqs                       165094                       # Number of write requests accepted
system.physmem.readBursts                      169781                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     165094                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10858880                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10194112                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10832740                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10303156                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5787                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4592                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10675                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10570                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10940                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10884                       # Per bank write bursts
system.physmem.perBankRdBursts::4               12996                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10666                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11098                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10877                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10287                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10457                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10268                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9318                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10425                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10908                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9678                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9623                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10097                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10006                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10747                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10511                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9282                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9914                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10247                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10166                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10178                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10302                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10037                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9553                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10068                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10279                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8984                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8912                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2852849531000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169226                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 160713                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    162999                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     9997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8955                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        62892                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      334.747313                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     194.220308                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     348.895470                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22415     35.64%     35.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14531     23.10%     58.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6612     10.51%     69.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3482      5.54%     74.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2506      3.98%     78.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1581      2.51%     81.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1054      1.68%     82.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1133      1.80%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9578     15.23%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          62892                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6668                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.444061                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      561.318574                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6666     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6668                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6668                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.887672                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.937507                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       22.272912                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5557     83.34%     83.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              39      0.58%     83.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              24      0.36%     84.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             223      3.34%     87.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             119      1.78%     89.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              51      0.76%     90.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              29      0.43%     90.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              45      0.67%     91.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             120      1.80%     93.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.18%     93.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              15      0.22%     93.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.21%     93.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              30      0.45%     94.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              19      0.28%     94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               8      0.12%     94.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              35      0.52%     95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              60      0.90%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               9      0.13%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               6      0.09%     96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              14      0.21%     96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             100      1.50%     97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.06%     97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            13      0.19%     98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             8      0.12%     98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            22      0.33%     98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             3      0.04%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            10      0.15%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            27      0.40%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             9      0.13%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.03%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             8      0.12%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             5      0.07%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.04%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6668                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1702635750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4883948250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    848350000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10034.98                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28784.98                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.57                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.61                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                     139924                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    126136                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.18                       # Row buffer hit rate for writes
system.physmem.avgGap                      8519147.54                       # Average gap between requests
system.physmem.pageHitRate                      80.87                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2713515031250                       # Time in different power states
system.physmem.memoryStateTime::REF       95262700000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       44072132750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 246765960                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 228697560                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 134644125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 124785375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                691906800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                631511400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               524685600                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               507468240                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          186333841200                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          186333841200                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           83199782385                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           82045768365                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1638723732000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1639736025000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1909855358070                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1909608097140                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.456797                       # Core power per rank (mW)
system.physmem.averagePower::1             669.370126                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             157                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31051775                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16857996                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2519060                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18534749                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13337392                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             71.958849                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7856975                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1512712                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24746159                       # DTB read hits
system.cpu.dtb.read_misses                      60199                       # DTB read misses
system.cpu.dtb.write_hits                    19443156                       # DTB write hits
system.cpu.dtb.write_misses                      6950                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4352                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1306                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1783                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       751                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24806358                       # DTB read accesses
system.cpu.dtb.write_accesses                19450106                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44189315                       # DTB hits
system.cpu.dtb.misses                           67149                       # DTB misses
system.cpu.dtb.accesses                      44256464                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                     57672689                       # ITB inst hits
system.cpu.itb.inst_misses                       5411                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2970                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8383                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57678100                       # ITB inst accesses
system.cpu.itb.hits                          57672689                       # DTB hits
system.cpu.itb.misses                            5411                       # DTB misses
system.cpu.itb.accesses                      57678100                       # DTB accesses
system.cpu.numCycles                        314966932                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112002684                       # Number of instructions committed
system.cpu.committedOps                     135423332                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7762811                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3036                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5390780993                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.812137                       # CPI: cycles per instruction
system.cpu.ipc                               0.355601                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3036                       # number of quiesce instructions executed
system.cpu.tickCycles                       228185661                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        86781271                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            843230                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.953176                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42691062                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            843742                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.597294                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         281436250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953176                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176134397                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176134397                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst     23488260                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23488260                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst     18281937                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18281937                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457712                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       457712                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst       460238                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460238                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst      41770197                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41770197                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst     41770197                       # number of overall hits
system.cpu.dcache.overall_hits::total        41770197                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       584617                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        584617                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst       541532                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       541532                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8359                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         8359                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.inst      1126149                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1126149                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst      1126149                       # number of overall misses
system.cpu.dcache.overall_misses::total       1126149                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8658802092                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8658802092                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21460434801                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21460434801                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    117977250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    117977250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       152000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       152000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  30119236893                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  30119236893                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  30119236893                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  30119236893                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst     24072877                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     24072877                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst     18823469                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18823469                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466071                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466071                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst       460240                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460240                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst     42896346                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42896346                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst     42896346                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42896346                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024285                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.024285                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028769                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.028769                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017935                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017935                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.026253                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.026253                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.026253                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.026253                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14811.067916                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14811.067916                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39629.116656                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39629.116656                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14113.799498                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14113.799498                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        76000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        76000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26745.339110                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26745.339110                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       699279                       # number of writebacks
system.cpu.dcache.writebacks::total            699279                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45143                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45143                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242778                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       242778                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       287921                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       287921                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       287921                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       287921                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       539474                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       539474                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298754                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298754                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8359                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8359                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst       838228                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       838228                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst       838228                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       838228                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6896325139                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6896325139                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11211804160                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11211804160                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    101230750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    101230750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       148000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       148000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18108129299                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  18108129299                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18108129299                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  18108129299                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790997000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790997000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439577500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439577500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230574500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230574500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022410                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022410                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015871                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015871                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017935                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017935                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.019541                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019541                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        74000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        74000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2898546                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.424366                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54764882                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2899058                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.890578                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15302672250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.424366                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998876                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998876                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60563021                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60563021                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54764882                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54764882                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54764882                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54764882                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54764882                       # number of overall hits
system.cpu.icache.overall_hits::total        54764882                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2899070                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2899070                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2899070                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2899070                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2899070                       # number of overall misses
system.cpu.icache.overall_misses::total       2899070                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39144211468                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39144211468                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39144211468                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39144211468                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39144211468                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39144211468                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57663952                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57663952                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57663952                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57663952                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57663952                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57663952                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050275                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050275                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050275                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050275                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050275                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050275                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13502.334013                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13502.334013                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13502.334013                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13502.334013                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2899070                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2899070                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2899070                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2899070                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2899070                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2899070                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33336586532                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  33336586532                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33336586532                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  33336586532                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33336586532                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  33336586532                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    222066250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    222066250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    222066250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    222066250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050275                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050275                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050275                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11499.062297                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            96693                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65074.721793                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4049393                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           161936                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            25.006132                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47626.273785                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.769943                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000365                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 17377.677699                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.726719                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001080                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.265162                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992961                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2281                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6890                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55911                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000656                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         36630547                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        36630547                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        71506                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4492                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      3409625                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        3485623                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       699279                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       699279                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.inst           49                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst       164818                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164818                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        71506                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4492                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      3574443                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3650441                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        71506                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4492                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      3574443                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3650441                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          123                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        37236                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        37360                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2769                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2769                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       131123                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131123                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          123                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       168359                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168483                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          123                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       168359                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168483                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      9516500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        74500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2756078250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2765669250                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       839964                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       839964                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst       146000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       146000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9200663428                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9200663428                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9516500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        74500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11956741678                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11966332678                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9516500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        74500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11956741678                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11966332678                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        71629                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4493                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      3446861                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      3522983                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       699279                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       699279                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2818                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2818                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       295941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        71629                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4493                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      3742802                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3818924                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        71629                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4493                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      3742802                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3818924                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000223                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010803                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.010605                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.982612                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982612                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.443071                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.443071                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000223                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.044982                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044118                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000223                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.044982                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044118                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74016.496133                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74027.549518                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   303.345612                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   303.345612                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        73000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        73000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.188861                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.188861                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71023.976769                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71023.976769                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88299                       # number of writebacks
system.cpu.l2cache.writebacks::total            88299                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          156                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          156                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst          156                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          156                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst          156                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          156                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          123                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37080                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        37204                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2769                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2769                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131123                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131123                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          123                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       168203                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168327                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          123                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       168203                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168327                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2281616000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2289681000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27874769                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27874769                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       122000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       122000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7547217572                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7547217572                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9828833572                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9836898572                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        62500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9828833572                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9836898572                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545306500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545306500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4107046000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107046000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652352500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652352500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010758                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010560                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.982612                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982612                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.443071                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443071                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044077                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044077                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        61000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        61000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3581708                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3581608                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       699279                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2818                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2820                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5804102                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2510082                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14997                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161563                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8490744                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185730048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98946845                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17972                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       286516                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284981381                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       60946                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4581834                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.007957                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.088847                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            4545376     99.20%     99.20% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6              36458      0.80%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4581834                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3016682672                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       202500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4358543218                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1342977701                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10504000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      89938750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178466                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480301                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347024164                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36804504                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.033420                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270180945000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.033420                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064589                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064589                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     27950377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     27950377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9603131283                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9603131283                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     27950377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     27950377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     27950377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     27950377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119446.055556                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119446.055556                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119446.055556                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         56022                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7210                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.770042                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     15781377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     15781377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     15781377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     15781377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     15781377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     15781377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               71576                       # Transaction distribution
system.membus.trans_dist::ReadResp              71576                       # Transaction distribution
system.membus.trans_dist::WriteReq              27607                       # Transaction distribution
system.membus.trans_dist::WriteResp             27607                       # Transaction distribution
system.membus.trans_dist::Writeback            124489                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4592                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4594                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129300                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129300                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446065                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 662584                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16500440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16664221                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21299677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              507                       # Total snoops (count)
system.membus.snoop_fanout::samples            332045                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  332045    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              332045                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87455500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1699000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1675329000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1688631909                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38334496                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------