path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.566404                       # Number of seconds simulated
sim_ticks                                2566404096500                       # Number of ticks simulated
final_tick                               2566404096500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 108919                       # Simulator instruction rate (inst/s)
host_op_rate                                   131120                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4613194748                       # Simulator tick rate (ticks/s)
host_mem_usage                                 411228                       # Number of bytes of host memory used
host_seconds                                   556.32                       # Real time elapsed on the host
sim_insts                                    60593541                       # Number of instructions simulated
sim_ops                                      72944224                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.realview.nvmem.bytes_read::cpu.inst          256                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           256                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          256                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          256                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            4                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              4                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           100                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              100                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          100                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          100                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          100                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             100                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         1664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10080024                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131192344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1001408                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1001408                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3810496                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6826568                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           26                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             157526                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15296370                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59539                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813557                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47190748                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst              3927684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51119130                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          390199                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             390199                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1484761                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.inst             1175213                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2659974                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1484761                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47190748                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           648                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             5102897                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53779104                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15296370                       # Number of read requests accepted
system.physmem.writeReqs                       813557                       # Number of write requests accepted
system.physmem.readBursts                    15296370                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     813557                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                978862336                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    105344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6837568                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131192344                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6826568                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1646                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  706692                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4678                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              955907                       # Per bank write bursts
system.physmem.perBankRdBursts::1              955585                       # Per bank write bursts
system.physmem.perBankRdBursts::2              955711                       # Per bank write bursts
system.physmem.perBankRdBursts::3              955918                       # Per bank write bursts
system.physmem.perBankRdBursts::4              957666                       # Per bank write bursts
system.physmem.perBankRdBursts::5              955713                       # Per bank write bursts
system.physmem.perBankRdBursts::6              955586                       # Per bank write bursts
system.physmem.perBankRdBursts::7              955417                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956298                       # Per bank write bursts
system.physmem.perBankRdBursts::9              955963                       # Per bank write bursts
system.physmem.perBankRdBursts::10             955537                       # Per bank write bursts
system.physmem.perBankRdBursts::11             955091                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956282                       # Per bank write bursts
system.physmem.perBankRdBursts::13             955994                       # Per bank write bursts
system.physmem.perBankRdBursts::14             956147                       # Per bank write bursts
system.physmem.perBankRdBursts::15             955909                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6629                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6411                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6529                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6576                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6489                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6741                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6778                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6680                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7055                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6798                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6471                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6090                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7091                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6663                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6989                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6847                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2566402308000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157526                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  59539                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1111407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    958360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    963566                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1076065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    974438                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1039000                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2689873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2594671                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3384839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    130586                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   112191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   103349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                   100054                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    19345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    18516                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18281                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      177                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1014578                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      971.536840                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     905.616961                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     204.240777                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22129      2.18%      2.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22531      2.22%      4.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8793      0.87%      5.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2465      0.24%      5.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2547      0.25%      5.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1763      0.17%      5.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8722      0.86%      6.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          969      0.10%      6.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       944659     93.11%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1014578                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6201                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2466.490405                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    89690.748368                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143         6195     99.90%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06            2      0.03%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6201                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6201                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.228995                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.200624                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.980358                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2397     38.66%     38.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 13      0.21%     38.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3771     60.81%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 16      0.26%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6201                       # Writes before turning the bus around for reads
system.physmem.totQLat                   395011426750                       # Total ticks spent queuing
system.physmem.totMemAccLat              681787501750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76473620000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25826.65                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44576.65                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         381.41                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.66                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.12                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.66                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.27                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.27                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14297539                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89444                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  83.70                       # Row buffer hit rate for writes
system.physmem.avgGap                       159305.64                       # Average gap between requests
system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2209544766500                       # Time in different power states
system.physmem.memoryStateTime::REF       85697820000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      271160177250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.trans_dist::ReadReq            16348869                       # Transaction distribution
system.membus.trans_dist::ReadResp           16348869                       # Transaction distribution
system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
system.membus.trans_dist::Writeback             59539                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4678                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4678                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131592                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131592                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383066                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            8                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3800                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1892039                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4278915                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34556547                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390498                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16908384                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     19306742                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               140417270                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            219423                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  219423    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              219423                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1783264500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                6000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3414000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17618330500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4827152764                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37437958000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq             16322171                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322171                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8178                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8178                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          524                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1032                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383066                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32660698                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15884                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio         1048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         2064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      2390498                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                123501026                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3976000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               524000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               522000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374888000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         38185527000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                12550628                       # Number of BP lookups
system.cpu.branchPred.condPredicted           9093116                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1061685                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8575859                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 6183324                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.101512                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1560078                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             139853                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     13629467                       # DTB read hits
system.cpu.dtb.read_misses                      33605                       # DTB read misses
system.cpu.dtb.write_hits                    11376627                       # DTB write hits
system.cpu.dtb.write_misses                      3703                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3447                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1539                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    252                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       593                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 13663072                       # DTB read accesses
system.cpu.dtb.write_accesses                11380330                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          25006094                       # DTB hits
system.cpu.dtb.misses                           37308                       # DTB misses
system.cpu.dtb.accesses                      25043402                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                     22908933                       # ITB inst hits
system.cpu.itb.inst_misses                       9079                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2384                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      5702                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 22918012                       # ITB inst accesses
system.cpu.itb.hits                          22908933                       # DTB hits
system.cpu.itb.misses                            9079                       # DTB misses
system.cpu.itb.accesses                      22918012                       # DTB accesses
system.cpu.numCycles                        572551547                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    60593541                       # Number of instructions committed
system.cpu.committedOps                      72944224                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       3228444                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                     77492                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   4562038068                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               9.449052                       # CPI: cycles per instruction
system.cpu.ipc                               0.105831                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    82978                       # number of quiesce instructions executed
system.cpu.tickCycles                       466653116                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       105898431                       # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements           1529478                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.463685                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            21373010                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1529990                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             13.969379                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        9990881000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.463685                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998953                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998953                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          191                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          24432991                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         24432991                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     21373010                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        21373010                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      21373010                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         21373010                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     21373010                       # number of overall hits
system.cpu.icache.overall_hits::total        21373010                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1529991                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1529991                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1529991                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1529991                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1529991                       # number of overall misses
system.cpu.icache.overall_misses::total       1529991                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  20681368889                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  20681368889                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  20681368889                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  20681368889                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  20681368889                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  20681368889                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22903001                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22903001                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22903001                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22903001                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22903001                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22903001                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.066803                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.066803                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.066803                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.066803                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.066803                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.066803                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13517.314082                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13517.314082                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1529991                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1529991                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1529991                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1529991                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1529991                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1529991                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17615727111                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  17615727111                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17615727111                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  17615727111                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17615727111                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  17615727111                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    172140750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    172140750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    172140750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    172140750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.066803                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.066803                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.066803                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.066803                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.066803                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.066803                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11513.614859                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3182062                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3182061                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763365                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763365                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       600919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2980                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2980                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       247461                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       247461                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3062730                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5773755                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        28972                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       100548                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8966005                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     97946560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84574454                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        43804                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       165736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          182730554                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       26649                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2846983                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            2846983    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2846983                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3381152937                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2301840639                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2547807667                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      18027487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      59116998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements            65091                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        51567.943403                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2406935                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           130479                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            18.446915                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     2524835361000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36492.360835                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    17.402377                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000576                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 15058.179616                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.556829                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000266                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.229770                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.786864                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           15                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65373                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2561                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6578                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56121                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000229                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997513                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         22965227                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        22965227                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        41408                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10949                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1892934                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1945291                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       600919                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       600919                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.inst           25                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           25                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst       114146                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       114146                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        41408                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10949                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2007080                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2059437                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        41408                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10949                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2007080                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2059437                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           26                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        23655                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23683                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2955                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2955                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       133315                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133315                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           26                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       156970                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156998                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           26                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       156970                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156998                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2068000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1704040750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1706258250                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       348485                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       348485                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9355155027                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9355155027                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2068000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11059195777                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11061413277                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2068000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11059195777                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11061413277                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        41434                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10951                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1916589                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1968974                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       600919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       600919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2980                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2980                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       247461                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       247461                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        41434                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10951                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2164050                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2216435                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        41434                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10951                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2164050                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2216435                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000628                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000183                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012342                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.012028                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.991611                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991611                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.538731                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.538731                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000628                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000183                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.072535                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.070834                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000628                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000183                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.072535                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.070834                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79538.461538                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72037.233143                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72045.697336                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   117.930626                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   117.930626                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70173.311533                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70173.311533                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79538.461538                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70454.200019                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70455.759163                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79538.461538                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70454.200019                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70455.759163                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59539                       # number of writebacks
system.cpu.l2cache.writebacks::total            59539                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           69                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           69                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           69                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           69                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           26                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        23586                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23614                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2955                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2955                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       133315                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133315                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           26                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       156901                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156929                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           26                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       156901                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156929                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1746000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1404219250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1406090250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     29553955                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29553955                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7656846473                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7656846473                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1746000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9061065723                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9062936723                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1746000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9061065723                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9062936723                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167363942750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167363942750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst  16707802808                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16707802808                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184071745558                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184071745558                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000628                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000183                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012306                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.011993                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.991611                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991611                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.538731                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.538731                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000628                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000183                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.072503                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.070802                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000628                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000183                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.072503                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.070802                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59536.133723                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59544.772169                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.338409                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.338409                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57434.245756                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57434.245756                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57750.210152                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57751.828680                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57750.210152                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57751.828680                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            635446                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.959259                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            21828831                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            635958                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             34.324328                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         227074250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959259                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.999920                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999920                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          91723842                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         91723842                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst     11595412                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11595412                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst      9746012                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9746012                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst       236764                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236764                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst       247613                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247613                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst      21341424                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21341424                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst     21341424                       # number of overall hits
system.cpu.dcache.overall_hits::total        21341424                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       458657                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        458657                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst       476663                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       476663                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst        10850                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        10850                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.inst       935320                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         935320                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst       935320                       # number of overall misses
system.cpu.dcache.overall_misses::total        935320                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst   6947637684                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   6947637684                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  22233411759                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  22233411759                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    151795500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    151795500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  29181049443                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  29181049443                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  29181049443                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  29181049443                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst     12054069                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12054069                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst     10222675                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222675                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       247614                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247614                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst       247613                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247613                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst     22276744                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     22276744                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst     22276744                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     22276744                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.038050                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.038050                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.046628                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.046628                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.043818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.041986                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.041986                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.041986                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.041986                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46643.879972                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 46643.879972                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13990.368664                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31199.000816                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31199.000816                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       600919                       # number of writebacks
system.cpu.dcache.writebacks::total            600919                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        80937                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        80937                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       226224                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       226224                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst           71                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           71                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       307161                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       307161                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       307161                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       307161                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       377720                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       377720                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       250439                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       250439                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        10779                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        10779                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst       628159                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       628159                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst       628159                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       628159                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   4824316311                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4824316311                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10814527330                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10814527330                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    129220000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    129220000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  15638843641                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15638843641                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  15638843641                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15638843641                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst  26058035692                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26058035692                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.031335                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031335                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.024498                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024498                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.043531                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.043531                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.028198                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.028198                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.028198                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028198                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1737063641000                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------