path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.853442                       # Number of seconds simulated
sim_ticks                                2853442108500                       # Number of ticks simulated
final_tick                               2853442108500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 171765                       # Simulator instruction rate (inst/s)
host_op_rate                                   207684                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4374009836                       # Simulator tick rate (ticks/s)
host_mem_usage                                 619996                       # Number of bytes of host memory used
host_seconds                                   652.36                       # Real time elapsed on the host
sim_insts                                   112053421                       # Number of instructions simulated
sim_ops                                     135485276                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         7296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1671680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9169380                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10849380                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1671680                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1671680                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7972992                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7990516                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          114                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26120                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143791                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170041                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124578                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128959                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2557                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               585847                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3213445                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3802208                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          585847                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             585847                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2794166                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6141                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2800308                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2794166                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2557                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              585847                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3219587                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6602516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170041                       # Number of read requests accepted
system.physmem.writeReqs                       165183                       # Number of write requests accepted
system.physmem.readBursts                      170041                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     165183                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10875008                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7616                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9072064                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10849380                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10308852                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      119                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23407                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4604                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10431                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10779                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11040                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10735                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13061                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10390                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11080                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11267                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10153                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10232                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10264                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9394                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10277                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10799                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10090                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9930                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8676                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9067                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9547                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9319                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8434                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8678                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9214                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9423                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8918                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8886                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8752                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8449                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8824                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8894                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8297                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8373                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
system.physmem.totGap                    2853441702500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169486                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 160802                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163468                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6406                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6696                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1817                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      100                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61793                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      322.802648                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     189.147121                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     338.470119                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22296     36.08%     36.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14465     23.41%     59.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6637     10.74%     70.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3539      5.73%     75.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2616      4.23%     80.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1600      2.59%     82.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1149      1.86%     84.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1212      1.96%     86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8279     13.40%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61793                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5874                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.927818                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      584.509202                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5873     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5874                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5873                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.134684                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.418054                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       43.798135                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            5542     94.36%     94.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              90      1.53%     95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              17      0.29%     96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              15      0.26%     96.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              16      0.27%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             28      0.48%     97.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            28      0.48%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            13      0.22%     97.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            10      0.17%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             8      0.14%     98.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            17      0.29%     98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            16      0.27%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            10      0.17%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             6      0.10%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             3      0.05%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             5      0.09%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             7      0.12%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             1      0.02%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             5      0.09%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351            11      0.19%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367             8      0.14%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             2      0.03%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             3      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             3      0.05%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::592-607             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5873                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1685079736                       # Total ticks spent queuing
system.physmem.totMemAccLat                4871117236                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    849610000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9916.78                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28666.78                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.18                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.61                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140217                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109661                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.35                       # Row buffer hit rate for writes
system.physmem.avgGap                      8512044.79                       # Average gap between requests
system.physmem.pageHitRate                      80.17                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  242267760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  132189750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 692507400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                468860400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186372491760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83617160895                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1638712655250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1910238133215                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.452112                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2726011845150                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95282460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32147776350                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  224857080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  122689875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 632876400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                449634240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186372491760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82395435150                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1639784344500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1909982329005                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.362464                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2727805815350                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95282460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30353736650                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             157                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31053109                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16852863                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2525514                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18620216                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13364906                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             71.776321                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7853668                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1516989                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     65844                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                65844                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43330                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22514                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        65844                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           65844    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        65844                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7786                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8821.657087                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7338.018596                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         6073     78.00%     78.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767         1707     21.92%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151            1      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::163840-180223            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7786                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    262515000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       262515000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    262515000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6400     82.20%     82.20% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1386     17.80%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7786                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65844                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65844                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7786                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7786                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        73630                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24757406                       # DTB read hits
system.cpu.dtb.read_misses                      59085                       # DTB read misses
system.cpu.dtb.write_hits                    19449348                       # DTB write hits
system.cpu.dtb.write_misses                      6759                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4357                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1268                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1766                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       739                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24816491                       # DTB read accesses
system.cpu.dtb.write_accesses                19456107                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44206754                       # DTB hits
system.cpu.dtb.misses                           65844                       # DTB misses
system.cpu.dtb.accesses                      44272598                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5446                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5446                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5122                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5446                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5446    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5446                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3184                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 11253.454774                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8989.562910                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7050.042435                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1281     40.23%     40.23% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383         1185     37.22%     77.45% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          717     22.52%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3184                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    262109500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       262109500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    262109500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2875     90.30%     90.30% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           309      9.70%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3184                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5446                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5446                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3184                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3184                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8630                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57726188                       # ITB inst hits
system.cpu.itb.inst_misses                       5446                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2973                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8450                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57731634                       # ITB inst accesses
system.cpu.itb.hits                          57726188                       # DTB hits
system.cpu.itb.misses                            5446                       # DTB misses
system.cpu.itb.accesses                      57731634                       # DTB accesses
system.cpu.numCycles                        317415724                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112053421                       # Number of instructions committed
system.cpu.committedOps                     135485276                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7764036                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5389516808                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.832718                       # CPI: cycles per instruction
system.cpu.ipc                               0.353018                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
system.cpu.tickCycles                       228406815                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        89008909                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            842109                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.947879                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42706608                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            842621                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.683057                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         313221250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.947879                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999898                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999898                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          357                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176191359                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176191359                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23499832                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23499832                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18286134                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18286134                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       457571                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       457571                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460116                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460116                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41785966                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41785966                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41785966                       # number of overall hits
system.cpu.dcache.overall_hits::total        41785966                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       583874                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        583874                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       541283                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       541283                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data         8366                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         8366                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1125157                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1125157                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1125157                       # number of overall misses
system.cpu.dcache.overall_misses::total       1125157                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   8774452459                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8774452459                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  23299729316                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  23299729316                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    120081750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    120081750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  32074181775                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  32074181775                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  32074181775                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  32074181775                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     24083706                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     24083706                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18827417                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18827417                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465937                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465937                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460118                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460118                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42911123                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42911123                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42911123                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42911123                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.024244                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.024244                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028750                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.028750                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.017955                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017955                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.026221                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.026221                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.026221                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.026221                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28506.405573                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28506.405573                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       697919                       # number of writebacks
system.cpu.dcache.writebacks::total            697919                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45195                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45195                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       242825                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       242825                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       288020                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       288020                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       288020                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       288020                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       538679                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       538679                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298458                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298458                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8366                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8366                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       837137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       837137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       837137                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       837137                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   7251218502                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   7251218502                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12288582898                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12288582898                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    107501250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    107501250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19539801400                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  19539801400                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19539801400                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19539801400                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5836783750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5836783750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4510033500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4510033500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10346817250                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10346817250                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.022367                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022367                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015852                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015852                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017955                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017955                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.019509                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.019509                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019509                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019509                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81250                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81250                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2898605                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.397830                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54818221                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2899117                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.908592                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15715014250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.397830                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998824                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998824                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          195                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60616478                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60616478                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54818221                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54818221                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54818221                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54818221                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54818221                       # number of overall hits
system.cpu.icache.overall_hits::total        54818221                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2899129                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2899129                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2899129                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2899129                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2899129                       # number of overall misses
system.cpu.icache.overall_misses::total       2899129                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39309012875                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39309012875                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39309012875                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39309012875                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39309012875                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39309012875                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57717350                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57717350                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57717350                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57717350                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57717350                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57717350                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050230                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050230                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050230                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050230                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050230                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050230                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13558.904373                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13558.904373                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13558.904373                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13558.904373                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13558.904373                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13558.904373                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2899129                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2899129                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2899129                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2899129                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2899129                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2899129                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  34950907125                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  34950907125                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  34950907125                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  34950907125                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  34950907125                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  34950907125                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    247386750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    247386750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    247386750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    247386750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050230                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050230                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050230                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050230                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050230                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050230                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.657794                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.657794                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.657794                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.657794                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.657794                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.657794                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            96782                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65059.413288                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4045474                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162031                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.967284                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    67.256900                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000383                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5373.703806                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.722862                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001026                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.186843                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.081996                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992728                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65218                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2276                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6932                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55893                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000473                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995148                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         36598730                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        36598730                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69951                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4476                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      2876131                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       532779                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        3483337                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       697919                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       697919                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           49                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164415                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164415                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        69951                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4476                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2876131                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       697194                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3647752                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        69951                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4476                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2876131                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       697194                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3647752                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          114                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        22980                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        14261                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        37356                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2807                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2807                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131192                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131192                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          114                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22980                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145453                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168548                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          114                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22980                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145453                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168548                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      9734000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        82500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1838541652                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1191731612                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3040089764                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1092965                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1092965                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10173645453                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10173645453                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9734000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        82500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1838541652                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11365377065                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13213735217                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9734000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        82500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1838541652                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11365377065                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13213735217                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        70065                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4477                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      2899111                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       547040                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      3520693                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       697919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       697919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2856                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2856                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295607                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295607                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        70065                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4477                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2899111                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       842647                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3816300                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        70065                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4477                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2899111                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       842647                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3816300                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001627                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000223                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.007927                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026069                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.010610                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982843                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982843                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.443805                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.443805                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001627                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000223                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007927                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172614                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044165                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001627                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000223                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007927                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172614                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044165                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85385.964912                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        82500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80006.164143                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83565.781642                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81381.565585                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   389.371215                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   389.371215                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77547.757889                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77547.757889                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85385.964912                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80006.164143                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78137.797536                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78397.460765                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85385.964912                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80006.164143                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78137.797536                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78397.460765                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88388                       # number of writebacks
system.cpu.l2cache.writebacks::total            88388                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          140                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          162                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          162                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          162                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          114                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        22958                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        14121                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        37194                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2807                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2807                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131192                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131192                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          114                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22958                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145313                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168386                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          114                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22958                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145313                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168386                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8305000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        70000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1550026348                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1005062888                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2563464236                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     49859307                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     49859307                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       136000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       136000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8531883047                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8531883047                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8305000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1550026348                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9536945935                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11095347283                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8305000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        70000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1550026348                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9536945935                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11095347283                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191729750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5400527000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5592256750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4151319000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4151319000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191729750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9551846000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9743575750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001627                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025813                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010564                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982843                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982843                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.443805                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443805                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001627                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172448                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044123                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001627                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172448                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044123                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        70000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67515.739524                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.050492                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68921.445287                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17762.489134                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17762.489134                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        70000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        70000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3579627                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3579531                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       697919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36254                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2856                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295607                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5804583                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2506486                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15045                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       158423                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8484537                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185746048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98788181                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17908                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       280260                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284832397                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       61029                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4577967                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.007970                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.088920                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            4541479     99.20%     99.20% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              36488      0.80%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4577967                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3013390750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       208500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4358889625                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1341438850                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10568000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      88362250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198914708                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36809505                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.032937                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270823051000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.032937                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064559                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064559                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29244877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29244877                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6652334326                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6652334326                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29244877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29244877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29244877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29244877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124978.106838                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124978.106838                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124978.106838                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124978.106838                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124978.106838                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22952                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3496                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.565217                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16937877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16937877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4768676336                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4768676336                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16937877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16937877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16937877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16937877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72384.089744                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72384.089744                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               71726                       # Transaction distribution
system.membus.trans_dist::ReadResp              71726                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::Writeback            124578                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4604                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4606                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129395                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129395                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446695                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554255                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 663142                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16522776                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16686485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21321941                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              504                       # Total snoops (count)
system.membus.snoop_fanout::samples            332271                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  332271    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              332271                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90362500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1704000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1022735199                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          997821410                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37468495                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------