path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.523629                       # Number of seconds simulated
sim_ticks                                2523629285500                       # Number of ticks simulated
final_tick                               2523629285500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  68763                       # Simulator instruction rate (inst/s)
host_op_rate                                    88448                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2863680529                       # Simulator tick rate (ticks/s)
host_mem_usage                                 399792                       # Number of bytes of host memory used
host_seconds                                   881.25                       # Real time elapsed on the host
sim_insts                                    60597236                       # Number of instructions simulated
sim_ops                                      77945371                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            799232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9095696                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129436176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       799232                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          799232                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3784448                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6800520                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           55                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12488                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142154                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15096906                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59132                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813150                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47367363                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1395                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               316699                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3604212                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51289695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          316699                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             316699                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1499605                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1195133                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2694738                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1499605                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47367363                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1395                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              316699                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4799345                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53984433                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15096906                       # Total number of read requests seen
system.physmem.writeReqs                       813150                       # Total number of write requests seen
system.physmem.cpureqs                         218484                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    966201984                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52041600                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              129436176                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6800520                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      390                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4690                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                943619                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                943957                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                943433                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                943463                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                943389                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                943250                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                943110                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                943289                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                943778                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                943634                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               943712                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               943686                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               943739                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               943592                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               943646                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               943219                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50102                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50378                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 49977                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 50030                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50914                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50821                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50673                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50817                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51140                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51219                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51127                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51111                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51352                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51158                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51299                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51032                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     1156336                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2523628152000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      36                       # Categorize read packet sizes
system.physmem.readPktSize::3                14942208                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154662                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                1910354                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  59132                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 4690                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                  14955823                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     89957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6537                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2881                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2334                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2059                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1682                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1270                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1277                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     6283                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     9566                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    13077                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      563                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3067                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32003                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    31809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    31595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    31423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    31264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                    46839255594                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              317495505594                       # Sum of mem lat for all requests
system.physmem.totBusLat                  60386064000                       # Total cycles spent in databus access
system.physmem.totBankLat                210270186000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3102.65                       # Average queueing delay per request
system.physmem.avgBankLat                    13928.39                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  21031.04                       # Average memory access latency
system.physmem.avgRdBW                         382.86                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.62                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.29                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.69                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.52                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.13                       # Average read queue length over time
system.physmem.avgWrQLen                        13.20                       # Average write queue length over time
system.physmem.readRowHits                   15050623                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    784578                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.70                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  96.49                       # Row buffer hit rate for writes
system.physmem.avgGap                       158618.43                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits             15048943                       # DTB read hits
system.cpu.checker.dtb.read_misses               7309                       # DTB read misses
system.cpu.checker.dtb.write_hits            11294215                       # DTB write hits
system.cpu.checker.dtb.write_misses              2189                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults            178                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses         15056252                       # DTB read accesses
system.cpu.checker.dtb.write_accesses        11296404                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                  26343158                       # DTB hits
system.cpu.checker.dtb.misses                    9498                       # DTB misses
system.cpu.checker.dtb.accesses              26352656                       # DTB accesses
system.cpu.checker.itb.inst_hits             61775988                       # ITB inst hits
system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses         61780459                       # ITB inst accesses
system.cpu.checker.itb.hits                  61775988                       # DTB hits
system.cpu.checker.itb.misses                    4471                       # DTB misses
system.cpu.checker.itb.accesses              61780459                       # DTB accesses
system.cpu.checker.numCycles                 78235930                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51393832                       # DTB read hits
system.cpu.dtb.read_misses                      77273                       # DTB read misses
system.cpu.dtb.write_hits                    11807513                       # DTB write hits
system.cpu.dtb.write_misses                     17284                       # DTB write misses
system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     7715                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2923                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    497                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51471105                       # DTB read accesses
system.cpu.dtb.write_accesses                11824797                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63201345                       # DTB hits
system.cpu.dtb.misses                           94557                       # DTB misses
system.cpu.dtb.accesses                      63295902                       # DTB accesses
system.cpu.itb.inst_hits                     11866090                       # ITB inst hits
system.cpu.itb.inst_misses                      12256                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     5202                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      3056                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 11878346                       # ITB inst accesses
system.cpu.itb.hits                          11866090                       # DTB hits
system.cpu.itb.misses                           12256                       # DTB misses
system.cpu.itb.accesses                      11878346                       # DTB accesses
system.cpu.numCycles                        471617242                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 14707934                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11701482                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             783806                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups               9735591                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  7867248                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1454059                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               82839                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           30177247                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       91949952                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14707934                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9321307                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      20604105                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4981007                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     133002                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               96623906                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2605                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        100214                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       208761                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          353                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11862293                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                731589                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6461                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          151283915                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.758817                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.115765                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                130696614     86.39%     86.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1382439      0.91%     87.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1755242      1.16%     88.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2339470      1.55%     90.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2142585      1.42%     91.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1134296      0.75%     92.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2618835      1.73%     93.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   784869      0.52%     94.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8429565      5.57%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            151283915                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.031186                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.194967                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32009474                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              96255861                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18724959                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1031397                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3262224                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2019817                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                174593                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              109260478                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                576218                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3262224                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33806773                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                36827261                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       53335707                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  17902220                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6149730                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              104066052                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 21507                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1015259                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4119258                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            31916                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           107817309                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             475022232                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        474932056                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             90176                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78731209                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 29086099                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             892462                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         797997                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12333143                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             20063520                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13521808                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1973034                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2429271                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   96511584                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2058662                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 123961862                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            189585                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        20013916                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     50091772                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         514148                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     151283915                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.819399                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.531663                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           106904579     70.66%     70.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13863783      9.16%     79.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7099546      4.69%     84.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5863279      3.88%     88.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12474907      8.25%     96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2771705      1.83%     98.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1719952      1.14%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              458027      0.30%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              128137      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       151283915                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   57031      0.64%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      3      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8373952     94.62%     95.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                418898      4.73%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58283800     47.02%     47.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                95201      0.08%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  19      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           13      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52766411     42.57%     89.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12450621     10.04%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              123961862                       # Type of FU issued
system.cpu.iq.rate                           0.262844                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8849884                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071392                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          408318037                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         118600535                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86285351                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23227                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12408                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10278                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              132435732                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12348                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           629942                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4347483                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7997                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29897                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1723272                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34108218                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        695964                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3262224                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                27920683                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                435052                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98794824                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            232558                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              20063520                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13521808                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1467094                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 114012                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3652                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29897                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         410015                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       293518                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               703533                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121755337                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52081116                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2206525                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        224578                       # number of nop insts executed
system.cpu.iew.exec_refs                     64400589                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11599904                       # Number of branches executed
system.cpu.iew.exec_stores                   12319473                       # Number of stores executed
system.cpu.iew.exec_rate                     0.258166                       # Inst execution rate
system.cpu.iew.wb_sent                      120729614                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      86295629                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47354389                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88420573                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.182978                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535558                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19868776                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1544514                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            612308                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    148104118                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.527303                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.512767                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    120332893     81.25%     81.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13565443      9.16%     90.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3964002      2.68%     93.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2135941      1.44%     94.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1954116      1.32%     95.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       973664      0.66%     96.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1592335      1.08%     97.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       730104      0.49%     98.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2855620      1.93%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    148104118                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60747617                       # Number of instructions committed
system.cpu.commit.committedOps               78095752                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27514573                       # Number of memory references committed
system.cpu.commit.loads                      15716037                       # Number of loads committed
system.cpu.commit.membars                      413105                       # Number of memory barriers committed
system.cpu.commit.branches                   10023091                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  69134185                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995980                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2855620                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    241297904                       # The number of ROB reads
system.cpu.rob.rob_writes                   199283253                       # The number of ROB writes
system.cpu.timesIdled                         1774711                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       320333327                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4575553300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60597236                       # Number of Instructions Simulated
system.cpu.committedOps                      77945371                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60597236                       # Number of Instructions Simulated
system.cpu.cpi                               7.782818                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.782818                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.128488                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.128488                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                551506178                       # number of integer regfile reads
system.cpu.int_regfile_writes                88407138                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8339                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2916                       # number of floating regfile writes
system.cpu.misc_regfile_reads               124072221                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912903                       # number of misc regfile writes
system.cpu.icache.replacements                 990875                       # number of replacements
system.cpu.icache.tagsinuse                510.405236                       # Cycle average of tags in use
system.cpu.icache.total_refs                 10787830                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 991387                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  10.881553                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6691567000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.405236                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996885                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996885                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     10787830                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        10787830                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      10787830                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         10787830                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     10787830                       # number of overall hits
system.cpu.icache.overall_hits::total        10787830                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1074333                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1074333                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1074333                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1074333                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1074333                       # number of overall misses
system.cpu.icache.overall_misses::total       1074333                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14125562486                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14125562486                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14125562486                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14125562486                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14125562486                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14125562486                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11862163                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11862163                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11862163                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11862163                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11862163                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11862163                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.090568                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.090568                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.090568                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.090568                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.090568                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.090568                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13148.216136                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13148.216136                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4400                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               296                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    14.864865                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        82890                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        82890                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        82890                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        82890                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        82890                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        82890                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991443                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       991443                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       991443                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       991443                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       991443                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       991443                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11470045988                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11470045988                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11470045988                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11470045988                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11470045988                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11470045988                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7052500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7052500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7052500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7052500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.083580                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.083580                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.083580                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.083580                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.083580                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.083580                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11569.042283                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11569.042283                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11569.042283                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11569.042283                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11569.042283                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11569.042283                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 645101                       # number of replacements
system.cpu.dcache.tagsinuse                511.994184                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21772820                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 645613                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.724259                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               35202000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.994184                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13909719                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13909719                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7289021                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7289021                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       285196                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       285196                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       285739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21198740                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21198740                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21198740                       # number of overall hits
system.cpu.dcache.overall_hits::total        21198740                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       730115                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        730115                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2961662                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2961662                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13591                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13591                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3691777                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3691777                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3691777                       # number of overall misses
system.cpu.dcache.overall_misses::total       3691777                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9540231500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9540231500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104360444235                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 104360444235                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    180814000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    180814000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       283000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       283000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 113900675735                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 113900675735                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 113900675735                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 113900675735                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14639834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14639834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10250683                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10250683                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       298787                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       298787                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       285758                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285758                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24890517                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24890517                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24890517                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24890517                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049872                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.049872                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.288923                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.288923                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045487                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045487                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000066                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000066                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.148321                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.148321                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.148321                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.148321                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13303.951144                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30852.534087                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30852.534087                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        29089                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        14501                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2531                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             252                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.493086                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    57.543651                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       609133                       # number of writebacks
system.cpu.dcache.writebacks::total            609133                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       342878                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       342878                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2712526                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2712526                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1365                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1365                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3055404                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3055404                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3055404                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3055404                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387237                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       387237                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249136                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249136                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12226                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12226                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       636373                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       636373                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       636373                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       636373                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4781839500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4781839500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8147970920                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8147970920                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    141479000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    141479000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       245000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       245000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12929810420                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  12929810420                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12929810420                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  12929810420                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  28006523855                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  28006523855                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026451                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026451                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024304                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024304                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.040919                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.040919                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000066                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025567                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025567                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025567                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025567                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 64428                       # number of replacements
system.cpu.l2cache.tagsinuse             51367.264734                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1930539                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                129823                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 14.870547                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          2488482557500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36879.772922                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    44.022997                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.000230                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   8192.461940                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6251.006645                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.562741                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000672                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.125007                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.095383                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.783802                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        83028                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12007                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       977743                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       388649                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1461427                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       609133                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       609133                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           53                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           53                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           16                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           16                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       113031                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       113031                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        83028                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12007                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       977743                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       501680                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1574458                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        83028                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12007                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       977743                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       501680                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1574458                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           55                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12377                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10733                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23166                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2933                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2933                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133200                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133200                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           55                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12377                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143933                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156366                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           55                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12377                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143933                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156366                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3825000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        49000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    666073500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    589040998                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1258988498                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       478000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       478000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6695831998                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6695831998                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3825000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        49000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    666073500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7284872996                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   7954820496                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3825000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        49000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    666073500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7284872996                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   7954820496                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        83083                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12008                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       990120                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       399382                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1484593                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       609133                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       609133                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2986                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2986                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           19                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246231                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246231                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        83083                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12008                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       990120                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       645613                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1730824                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        83083                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12008                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       990120                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       645613                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1730824                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000662                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000083                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012501                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026874                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015604                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982251                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982251                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.540955                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.540955                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000662                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000083                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012501                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.222940                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.090342                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000662                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000083                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012501                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.222940                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.090342                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69545.454545                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        49000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53815.423770                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54881.300475                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54346.391177                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   162.973065                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   162.973065                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50269.008994                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50269.008994                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69545.454545                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        49000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53815.423770                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50612.944884                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 50873.082998                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69545.454545                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        49000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53815.423770                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50612.944884                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 50873.082998                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59132                       # number of writebacks
system.cpu.l2cache.writebacks::total            59132                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           13                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           61                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           61                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           55                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12364                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10672                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23092                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2933                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2933                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133200                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133200                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           55                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12364                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143872                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156292                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           55                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12364                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143872                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156292                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3125110                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        37000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    508931159                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    450583388                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    962676657                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29345422                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29345422                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5043706030                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5043706030                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3125110                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        37000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    508931159                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5494289418                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6006382687                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3125110                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        37000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    508931159                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5494289418                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6006382687                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      4470659                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963401029                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166967871688                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  18112636815                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  18112636815                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      4470659                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185076037844                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185080508503                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000662                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000083                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012487                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026721                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015554                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982251                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982251                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.540955                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.540955                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000662                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000083                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012487                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222846                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.090299                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000662                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000083                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012487                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222846                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.090299                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        37000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41162.338968                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42221.082084                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41688.751819                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.258098                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.258098                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        37000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        37000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1068163777856                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    88030                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------