path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.827042                       # Number of seconds simulated
sim_ticks                                2827042159500                       # Number of ticks simulated
final_tick                               2827042159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  73670                       # Simulator instruction rate (inst/s)
host_op_rate                                    89358                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1840258315                       # Simulator tick rate (ticks/s)
host_mem_usage                                 564112                       # Number of bytes of host memory used
host_seconds                                  1536.22                       # Real time elapsed on the host
sim_insts                                   113173742                       # Number of instructions simulated
sim_ops                                     137273263                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1324048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9496932                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10823604                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1324048                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1324048                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8116352                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8133876                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              22933                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             148909                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                171883                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126818                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               131199                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            430                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               468351                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3359317                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3828597                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          468351                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             468351                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2870970                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6199                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2877168                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2870970                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           430                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              468351                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3365516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6705765                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        171884                       # Number of read requests accepted
system.physmem.writeReqs                       167423                       # Number of write requests accepted
system.physmem.readBursts                      171884                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     167423                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10992576                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10315392                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10823668                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10452212                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    6228                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4543                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10965                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10116                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11197                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11389                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13120                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10535                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11120                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11540                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10348                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11053                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10478                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9244                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10124                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10758                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10029                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9743                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10407                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9909                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10642                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10446                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9703                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10218                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10399                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10626                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10202                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10761                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9802                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9030                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9755                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10443                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9720                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9115                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2827041948500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                    2993                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  168336                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 163042                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    151765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15965                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      3221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10773                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64399                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      330.873212                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     190.977516                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     347.816153                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          23539     36.55%     36.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14785     22.96%     59.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6319      9.81%     69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3687      5.73%     75.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2636      4.09%     79.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1562      2.43%     81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1140      1.77%     83.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1107      1.72%     85.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9624     14.94%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64399                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6814                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.206340                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      540.339482                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6812     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6814                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6814                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.653948                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.805353                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       22.459775                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5702     83.68%     83.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              39      0.57%     84.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              26      0.38%     84.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             231      3.39%     88.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             131      1.92%     89.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              61      0.90%     90.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              35      0.51%     91.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              27      0.40%     91.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             123      1.81%     93.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              13      0.19%     93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              19      0.28%     94.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              11      0.16%     94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              31      0.45%     94.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              13      0.19%     94.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              13      0.19%     95.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              26      0.38%     95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              61      0.90%     96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              10      0.15%     96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               9      0.13%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              11      0.16%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              89      1.31%     98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.06%     98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             7      0.10%     98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            18      0.26%     98.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             4      0.06%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             5      0.07%     98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.06%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            26      0.38%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.06%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.06%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             5      0.07%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            11      0.16%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151            11      0.16%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.04%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.04%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.04%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.04%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             3      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             3      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6814                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2084525750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5305007000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    858795000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12136.34                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30886.34                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.89                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.65                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.83                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.70                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.50                       # Average write queue length when enqueuing
system.physmem.readRowHits                     141721                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    126816                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.67                       # Row buffer hit rate for writes
system.physmem.avgGap                      8331811.45                       # Average gap between requests
system.physmem.pageHitRate                      80.65                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2694668588500                       # Time in different power states
system.physmem.memoryStateTime::REF       94401060000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       37972497000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 254499840                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 232356600                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 138864000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 126781875                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                701859600                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                637852800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               533628000                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               510805440                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          184648473360                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          184648473360                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           80377758270                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           79142156730                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1625717004000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1626800865000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1892372087070                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1892099291805                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.382923                       # Core power per rank (mW)
system.physmem.averagePower::1             669.286428                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          128                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            45                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               45                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           45                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           45                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              45                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                46933448                       # Number of BP lookups
system.cpu.branchPred.condPredicted          24039449                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1232882                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             29542848                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                21360620                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.303862                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                11754095                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              33720                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits             24594187                       # DTB read hits
system.cpu.checker.dtb.read_misses               8246                       # DTB read misses
system.cpu.checker.dtb.write_hits            19641862                       # DTB write hits
system.cpu.checker.dtb.write_misses              1441                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries             4296                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults           1766                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses         24602433                       # DTB read accesses
system.cpu.checker.dtb.write_accesses        19643303                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                  44236049                       # DTB hits
system.cpu.checker.dtb.misses                    9687                       # DTB misses
system.cpu.checker.dtb.accesses              44245736                       # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.itb.inst_hits            115876249                       # ITB inst hits
system.cpu.checker.itb.inst_misses               4826                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                  128                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries             2977                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses        115881075                       # ITB inst accesses
system.cpu.checker.itb.hits                 115876249                       # DTB hits
system.cpu.checker.itb.misses                    4826                       # DTB misses
system.cpu.checker.itb.accesses             115881075                       # DTB accesses
system.cpu.checker.numCycles                139127814                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     25465003                       # DTB read hits
system.cpu.dtb.read_misses                      60438                       # DTB read misses
system.cpu.dtb.write_hits                    19916425                       # DTB write hits
system.cpu.dtb.write_misses                      9382                       # DTB write misses
system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4324                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       344                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   2309                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 25525441                       # DTB read accesses
system.cpu.dtb.write_accesses                19925807                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          45381428                       # DTB hits
system.cpu.dtb.misses                           69820                       # DTB misses
system.cpu.dtb.accesses                      45451248                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                     66294026                       # ITB inst hits
system.cpu.itb.inst_misses                      11939                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                          128                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     3096                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2177                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 66305965                       # ITB inst accesses
system.cpu.itb.hits                          66294026                       # DTB hits
system.cpu.itb.misses                           11939                       # DTB misses
system.cpu.itb.accesses                      66305965                       # DTB accesses
system.cpu.numCycles                        260580731                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          104873538                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      184739295                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    46933448                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           33114715                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     145635789                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6158762                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     168952                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 8750                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        338958                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       503648                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  66294321                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1128854                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4994                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          254609122                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.884999                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.237560                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                155317216     61.00%     61.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 29235163     11.48%     72.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 14076452      5.53%     78.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 55980291     21.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            254609122                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.180111                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.708952                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 78085586                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             105431733                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  64660886                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3829260                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                2601657                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3422216                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                485978                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              157447803                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3691485                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                2601657                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 83925210                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                10033565                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       74541150                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  62655394                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              20852146                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              146807646                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                950357                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents                437123                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  62766                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                  16447                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               18089237                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           150492315                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             678770164                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        164434086                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             10967                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             141835122                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  8657190                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2845976                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2649716                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13845319                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26411369                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21300781                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1686386                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2189128                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  143541895                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2120957                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 143337283                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            269192                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6251828                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     14653372                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         125306                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     254609122                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.562970                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.882443                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           166344309     65.33%     65.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            45117660     17.72%     83.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            32035421     12.58%     95.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            10298180      4.04%     99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4              813519      0.32%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       254609122                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 7370311     32.63%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     32      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                5632420     24.93%     57.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               9586874     42.44%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              96009315     66.98%     66.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               113982      0.08%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           8594      0.01%     67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             26194290     18.27%     85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21008765     14.66%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              143337283                       # Type of FU issued
system.cpu.iq.rate                           0.550069                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    22589637                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157598                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          564106761                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         151919680                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    140223084                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               35756                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13217                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        11431                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              165901147                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   23436                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           324147                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1490308                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses          533                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18251                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       701176                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        88081                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          6304                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                2601657                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  950737                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                291154                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           145863821                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26411369                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21300781                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1096076                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  17895                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                256263                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18251                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         317548                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       471732                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               789280                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             142394540                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25793108                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            873030                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        200969                       # number of nop insts executed
system.cpu.iew.exec_refs                     46672402                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 26533167                       # Number of branches executed
system.cpu.iew.exec_stores                   20879294                       # Number of stores executed
system.cpu.iew.exec_rate                     0.546451                       # Inst execution rate
system.cpu.iew.wb_sent                      142007306                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     140234515                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  63283849                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95860591                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.538161                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.660165                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7591533                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1995651                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            755158                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    251674404                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.546055                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.146686                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    178222235     70.81%     70.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     43294364     17.20%     88.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     15476639      6.15%     94.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4357303      1.73%     95.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      6369018      2.53%     98.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1679088      0.67%     99.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       777340      0.31%     99.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       414271      0.16%     99.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1084146      0.43%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    251674404                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            113328647                       # Number of instructions committed
system.cpu.commit.committedOps              137428168                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       45520666                       # Number of memory references committed
system.cpu.commit.loads                      24921061                       # Number of loads committed
system.cpu.commit.membars                      814701                       # Number of memory barriers committed
system.cpu.commit.branches                   26049415                       # Number of branches committed
system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 120247607                       # Number of committed integer instructions.
system.cpu.commit.function_calls              4892692                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         91785919     66.79%     66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          112990      0.08%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc         8593      0.01%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        24921061     18.13%     85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20599605     14.99%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         137428168                       # Class of committed instruction
system.cpu.commit.bw_lim_events               1084146                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    373381031                       # The number of ROB reads
system.cpu.rob.rob_writes                   292971684                       # The number of ROB writes
system.cpu.timesIdled                          892930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         5971609                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   5393503589                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   113173742                       # Number of Instructions Simulated
system.cpu.committedOps                     137273263                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               2.302484                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.302484                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.434314                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.434314                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                155831391                       # number of integer regfile reads
system.cpu.int_regfile_writes                88636025                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      9607                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 503020698                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 53185327                       # number of cc regfile writes
system.cpu.misc_regfile_reads               444130548                       # number of misc regfile reads
system.cpu.misc_regfile_writes                1521619                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            837995                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.958491                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40159583                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            838507                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             47.894154                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         244924250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.958491                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999919                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         179379502                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        179379502                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23322864                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23322864                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     15584894                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       15584894                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       346636                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        346636                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       442009                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       442009                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460310                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460310                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      38907758                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         38907758                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     39254394                       # number of overall hits
system.cpu.dcache.overall_hits::total        39254394                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       700618                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        700618                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3574058                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3574058                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       177109                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       177109                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        26740                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        26740                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      4274676                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4274676                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4451785                       # number of overall misses
system.cpu.dcache.overall_misses::total       4451785                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9939142148                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9939142148                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 135148977049                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    356483749                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    356483749                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       189500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       189500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 145088119197                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 145088119197                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 145088119197                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 145088119197                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     24023482                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     24023482                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19158952                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19158952                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       523745                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       523745                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468749                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       468749                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460315                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460315                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     43182434                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     43182434                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43706179                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43706179                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029164                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.029164                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186548                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.186548                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338159                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.338159                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.098991                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.098991                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.101857                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.101857                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        37900                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        37900                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33941.313727                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32590.998711                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       505021                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              6926                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.916691                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       695574                       # number of writebacks
system.cpu.dcache.writebacks::total            695574                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286297                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       286297                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274736                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3274736                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18417                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        18417                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3561033                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3561033                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3561033                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3561033                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414321                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       414321                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299322                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       299322                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119334                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       119334                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8323                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8323                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       713643                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       713643                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       832977                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       832977                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5358688665                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5358688665                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11888843709                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11888843709                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1476460251                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1476460251                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110246000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110246000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       179500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       179500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17247532374                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  17247532374                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18723992625                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  18723992625                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792718250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792718250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440457453                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440457453                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233175703                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233175703                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017247                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017247                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017756                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017756                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016526                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019059                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019059                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        35900                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        35900                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1894210                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.373832                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            64309690                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1894722                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             33.941491                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       13186180250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.373832                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998777                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998777                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          68186062                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         68186062                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     64309690                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        64309690                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      64309690                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         64309690                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     64309690                       # number of overall hits
system.cpu.icache.overall_hits::total        64309690                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1981630                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1981630                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1981630                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1981630                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1981630                       # number of overall misses
system.cpu.icache.overall_misses::total       1981630                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  26770075875                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  26770075875                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  26770075875                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  26770075875                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  26770075875                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  26770075875                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     66291320                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     66291320                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     66291320                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     66291320                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     66291320                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     66291320                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029893                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.029893                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.029893                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.029893                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.029893                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.029893                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13509.119197                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13509.119197                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1592                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               104                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    15.307692                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86886                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        86886                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        86886                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        86886                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        86886                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        86886                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894744                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1894744                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1894744                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1894744                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1894744                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1894744                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22166113097                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  22166113097                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22166113097                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  22166113097                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22166113097                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  22166113097                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    202549500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    202549500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    202549500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    202549500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028582                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.028582                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.028582                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.737717                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            98615                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65077.693225                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3021592                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           163828                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            18.443685                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218373                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798544                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5192.626837                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.756260                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000156                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157315                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.079233                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.993007                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2969                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7003                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55048                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         28442992                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        28442992                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53902                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11707                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1874744                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       528230                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2468583                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       695574                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       695574                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           36                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           36                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       159750                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       159750                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        53902                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        11707                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1874744                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       687980                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2628333                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        53902                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        11707                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1874744                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       687980                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2628333                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           19                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        19968                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        13616                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        33610                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2734                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2734                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       136934                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       136934                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           19                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        19968                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       150550                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        170544                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           19                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        19968                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       150550                       # number of overall misses
system.cpu.l2cache.overall_misses::total       170544                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1472750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       536250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1503894000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1090000000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2595903000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       581975                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       581975                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       144500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9927756441                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9927756441                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1472750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       536250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1503894000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11017756441                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  12523659441                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1472750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       536250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1503894000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11017756441                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  12523659441                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53921                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11714                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1894712                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       541846                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2502193                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       695574                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       695574                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2770                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2770                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296684                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296684                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53921                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        11714                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1894712                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       838530                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2798877                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53921                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        11714                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1894712                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       838530                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2798877                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000352                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000598                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010539                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025129                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.013432                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.987004                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.987004                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.461548                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.461548                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000352                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000598                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010539                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.179540                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.060933                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000352                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000598                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010539                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.179540                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.060933                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77513.157895                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75315.204327                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80052.878966                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77236.030943                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   212.865764                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   212.865764                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72500.302635                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72500.302635                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77513.157895                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75315.204327                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73183.370581                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73433.597435                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77513.157895                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75315.204327                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73183.370581                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73433.597435                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        90628                       # number of writebacks
system.cpu.l2cache.writebacks::total            90628                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          137                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          137                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19943                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        13504                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        33473                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2734                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2734                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       136934                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       136934                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           19                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        19943                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       150438                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       170407                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           19                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        19943                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       150438                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       170407                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       451250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1251787750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    914145000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2167621250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27559234                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27559234                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8214311559                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8214311559                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       451250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1251787750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9128456559                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10381932809                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       451250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1251787750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9128456559                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10381932809                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157877000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387474750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545351750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107339500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107339500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157877000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494814250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652691250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024922                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013377                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987004                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987004                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461548                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461548                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060884                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.060884                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        2565344                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2565278                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27608                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27608                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       695574                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2770                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2775                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296684                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296684                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795456                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495832                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31236                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128794                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6451318                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121309456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98375777                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215684                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          219947773                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       65392                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3562462                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        9.010230                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.100625                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::9            3526018     98.98%     98.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::10             36444      1.02%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3562462                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2503396529                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2849706150                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1334755109                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      19527240                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      74897454                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72888                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72888                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178438                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320992                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2320992                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480189                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347066130                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36776516                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36410                       # number of replacements
system.iocache.tags.tagsinuse                1.000725                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         251942535000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.000725                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062545                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062545                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
system.iocache.tags.data_accesses              327996                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          220                       # number of demand (read+write) misses
system.iocache.demand_misses::total               220                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          220                       # number of overall misses
system.iocache.overall_misses::total              220                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     26411377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     26411377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9622478237                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9622478237                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     26411377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     26411377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     26411377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     26411377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          220                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             220                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          220                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            220                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120051.713636                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120051.713636                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120051.713636                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         56749                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7275                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.800550                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          220                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          220                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          220                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          220                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          220                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          220                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     14970377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     14970377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     14970377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     14970377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     14970377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     14970377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               67832                       # Transaction distribution
system.membus.trans_dist::ReadResp              67831                       # Transaction distribution
system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
system.membus.trans_dist::Writeback            126818                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4543                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4545                       # Transaction distribution
system.membus.trans_dist::ReadExReq            135125                       # Transaction distribution
system.membus.trans_dist::ReadExResp           135125                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452492                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108873                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108873                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 669001                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16640360                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16803825                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21439281                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              484                       # Total snoops (count)
system.membus.snoop_fanout::samples            336405                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  336405    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              336405                       # Request fanout histogram
system.membus.reqLayer0.occupancy            94190000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               10500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1683660499                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1677935457                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38220484                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3039                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------