path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.525132                       # Number of seconds simulated
sim_ticks                                2525131633500                       # Number of ticks simulated
final_tick                               2525131633500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  63748                       # Simulator instruction rate (inst/s)
host_op_rate                                    82026                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2669254242                       # Simulator tick rate (ticks/s)
host_mem_usage                                 403420                       # Number of bytes of host memory used
host_seconds                                   946.01                       # Real time elapsed on the host
sim_insts                                    60305678                       # Number of instructions simulated
sim_ops                                      77596684                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            796928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9094736                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129432144                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       796928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          796928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3784384                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6800456                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           42                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12452                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142139                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15096843                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59131                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813149                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47339181                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1064                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               315599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3601688                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51257583                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          315599                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315599                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1498688                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1194422                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2693110                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1498688                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47339181                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1064                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              315599                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4796110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53950692                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15096843                       # Number of read requests accepted
system.physmem.writeReqs                       813149                       # Number of write requests accepted
system.physmem.readBursts                    15096843                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     813149                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                963738752                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2459200                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6902144                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 129432144                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6800456                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    38425                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  705284                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4682                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              943580                       # Per bank write bursts
system.physmem.perBankRdBursts::1              943152                       # Per bank write bursts
system.physmem.perBankRdBursts::2              939288                       # Per bank write bursts
system.physmem.perBankRdBursts::3              939310                       # Per bank write bursts
system.physmem.perBankRdBursts::4              943113                       # Per bank write bursts
system.physmem.perBankRdBursts::5              943139                       # Per bank write bursts
system.physmem.perBankRdBursts::6              939134                       # Per bank write bursts
system.physmem.perBankRdBursts::7              938551                       # Per bank write bursts
system.physmem.perBankRdBursts::8              944000                       # Per bank write bursts
system.physmem.perBankRdBursts::9              943392                       # Per bank write bursts
system.physmem.perBankRdBursts::10             938425                       # Per bank write bursts
system.physmem.perBankRdBursts::11             937973                       # Per bank write bursts
system.physmem.perBankRdBursts::12             943928                       # Per bank write bursts
system.physmem.perBankRdBursts::13             943534                       # Per bank write bursts
system.physmem.perBankRdBursts::14             939230                       # Per bank write bursts
system.physmem.perBankRdBursts::15             938669                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6703                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6464                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6595                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6634                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6559                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6792                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6793                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6730                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7130                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6877                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6539                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6181                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7151                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6766                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7035                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6897                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2525130505500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      36                       # Read request sizes (log2)
system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154599                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  59131                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1173486                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1117689                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1073548                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3627714                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2609756                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2597217                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2603662                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     53378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     57682                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     21065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    20906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    20772                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20252                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20160                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4887                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        86134                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11268.950798                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1000.903149                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16775.480046                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          23607     27.41%     27.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14081     16.35%     43.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         2628      3.05%     46.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2075      2.41%     49.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1317      1.53%     50.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1250      1.45%     52.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          847      0.98%     53.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519          989      1.15%     54.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          557      0.65%     54.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          603      0.70%     55.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          514      0.60%     56.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          583      0.68%     56.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          284      0.33%     57.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          264      0.31%     57.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          155      0.18%     57.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          634      0.74%     58.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095           90      0.10%     58.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          143      0.17%     58.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223           77      0.09%     58.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          121      0.14%     59.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351           52      0.06%     59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415          516      0.60%     59.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479           33      0.04%     59.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          269      0.31%     60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           22      0.03%     60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671           94      0.11%     60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           18      0.02%     60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799          142      0.16%     60.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           22      0.03%     60.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           57      0.07%     60.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           13      0.02%     60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          390      0.45%     60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119            6      0.01%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           32      0.04%     60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           13      0.02%     60.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311          120      0.14%     61.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375            5      0.01%     61.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           22      0.03%     61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503            8      0.01%     61.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567          107      0.12%     61.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631            7      0.01%     61.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           24      0.03%     61.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759           11      0.01%     61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823           86      0.10%     61.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887            7      0.01%     61.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           27      0.03%     61.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015            4      0.00%     61.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          358      0.42%     61.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143            7      0.01%     61.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           18      0.02%     61.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            8      0.01%     61.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335          154      0.18%     62.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399            9      0.01%     62.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           15      0.02%     62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527            8      0.01%     62.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591           31      0.04%     62.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655            4      0.00%     62.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           11      0.01%     62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783            7      0.01%     62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847           39      0.05%     62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911            9      0.01%     62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           15      0.02%     62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039           10      0.01%     62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          368      0.43%     62.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            4      0.00%     62.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           15      0.02%     62.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295            8      0.01%     62.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359          165      0.19%     62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423           14      0.02%     62.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           12      0.01%     62.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551            8      0.01%     62.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615           92      0.11%     63.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679            3      0.00%     63.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743            8      0.01%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807            2      0.00%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871           95      0.11%     63.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            2      0.00%     63.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           16      0.02%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063            5      0.01%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          379      0.44%     63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            5      0.01%     63.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           10      0.01%     63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            5      0.01%     63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383           88      0.10%     63.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447           11      0.01%     63.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511           21      0.02%     63.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575            3      0.00%     63.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639          146      0.17%     63.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            2      0.00%     63.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767            8      0.01%     64.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            2      0.00%     64.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895           64      0.07%     64.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            1      0.00%     64.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023           13      0.02%     64.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087           11      0.01%     64.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          283      0.33%     64.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            1      0.00%     64.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279            8      0.01%     64.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343            2      0.00%     64.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407           88      0.10%     64.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471            4      0.00%     64.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535           11      0.01%     64.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            6      0.01%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663          153      0.18%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727            1      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791           14      0.02%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855            7      0.01%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           78      0.09%     64.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983            2      0.00%     64.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047            9      0.01%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111            4      0.00%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          368      0.43%     65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239            2      0.00%     65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303           11      0.01%     65.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367           12      0.01%     65.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431          136      0.16%     65.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495            5      0.01%     65.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559            9      0.01%     65.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            1      0.00%     65.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687           88      0.10%     65.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815            9      0.01%     65.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7879            5      0.01%     65.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           84      0.10%     65.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007            1      0.00%     65.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071           11      0.01%     65.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8135            1      0.00%     65.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          389      0.45%     66.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8263            1      0.00%     66.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8327            2      0.00%     66.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           79      0.09%     66.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8647            1      0.00%     66.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711           78      0.09%     66.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8839            1      0.00%     66.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8903            1      0.00%     66.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967          130      0.15%     66.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095            1      0.00%     66.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          355      0.41%     66.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9351            2      0.00%     66.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           73      0.08%     67.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9543            1      0.00%     67.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9607            4      0.00%     67.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9671            1      0.00%     67.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735          140      0.16%     67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9799            2      0.00%     67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927            1      0.00%     67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991           79      0.09%     67.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119            4      0.00%     67.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          272      0.32%     67.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10439            1      0.00%     67.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503           15      0.02%     67.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10567            1      0.00%     67.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10631            1      0.00%     67.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759          132      0.15%     67.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10951            3      0.00%     67.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015           75      0.09%     67.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          373      0.43%     68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11399            1      0.00%     68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527           86      0.10%     68.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591            2      0.00%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11655            1      0.00%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11719            2      0.00%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783           77      0.09%     68.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911            2      0.00%     68.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11975            1      0.00%     68.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039          144      0.17%     68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12103            1      0.00%     68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167            4      0.00%     68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          340      0.39%     69.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359            1      0.00%     69.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423            2      0.00%     69.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12487            1      0.00%     69.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551           26      0.03%     69.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807           18      0.02%     69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12871            1      0.00%     69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12935            1      0.00%     69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999            2      0.00%     69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063          146      0.17%     69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13127            1      0.00%     69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191            2      0.00%     69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          339      0.39%     69.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575           74      0.09%     69.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831           78      0.09%     69.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13895            1      0.00%     69.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959            1      0.00%     69.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087           87      0.10%     70.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14151            2      0.00%     70.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215            4      0.00%     70.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          340      0.39%     70.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599           79      0.09%     70.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14727            4      0.00%     70.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           86      0.10%     70.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14919            2      0.00%     70.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           13      0.02%     70.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            2      0.00%     70.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15303            1      0.00%     70.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          405      0.47%     71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           83      0.10%     71.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15687            1      0.00%     71.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879           89      0.10%     71.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16071            1      0.00%     71.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135           86      0.10%     71.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263           12      0.01%     71.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          642      0.75%     72.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647           86      0.10%     72.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16711            2      0.00%     72.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16775            1      0.00%     72.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903           84      0.10%     72.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17095            1      0.00%     72.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           92      0.11%     72.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287            4      0.00%     72.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17351            1      0.00%     72.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          410      0.48%     72.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479            2      0.00%     72.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17543            3      0.00%     72.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           15      0.02%     72.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17735            1      0.00%     72.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799            5      0.01%     72.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17863            1      0.00%     72.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           86      0.10%     73.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17984-17991            1      0.00%     73.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055            1      0.00%     73.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18112-18119            2      0.00%     73.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183           83      0.10%     73.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311            3      0.00%     73.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          331      0.38%     73.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503            1      0.00%     73.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18567            1      0.00%     73.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695           89      0.10%     73.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18880-18887            2      0.00%     73.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951           83      0.10%     73.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19136-19143            1      0.00%     73.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207           74      0.09%     73.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            3      0.00%     73.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          326      0.38%     74.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19520-19527            1      0.00%     74.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19584-19591            3      0.00%     74.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19648-19655            1      0.00%     74.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719          138      0.16%     74.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19840-19847            1      0.00%     74.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975           15      0.02%     74.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231           23      0.03%     74.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20288-20295            1      0.00%     74.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359            3      0.00%     74.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          336      0.39%     74.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615            1      0.00%     74.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20672-20679            2      0.00%     74.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743          143      0.17%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20864-20871            3      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999           73      0.08%     75.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255           89      0.10%     75.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21319            1      0.00%     75.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383            3      0.00%     75.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447            1      0.00%     75.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          367      0.43%     75.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21568-21575            1      0.00%     75.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21632-21639            1      0.00%     75.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767           76      0.09%     75.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21824-21831            1      0.00%     75.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21895            5      0.01%     75.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023          129      0.15%     75.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151            1      0.00%     75.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279           14      0.02%     75.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22336-22343            1      0.00%     75.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407            3      0.00%     75.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22464-22471            2      0.00%     75.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          268      0.31%     76.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22720-22727            2      0.00%     76.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791           78      0.09%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22848-22855            1      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919            1      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22976-22983            2      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047          143      0.17%     76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23104-23111            1      0.00%     76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23175            1      0.00%     76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           77      0.09%     76.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23360-23367            3      0.00%     76.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431            2      0.00%     76.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          350      0.41%     76.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23687            1      0.00%     76.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815          126      0.15%     77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23936-23943            1      0.00%     77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24000-24007            2      0.00%     77.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071           74      0.09%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24192-24199            2      0.00%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24256-24263            1      0.00%     77.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           82      0.10%     77.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455            3      0.00%     77.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          270      0.31%     77.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839           79      0.09%     77.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25024-25031            1      0.00%     77.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095           77      0.09%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25216-25223            2      0.00%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25280-25287            1      0.00%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351          133      0.15%     77.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479            2      0.00%     77.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          355      0.41%     78.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           72      0.08%     78.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25984-25991            2      0.00%     78.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119          138      0.16%     78.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26176-26183            1      0.00%     78.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26247            1      0.00%     78.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26311            2      0.00%     78.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375           79      0.09%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503            2      0.00%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          269      0.31%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26688-26695            1      0.00%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26752-26759            1      0.00%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823            1      0.00%     79.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887           14      0.02%     79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27008-27015            4      0.00%     79.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27072-27079            1      0.00%     79.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143          130      0.15%     79.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27200-27207            1      0.00%     79.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399           74      0.09%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591            1      0.00%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          367      0.43%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847            1      0.00%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911           85      0.10%     79.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27968-27975            2      0.00%     79.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28032-28039            2      0.00%     79.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28096-28103            1      0.00%     79.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167           75      0.09%     79.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28288-28295            2      0.00%     79.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28352-28359            2      0.00%     79.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423          143      0.17%     80.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28480-28487            2      0.00%     80.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551            4      0.00%     80.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28615            1      0.00%     80.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          337      0.39%     80.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28743            1      0.00%     80.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28864-28871            2      0.00%     80.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935           26      0.03%     80.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28992-28999            1      0.00%     80.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191           17      0.02%     80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29248-29255            2      0.00%     80.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447          139      0.16%     80.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511            3      0.00%     80.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            4      0.00%     80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29632-29639            1      0.00%     80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          329      0.38%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831            2      0.00%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959           70      0.08%     81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215           79      0.09%     81.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471           92      0.11%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            4      0.00%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30656-30663            1      0.00%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          327      0.38%     81.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855            4      0.00%     81.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30912-30919            2      0.00%     81.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983           84      0.10%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           89      0.10%     82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367            1      0.00%     82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31424-31431            1      0.00%     82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           19      0.02%     82.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31552-31559            2      0.00%     82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623            5      0.01%     82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31680-31687            1      0.00%     82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          406      0.47%     82.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31872-31879            1      0.00%     82.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           83      0.10%     82.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32064-32071            1      0.00%     82.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135            2      0.00%     82.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263           82      0.10%     82.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32320-32327            1      0.00%     82.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32448-32455            2      0.00%     82.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519           93      0.11%     82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32576-32583            1      0.00%     82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          645      0.75%     83.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32832-32839            2      0.00%     83.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903            1      0.00%     83.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031           83      0.10%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33088-33095            1      0.00%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33216-33223            2      0.00%     83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287           82      0.10%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415            4      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33472-33479            1      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           95      0.11%     83.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          411      0.48%     84.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33984-33991            1      0.00%     84.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           13      0.02%     84.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34119            1      0.00%     84.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           83      0.10%     84.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439            2      0.00%     84.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567           86      0.10%     84.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34688-34695            1      0.00%     84.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          328      0.38%     84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079           86      0.10%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35136-35143            1      0.00%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35200-35207            1      0.00%     85.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335           76      0.09%     85.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463            3      0.00%     85.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591           72      0.08%     85.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35712-35719            1      0.00%     85.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          328      0.38%     85.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103          138      0.16%     85.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36224-36231            1      0.00%     85.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359           15      0.02%     85.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36487            3      0.00%     85.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615           25      0.03%     85.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          337      0.39%     86.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36992-36999            2      0.00%     86.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127          141      0.16%     86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37184-37191            1      0.00%     86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383           73      0.08%     86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511            3      0.00%     86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37568-37575            1      0.00%     86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639           82      0.10%     86.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          365      0.42%     86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37959            1      0.00%     86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38016-38023            2      0.00%     86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151           75      0.09%     87.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38336-38343            1      0.00%     87.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407          129      0.15%     87.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38464-38471            1      0.00%     87.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535            2      0.00%     87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663           14      0.02%     87.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38720-38727            1      0.00%     87.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          267      0.31%     87.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38976-38983            1      0.00%     87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39104-39111            1      0.00%     87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175           77      0.09%     87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39232-39239            1      0.00%     87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39296-39303            1      0.00%     87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431          140      0.16%     87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39552-39559            2      0.00%     87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           70      0.08%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39808-39815            1      0.00%     87.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          351      0.41%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071            1      0.00%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199          129      0.15%     88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455           76      0.09%     88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583            2      0.00%     88.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40640-40647            1      0.00%     88.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           80      0.09%     88.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40832-40839            2      0.00%     88.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          269      0.31%     88.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41152-41159            2      0.00%     88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223           77      0.09%     89.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41408-41415            1      0.00%     89.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479           75      0.09%     89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607            2      0.00%     89.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735          131      0.15%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41856-41863            3      0.00%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          349      0.41%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42112-42119            2      0.00%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           70      0.08%     89.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503          140      0.16%     89.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42624-42631            2      0.00%     89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42695            1      0.00%     89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759           77      0.09%     90.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42816-42823            1      0.00%     90.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          267      0.31%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43136-43143            3      0.00%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43200-43207            1      0.00%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271           14      0.02%     90.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43328-43335            1      0.00%     90.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527          127      0.15%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43648-43655            1      0.00%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783           80      0.09%     90.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43840-43847            2      0.00%     90.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43904-43911            2      0.00%     90.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          364      0.42%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103            1      0.00%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44160-44167            1      0.00%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44224-44231            1      0.00%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295           83      0.10%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44352-44359            1      0.00%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423            1      0.00%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551           73      0.08%     91.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807          144      0.17%     91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44864-44871            2      0.00%     91.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          337      0.39%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191            1      0.00%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45248-45255            1      0.00%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319           24      0.03%     91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45440-45447            3      0.00%     91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575           16      0.02%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703            3      0.00%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831          144      0.17%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45888-45895            2      0.00%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          327      0.38%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46144-46151            1      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343           69      0.08%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599           79      0.09%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855           89      0.10%     92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46912-46919            1      0.00%     92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983            1      0.00%     92.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          334      0.39%     93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47232-47239            2      0.00%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303            3      0.00%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367           78      0.09%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           88      0.10%     93.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751            4      0.00%     93.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           24      0.03%     93.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943            1      0.00%     93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007            1      0.00%     93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          398      0.46%     93.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391           83      0.10%     93.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647           77      0.09%     93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775           72      0.08%     94.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903           83      0.10%     94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            1      0.00%     94.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            3      0.00%     94.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            1      0.00%     94.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5012      5.82%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49216-49223            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49600-49607            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49664-49671            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49728-49735            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49856-49863            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49920-49927            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50368-50375            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50496-50503            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50560-50567            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50695            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50944-50951            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51008-51015            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51136-51143            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51207            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51264-51271            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51520-51527            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51840-51847            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          86134                       # Bytes accessed per row activation
system.physmem.totQLat                   365453646000                       # Total ticks spent queuing
system.physmem.totMemAccLat              458164497250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  75292090000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 17418761250                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24269.06                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1156.75                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30425.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         381.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.26                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.83                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14986798                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93332                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  86.53                       # Row buffer hit rate for writes
system.physmem.avgGap                       158713.50                       # Average gap between requests
system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               1.72                       # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54900302                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16149434                       # Transaction distribution
system.membus.trans_dist::ReadResp           16149434                       # Transaction distribution
system.membus.trans_dist::WriteReq             763332                       # Transaction distribution
system.membus.trans_dist::WriteResp            763332                       # Transaction distribution
system.membus.trans_dist::Writeback             59131                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4679                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4682                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131448                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131448                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885801                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272507                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34156923                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390301                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16694936                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19092825                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           138630489                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              138630489                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1486873500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3694000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17363465500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4733669250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33737503451                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      48285786                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16125522                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16125522                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8157                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8157                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          516                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29884416                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     29884416                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32267358                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1032                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390301                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            121927965                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               121927965                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3973000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               516000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               518000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         14942208000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374785000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         40921719549                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                14384927                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11469310                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            704177                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9471049                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7661571                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             80.894640                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1398227                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72610                       # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits             14986834                       # DTB read hits
system.cpu.checker.dtb.read_misses               7307                       # DTB read misses
system.cpu.checker.dtb.write_hits            11227416                       # DTB write hits
system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries             6418                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults            179                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses         14994141                       # DTB read accesses
system.cpu.checker.dtb.write_accesses        11229607                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                  26214250                       # DTB hits
system.cpu.checker.dtb.misses                    9498                       # DTB misses
system.cpu.checker.dtb.accesses              26223748                       # DTB accesses
system.cpu.checker.itb.inst_hits             61479661                       # ITB inst hits
system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries             4683                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses         61484134                       # ITB inst accesses
system.cpu.checker.itb.hits                  61479661                       # DTB hits
system.cpu.checker.itb.misses                    4473                       # DTB misses
system.cpu.checker.itb.accesses              61484134                       # DTB accesses
system.cpu.checker.numCycles                 77882476                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51182106                       # DTB read hits
system.cpu.dtb.read_misses                      64421                       # DTB read misses
system.cpu.dtb.write_hits                    11699698                       # DTB write hits
system.cpu.dtb.write_misses                     15824                       # DTB write misses
system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     6560                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2374                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    404                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1314                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51246527                       # DTB read accesses
system.cpu.dtb.write_accesses                11715522                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          62881804                       # DTB hits
system.cpu.dtb.misses                           80245                       # DTB misses
system.cpu.dtb.accesses                      62962049                       # DTB accesses
system.cpu.itb.inst_hits                     11522583                       # ITB inst hits
system.cpu.itb.inst_misses                      11276                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     4956                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      3012                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 11533859                       # ITB inst accesses
system.cpu.itb.hits                          11522583                       # DTB hits
system.cpu.itb.misses                           11276                       # DTB misses
system.cpu.itb.accesses                      11533859                       # DTB accesses
system.cpu.numCycles                        474898657                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           29752889                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       90273347                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14384927                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9059798                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      20146705                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4653497                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     122274                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               96010555                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2615                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         88482                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      2690288                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          446                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11519088                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                708911                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5337                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          152021113                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.740504                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.094585                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131890125     86.76%     86.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1304050      0.86%     87.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1713045      1.13%     88.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2295968      1.51%     90.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2102742      1.38%     91.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1107769      0.73%     92.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2555355      1.68%     94.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   744146      0.49%     94.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8307913      5.46%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            152021113                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.030291                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.190090                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31508438                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              98138099                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18373215                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                963804                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3037557                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1957081                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171807                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              107274658                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                567663                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3037557                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33258738                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                39476292                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       52673596                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  17529662                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6045268                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102285915                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20597                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1004806                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4066044                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              644                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           106018919                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             466959682                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        432092489                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             10446                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78387358                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27631560                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             830464                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         736820                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12181979                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             19715902                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13307123                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1978281                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2470778                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   95109477                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1982753                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 122906700                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            167286                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        18927569                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     47237054                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         500451                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     152021113                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.808484                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.527863                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           108300469     71.24%     71.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13447891      8.85%     80.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6945073      4.57%     84.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5857007      3.85%     88.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12370739      8.14%     96.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2808869      1.85%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1695394      1.12%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              467391      0.31%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              128280      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       152021113                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   61937      0.70%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      6      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8370529     94.64%     95.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                412377      4.66%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.30%      0.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              57620183     46.88%     47.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93128      0.08%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  24      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  6      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              20      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2114      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           20      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52507579     42.72%     89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12319960     10.02%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              122906700                       # Type of FU issued
system.cpu.iq.rate                           0.258806                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8844849                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071964                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          406902990                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         116036304                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     85470220                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23531                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12536                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10316                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              131375312                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12571                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           623425                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4061911                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6363                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30197                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1575391                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107753                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        681273                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3037557                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                30701555                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                434229                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            97313991                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            205819                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              19715902                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13307123                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1410230                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3566                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30197                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         350181                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       268988                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               619169                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             120829627                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              51869148                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2077073                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221761                       # number of nop insts executed
system.cpu.iew.exec_refs                     64080783                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11475005                       # Number of branches executed
system.cpu.iew.exec_stores                   12211635                       # Number of stores executed
system.cpu.iew.exec_rate                     0.254432                       # Inst execution rate
system.cpu.iew.wb_sent                      119890224                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      85480536                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47031033                       # num instructions producing a value
system.cpu.iew.wb_consumers                  87879900                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.179997                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535174                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        18664214                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482302                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            534875                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    148983556                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.521850                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.510275                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    121547303     81.58%     81.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13306218      8.93%     90.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3902162      2.62%     93.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2119528      1.42%     94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1937783      1.30%     95.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       976082      0.66%     96.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1595601      1.07%     97.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       718241      0.48%     98.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2880638      1.93%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    148983556                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60456059                       # Number of instructions committed
system.cpu.commit.committedOps               77747065                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27385723                       # Number of memory references committed
system.cpu.commit.loads                      15653991                       # Number of loads committed
system.cpu.commit.membars                      403571                       # Number of memory barriers committed
system.cpu.commit.branches                    9961071                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68852511                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991207                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2880638                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    240665808                       # The number of ROB reads
system.cpu.rob.rob_writes                   195946920                       # The number of ROB writes
system.cpu.timesIdled                         1776652                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       322877544                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4575281578                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60305678                       # Number of Instructions Simulated
system.cpu.committedOps                      77596684                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60305678                       # Number of Instructions Simulated
system.cpu.cpi                               7.874858                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.874858                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.126986                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.126986                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                547244885                       # number of integer regfile reads
system.cpu.int_regfile_writes                87532646                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8511                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2972                       # number of floating regfile writes
system.cpu.misc_regfile_reads                30145050                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 831837                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                58898886                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2658060                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2658059                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763332                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763332                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       607897                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2956                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq           13                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2969                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       246128                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       246128                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961789                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796637                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30578                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       127052                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7916056                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62740736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85535129                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        41644                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       210260                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      148527769                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148527769                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       199672                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3129078659                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1474541718                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2550360089                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      20171491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      74593037                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            980798                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.579102                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            10457750                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            981310                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             10.656928                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        6918450250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.579102                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999178                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999178                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          12500309                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         12500309                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     10457750                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        10457750                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      10457750                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         10457750                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     10457750                       # number of overall hits
system.cpu.icache.overall_hits::total        10457750                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1061214                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1061214                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1061214                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1061214                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1061214                       # number of overall misses
system.cpu.icache.overall_misses::total       1061214                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14272429649                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14272429649                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14272429649                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14272429649                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14272429649                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14272429649                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11518964                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11518964                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11518964                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11518964                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11518964                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11518964                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092128                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.092128                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.092128                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.092128                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.092128                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.092128                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13449.153186                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13449.153186                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5990                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               322                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    18.602484                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79868                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79868                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79868                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79868                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79868                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79868                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981346                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       981346                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       981346                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       981346                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       981346                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       981346                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11584683024                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11584683024                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11584683024                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11584683024                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11584683024                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11584683024                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8658250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8658250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8658250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      8658250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085194                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085194                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085194                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.085194                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085194                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.085194                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            64371                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        51362.964424                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1886397                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           129765                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            14.537025                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     2489982729000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    27.936805                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8173.687928                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6235.066458                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.563450                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000426                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124721                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.095140                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.783737                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65375                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3055                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6962                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54965                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997543                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18784884                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18784884                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52523                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10409                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       967861                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       387146                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1417939                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607897                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607897                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           41                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           41                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           10                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           10                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112916                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112916                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52523                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10409                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       967861                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       500062                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1530855                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52523                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10409                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       967861                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       500062                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1530855                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           42                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12345                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10721                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23110                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2915                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2915                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133212                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133212                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           42                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12345                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143933                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156322                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           42                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12345                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143933                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156322                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3605250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       158000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    903018500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    812779249                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1719560999                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       510978                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       510978                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10116159486                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10116159486                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3605250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       158000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    903018500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10928938735                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11835720485                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3605250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       158000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    903018500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10928938735                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11835720485                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52565                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10411                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       980206                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397867                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1441049                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607897                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607897                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2956                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2956                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           13                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           13                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246128                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246128                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52565                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10411                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       980206                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643995                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1687177                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52565                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10411                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       980206                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643995                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1687177                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000799                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000192                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012594                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026946                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016037                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986130                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986130                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.230769                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.230769                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541231                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541231                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000799                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000192                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012594                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223500                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092653                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000799                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000192                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012594                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223500                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092653                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        79000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   175.292624                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   175.292624                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59131                       # number of writebacks
system.cpu.l2cache.writebacks::total            59131                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           66                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           66                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           77                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           42                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12334                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10655                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23033                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2915                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2915                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133212                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133212                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           42                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12334                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143867                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156245                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           42                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12334                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143867                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156245                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3085750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       133500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    747187750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    675762749                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426169749                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29153914                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29153914                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8455143514                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8455143514                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3085750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    747187750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9130906263                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9881313263                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3085750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       133500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    747187750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9130906263                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9881313263                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6187249                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17442653817                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17442653817                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6187249                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000799                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000192                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012583                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026780                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015983                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986130                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986130                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.230769                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.230769                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541231                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541231                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000799                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000192                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012583                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223398                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092607                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000799                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000192                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012583                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223398                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092607                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            643483                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.993331                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            21507621                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            643995                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             33.397186                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          42430250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.993331                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         101519243                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        101519243                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     13755484                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13755484                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7258628                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7258628                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242811                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242811                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247593                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247593                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21014112                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21014112                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21014112                       # number of overall hits
system.cpu.dcache.overall_hits::total        21014112                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       737297                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        737297                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2963410                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2963410                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13576                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13576                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           13                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3700707                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3700707                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3700707                       # number of overall misses
system.cpu.dcache.overall_misses::total       3700707                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  10005137822                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  10005137822                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 141347559382                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185728250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    185728250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       206503                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       206503                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 151352697204                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 151352697204                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 151352697204                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 151352697204                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14492781                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14492781                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222038                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222038                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256387                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256387                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247606                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247606                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24714819                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24714819                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24714819                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24714819                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050873                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050873                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289904                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289904                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052951                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052951                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000053                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000053                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149736                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149736                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149736                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149736                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40898.319484                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40898.319484                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        32831                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        27415                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2635                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             279                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.459583                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    98.261649                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607897                       # number of writebacks
system.cpu.dcache.writebacks::total            607897                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       351582                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       351582                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2714405                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2714405                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1345                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1345                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3065987                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3065987                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3065987                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3065987                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385715                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385715                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249005                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249005                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12231                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12231                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634720                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634720                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634720                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634720                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4972029375                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4972029375                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11600619783                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11600619783                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    146011500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    146011500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       180497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       180497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16572649158                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  16572649158                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16572649158                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  16572649158                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26841536765                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26841536765                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026614                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026614                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024360                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024360                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047705                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047705                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000053                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025682                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025682                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1499067779549                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83033                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------