path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.534279                       # Number of seconds simulated
sim_ticks                                2534279149500                       # Number of ticks simulated
final_tick                               2534279149500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  43780                       # Simulator instruction rate (inst/s)
host_op_rate                                    56332                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1839722930                       # Simulator tick rate (ticks/s)
host_mem_usage                                 400528                       # Number of bytes of host memory used
host_seconds                                  1377.53                       # Real time elapsed on the host
sim_insts                                    60307893                       # Number of instructions simulated
sim_ops                                      77599512                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    119547392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            796992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9094160                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129441552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       796992                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          796992                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3783360                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6799432                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14943424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12453                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142130                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15098054                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59115                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813133                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47172148                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1136                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               314485                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3588460                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51076280                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          314485                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314485                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1492874                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1190110                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2682985                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1492874                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47172148                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1136                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              314485                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4778571                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53759265                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15098054                       # Total number of read requests seen
system.physmem.writeReqs                       813133                       # Total number of write requests seen
system.physmem.cpureqs                         218381                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    966275456                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52040512                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              129441552                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6799432                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      339                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4672                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                944601                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                943433                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                943409                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                943592                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                943465                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                943701                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                943525                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                943240                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                944001                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                943648                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               943214                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               942809                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               943923                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               943684                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               943779                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               943691                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 49135                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 48909                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50973                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51086                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51003                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51258                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51261                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51198                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51347                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51095                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50750                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                50404                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51353                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50977                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51264                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51120                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32444                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2534279100000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      36                       # Categorize read packet sizes
system.physmem.readPktSize::3                14943424                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154594                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  59115                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1052560                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    982701                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    988227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3681755                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2757300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2755283                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2712082                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     17052                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     27533                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    39830                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    27503                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    10257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    10197                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    13755                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     6392                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2818                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32536                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32462                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        42559                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    23924.789210                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1816.195393                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   32272.883514                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95           8308     19.52%     19.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159         3417      8.03%     27.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223         2234      5.25%     32.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287         1796      4.22%     37.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351         1258      2.96%     39.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415         1103      2.59%     42.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479          837      1.97%     44.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543          830      1.95%     46.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607          538      1.26%     47.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671          533      1.25%     49.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735          414      0.97%     49.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799          384      0.90%     50.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863          258      0.61%     51.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927          273      0.64%     52.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991          193      0.45%     52.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055          240      0.56%     53.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119          148      0.35%     53.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183          144      0.34%     53.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247          105      0.25%     54.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311          120      0.28%     54.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375           89      0.21%     54.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439          396      0.93%     55.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503         1932      4.54%     60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567          440      1.03%     61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631           89      0.21%     61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695          139      0.33%     61.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759           56      0.13%     61.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823          104      0.24%     61.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887           40      0.09%     62.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951           62      0.15%     62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015           22      0.05%     62.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079           58      0.14%     62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143           29      0.07%     62.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207           47      0.11%     62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271           13      0.03%     62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335           37      0.09%     62.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399           11      0.03%     62.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463           28      0.07%     62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527           17      0.04%     62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591           25      0.06%     62.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655            7      0.02%     62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719           18      0.04%     62.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783            4      0.01%     62.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847           18      0.04%     63.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911            6      0.01%     63.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975           14      0.03%     63.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039            6      0.01%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103           12      0.03%     63.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167            2      0.00%     63.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231            7      0.02%     63.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295            6      0.01%     63.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359           17      0.04%     63.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423            5      0.01%     63.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487            8      0.02%     63.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551            3      0.01%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615            5      0.01%     63.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679            6      0.01%     63.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743            9      0.02%     63.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807            1      0.00%     63.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871            5      0.01%     63.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935            4      0.01%     63.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999            9      0.02%     63.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063            4      0.01%     63.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127           39      0.09%     63.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191            5      0.01%     63.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255            7      0.02%     63.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319            4      0.01%     63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383            6      0.01%     63.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447            2      0.00%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511            3      0.01%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575            4      0.01%     63.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4639            4      0.01%     63.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767            6      0.01%     63.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831            1      0.00%     63.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895            8      0.02%     63.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959            3      0.01%     63.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023            5      0.01%     63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151            5      0.01%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215            1      0.00%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279            1      0.00%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343            1      0.00%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407            1      0.00%     63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471            2      0.00%     63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535            3      0.01%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5599            1      0.00%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5663            2      0.00%     63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5727            3      0.01%     63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919            3      0.01%     63.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047            3      0.01%     63.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111            1      0.00%     63.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175            6      0.01%     63.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6239            3      0.01%     63.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303            1      0.00%     63.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6431            1      0.00%     63.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495            2      0.00%     63.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559            3      0.01%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6623            2      0.00%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6687            3      0.01%     63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751            1      0.00%     63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815           18      0.04%     63.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879            5      0.01%     63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943            1      0.00%     63.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071            8      0.02%     63.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199            6      0.01%     63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7327            1      0.00%     63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391            1      0.00%     63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455            8      0.02%     63.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583            9      0.02%     63.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7647            2      0.00%     63.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711            6      0.01%     63.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839            3      0.01%     63.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903            3      0.01%     63.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967            4      0.01%     63.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031            5      0.01%     63.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095            7      0.02%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159            4      0.01%     63.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223          322      0.76%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8735            1      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8991            1      0.00%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9183            1      0.00%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9247            2      0.00%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9503            1      0.00%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9567            1      0.00%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271           19      0.04%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10527            1      0.00%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11039            1      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11295            1      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11551            2      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11935            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12575            2      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343            4      0.01%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13599            1      0.00%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13855            1      0.00%     64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14367            2      0.00%     64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14623            1      0.00%     64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14879            2      0.00%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15071            1      0.00%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15199            1      0.00%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15391            3      0.01%     64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15647            2      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16159            1      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16415            2      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16671            1      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16927            3      0.01%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17183            2      0.00%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17247            2      0.00%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17375            1      0.00%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17439            2      0.00%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17823            1      0.00%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17951            2      0.00%     64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17984-18015            1      0.00%     64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18207            2      0.00%     64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463            2      0.00%     64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19231            2      0.00%     64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19840-19871            1      0.00%     64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20255            3      0.01%     64.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20544-20575            1      0.00%     64.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20767            1      0.00%     64.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21279            1      0.00%     64.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21343            1      0.00%     64.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21535            2      0.00%     64.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22047            1      0.00%     64.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22303            1      0.00%     64.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22431            1      0.00%     64.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22559            1      0.00%     64.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22592-22623            1      0.00%     64.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22815            1      0.00%     64.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23071            1      0.00%     64.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23583            2      0.00%     64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23839            2      0.00%     64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24351            2      0.00%     64.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24607            4      0.01%     64.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25119            1      0.00%     64.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25631            3      0.01%     64.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25664-25695            1      0.00%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25759            1      0.00%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26399            1      0.00%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26655            2      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27328-27359            1      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27487            1      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27679            1      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28447            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28703            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28767            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28959            2      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29215            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29376-29407            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29471            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29727            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29983            1      0.00%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30016-30047            1      0.00%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30239            3      0.01%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30623            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30751            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31135            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31263            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31424-31455            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31519            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31775            2      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32287            1      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33695            2      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33759            1      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823           44      0.10%     65.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34176-34207            1      0.00%     65.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34752-34783            1      0.00%     65.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36639            1      0.00%     65.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36895            2      0.00%     65.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37248-37279            1      0.00%     65.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39296-39327            1      0.00%     65.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39808-39839            1      0.00%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40000-40031            1      0.00%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42015            1      0.00%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42048-42079            1      0.00%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42527            2      0.00%     65.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43295            1      0.00%     65.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44703            1      0.00%     65.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44831            1      0.00%     65.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45343            1      0.00%     65.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47647            1      0.00%     65.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47967            1      0.00%     65.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48159            1      0.00%     65.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48671            1      0.00%     65.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48927            1      0.00%     65.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49183            1      0.00%     65.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49920-49951            1      0.00%     65.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50207            2      0.00%     65.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50432-50463            1      0.00%     65.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50719            1      0.00%     65.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54272-54303            1      0.00%     65.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56000-56031            1      0.00%     65.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56832-56863            1      0.00%     65.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57344-57375            1      0.00%     65.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58399            1      0.00%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58944-58975            1      0.00%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59840-59871            1      0.00%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62208-62239            1      0.00%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62848-62879            1      0.00%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63232-63263            1      0.00%     65.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63519            2      0.00%     65.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64256-64287            1      0.00%     65.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64704-64735            1      0.00%     65.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65055           13      0.03%     65.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65152-65183           18      0.04%     65.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65311           18      0.04%     65.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65344-65375            8      0.02%     65.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65503           18      0.04%     65.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567        14406     33.85%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::113216-113247            1      0.00%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129664-129695            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129792-129823            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129984-130015            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130432-130463            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103          325      0.76%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127            3      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::168704-168735            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::169664-169695            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::190464-190495            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196352-196383            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196639            9      0.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          42559                       # Bytes accessed per row activation
system.physmem.totQLat                   355117101750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              446336213000                       # Sum of mem lat for all requests
system.physmem.totBusLat                  75488575000                       # Total cycles spent in databus access
system.physmem.totBankLat                 15730536250                       # Total cycles spent in bank access
system.physmem.avgQLat                       23521.25                       # Average queueing delay per request
system.physmem.avgBankLat                     1041.92                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  29563.16                       # Average memory access latency
system.physmem.avgRdBW                         381.28                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.53                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.08                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.14                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.18                       # Average read queue length over time
system.physmem.avgWrQLen                        11.71                       # Average write queue length over time
system.physmem.readRowHits                   15070837                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    797438                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  98.07                       # Row buffer hit rate for writes
system.physmem.avgGap                       159276.56                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54705448                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16150672                       # Transaction distribution
system.membus.trans_dist::ReadResp           16150669                       # Transaction distribution
system.membus.trans_dist::WriteReq             763336                       # Transaction distribution
system.membus.trans_dist::WriteResp            763336                       # Transaction distribution
system.membus.trans_dist::Writeback             59115                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4669                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4672                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131424                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131424                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382946                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885755                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272475                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29886845                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     29886845                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave      2382946                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port     31772600                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio         3770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34159320                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390309                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16693592                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7540                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19091509                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119547368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    119547368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave      2390309                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port    136240960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio         7540                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           138638877                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              138638877                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1491846000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy         17371820500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.7                       # Layer utilization (%)
system.membus.reqLayer3.occupancy             3645000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4719558707                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33739093743                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      48115298                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16126739                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16126726                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8158                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8158                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          518                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29886835                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     29886835                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio         7936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio          518                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio         1026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side     29886835                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32269781                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1036                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2052                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390309                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119547288                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119547288                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio        15872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio         1036                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio         2052                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side    119547288                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            121937597                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               121937597                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3973000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               518000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               519000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         14943424000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374788000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         29886822000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.2                       # Layer utilization (%)
system.cpu.branchPred.lookups                14673159                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11756965                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            704729                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9767663                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7945266                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.342548                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1399657                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72413                       # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits             14987453                       # DTB read hits
system.cpu.checker.dtb.read_misses               7307                       # DTB read misses
system.cpu.checker.dtb.write_hits            11227781                       # DTB write hits
system.cpu.checker.dtb.write_misses              2189                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults            178                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses         14994760                       # DTB read accesses
system.cpu.checker.dtb.write_accesses        11229970                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                  26215234                       # DTB hits
system.cpu.checker.dtb.misses                    9496                       # DTB misses
system.cpu.checker.dtb.accesses              26224730                       # DTB accesses
system.cpu.checker.itb.inst_hits             61481893                       # ITB inst hits
system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses         61486364                       # ITB inst accesses
system.cpu.checker.itb.hits                  61481893                       # DTB hits
system.cpu.checker.itb.misses                    4471                       # DTB misses
system.cpu.checker.itb.accesses              61486364                       # DTB accesses
system.cpu.checker.numCycles                 77885319                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51397173                       # DTB read hits
system.cpu.dtb.read_misses                      63986                       # DTB read misses
system.cpu.dtb.write_hits                    11699533                       # DTB write hits
system.cpu.dtb.write_misses                     15890                       # DTB write misses
system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     6549                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2402                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    405                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1410                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51461159                       # DTB read accesses
system.cpu.dtb.write_accesses                11715423                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63096706                       # DTB hits
system.cpu.dtb.misses                           79876                       # DTB misses
system.cpu.dtb.accesses                      63176582                       # DTB accesses
system.cpu.itb.inst_hits                     12260245                       # ITB inst hits
system.cpu.itb.inst_misses                      11468                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     4980                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2998                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 12271713                       # ITB inst accesses
system.cpu.itb.hits                          12260245                       # DTB hits
system.cpu.itb.misses                           11468                       # DTB misses
system.cpu.itb.accesses                      12271713                       # DTB accesses
system.cpu.numCycles                        475189978                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30497823                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       96057374                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14673159                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9344923                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21151922                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5296118                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     123395                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               94706901                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2678                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         86562                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      2683934                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          445                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  12256747                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                864492                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5531                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          152887644                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.777320                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.141699                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131751310     86.18%     86.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1303513      0.85%     87.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1714679      1.12%     88.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2493622      1.63%     89.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2205066      1.44%     91.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1108856      0.73%     91.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2738323      1.79%     93.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   743817      0.49%     94.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8828458      5.77%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            152887644                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.030879                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.202145                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32458089                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              96821111                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19172249                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                971461                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3464734                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1958214                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171741                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              112504503                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                568893                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3464734                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 34365136                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38157390                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       52654113                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18177530                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6068741                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              106257538                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20628                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1016430                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4078403                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              665                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           110740396                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             486151881                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        486061534                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             90347                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78390288                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32350107                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             830682                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         737164                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12219946                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             20282216                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13494315                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1963339                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2435947                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97859231                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1984036                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 124319403                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            165680                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21668523                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     56420296                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         501641                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     152887644                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.813142                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.528360                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           108584137     71.02%     71.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13613798      8.90%     79.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7066944      4.62%     84.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5988746      3.92%     88.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12566780      8.22%     96.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2768589      1.81%     98.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1723460      1.13%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              446866      0.29%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              128324      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       152887644                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   62053      0.70%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      3      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8365072     94.62%     95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                413828      4.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58665929     47.19%     47.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93120      0.07%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  16      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  1      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              11      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52876194     42.53%     90.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12318342      9.91%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              124319403                       # Type of FU issued
system.cpu.iq.rate                           0.261620                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8840956                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071115                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          410589228                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         121528348                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86069861                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23359                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10285                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              132784241                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12452                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           624311                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4627641                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6443                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30069                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1762200                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107875                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        918337                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3464734                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                29357042                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                436051                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100064926                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            205472                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              20282216                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13494315                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1410818                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 114442                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3537                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30069                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         350642                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       268888                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               619530                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121646726                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52084248                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2672677                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221659                       # number of nop insts executed
system.cpu.iew.exec_refs                     64295158                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11560329                       # Number of branches executed
system.cpu.iew.exec_stores                   12210910                       # Number of stores executed
system.cpu.iew.exec_rate                     0.255996                       # Inst execution rate
system.cpu.iew.wb_sent                      120490085                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      86080146                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47268053                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88199499                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.181149                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535922                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        21408137                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482395                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            535479                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    149422910                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.520334                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.507055                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    121949451     81.61%     81.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13299405      8.90%     90.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3946740      2.64%     93.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2141050      1.43%     94.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1955041      1.31%     95.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       959721      0.64%     96.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1537792      1.03%     97.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       781343      0.52%     98.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2852367      1.91%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    149422910                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60458274                       # Number of instructions committed
system.cpu.commit.committedOps               77749893                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27386690                       # Number of memory references committed
system.cpu.commit.loads                      15654575                       # Number of loads committed
system.cpu.commit.membars                      403596                       # Number of memory barriers committed
system.cpu.commit.branches                    9961373                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68855105                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991268                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2852367                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    243879966                       # The number of ROB reads
system.cpu.rob.rob_writes                   201882555                       # The number of ROB writes
system.cpu.timesIdled                         1780421                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       322302334                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4593285278                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60307893                       # Number of Instructions Simulated
system.cpu.committedOps                      77599512                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60307893                       # Number of Instructions Simulated
system.cpu.cpi                               7.879399                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.879399                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.126913                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.126913                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                550704703                       # number of integer regfile reads
system.cpu.int_regfile_writes                88578313                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8302                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2882                       # number of floating regfile writes
system.cpu.misc_regfile_reads                30116391                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 831896                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                58661050                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2657246                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2657245                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       607669                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2958                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq           15                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2973                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       246055                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       246055                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side      1960500                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      5796171                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma        30982                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma       126318                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count                  7913971                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side     62698816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     85512245                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma        42284                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma       208804                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size             148462149                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148462149                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       201328                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3128322117                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1471549889                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2533210636                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      20419483                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      74237753                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.replacements                 980157                       # number of replacements
system.cpu.icache.tagsinuse                511.579914                       # Cycle average of tags in use
system.cpu.icache.total_refs                 11196212                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 980669                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  11.416912                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6837358000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.579914                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999180                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999180                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11196212                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11196212                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11196212                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11196212                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11196212                       # number of overall hits
system.cpu.icache.overall_hits::total        11196212                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1060409                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1060409                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1060409                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1060409                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1060409                       # number of overall misses
system.cpu.icache.overall_misses::total       1060409                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14257699991                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14257699991                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14257699991                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14257699991                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14257699991                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14257699991                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12256621                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12256621                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12256621                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12256621                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12256621                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12256621                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.086517                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.086517                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.086517                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.086517                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.086517                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.086517                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13445.472446                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13445.472446                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6872                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               372                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    18.473118                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79698                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79698                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79698                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79698                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79698                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79698                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       980711                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       980711                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       980711                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       980711                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       980711                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       980711                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11583440602                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11583440602                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11583440602                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11583440602                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11583440602                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11583440602                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9547000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9547000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9547000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      9547000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.080015                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.080015                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.080015                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.080015                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.080015                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.080015                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.268153                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.268153                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.268153                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.268153                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.268153                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.268153                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 64365                       # number of replacements
system.cpu.l2cache.tagsinuse             51350.135703                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1885273                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                129757                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 14.529259                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          2499221448500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36903.083753                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    33.180761                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.000367                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   8167.882252                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6245.988569                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.563096                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000506                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.124632                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.095306                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.783541                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52156                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10569                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       967205                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       387072                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1417002                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607669                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607669                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           12                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           12                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112874                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112874                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52156                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10569                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       967205                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       499946                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1529876                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52156                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10569                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       967205                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       499946                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1529876                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12345                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10738                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23130                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2912                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2912                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133181                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133181                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           45                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12345                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143919                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156311                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           45                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12345                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143919                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156311                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4040500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       130000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    909082500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    805516497                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1718769497                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       409500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       409500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9052113500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9052113500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4040500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       130000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    909082500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9857629997                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10770882997                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4040500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       130000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    909082500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9857629997                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10770882997                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52201                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10571                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       979550                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397810                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1440132                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607669                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607669                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2958                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2958                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           15                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           15                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246055                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246055                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52201                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10571                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       979550                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643865                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1686187                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52201                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10571                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       979550                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643865                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1686187                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000862                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000189                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012603                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026993                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016061                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984449                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984449                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.200000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541265                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541265                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000862                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000189                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012603                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223524                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092701                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000862                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000189                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012603                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223524                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092701                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89788.888889                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        65000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73639.732685                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75015.505401                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74309.100605                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   140.625000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   140.625000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67968.505267                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67968.505267                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89788.888889                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        65000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73639.732685                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68494.291907                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68906.749986                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89788.888889                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        65000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73639.732685                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68494.291907                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68906.749986                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59115                       # number of writebacks
system.cpu.l2cache.writebacks::total            59115                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           68                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           68                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           79                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           68                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           79                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           45                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12334                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10670                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23051                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2912                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2912                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133181                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133181                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           45                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12334                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143851                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156232                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           45                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12334                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143851                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156232                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3481250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       105750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    755022750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    668946247                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1427555997                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29123912                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29123912                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7387753007                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7387753007                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3481250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       105750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    755022750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8056699254                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8815309004                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3481250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       105750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    755022750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8056699254                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8815309004                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      7078250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166940694000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166947772250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  26398880620                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  26398880620                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      7078250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193339574620                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193346652870                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000862                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000189                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012591                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026822                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016006                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984449                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984449                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541265                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541265                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000862                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000189                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012591                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223418                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092654                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000862                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000189                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012591                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223418                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092654                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55471.523768                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55471.523768                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61214.751905                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56007.252324                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56424.477725                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61214.751905                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56007.252324                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56424.477725                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643353                       # number of replacements
system.cpu.dcache.tagsinuse                511.992092                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21505591                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 643865                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.400777                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               48193000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.992092                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13753583                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13753583                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7258444                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7258444                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242854                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242854                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247602                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247602                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21012027                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21012027                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21012027                       # number of overall hits
system.cpu.dcache.overall_hits::total        21012027                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       737498                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        737498                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2963942                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2963942                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13539                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13539                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           15                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           15                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3701440                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3701440                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3701440                       # number of overall misses
system.cpu.dcache.overall_misses::total       3701440                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  10068067500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  10068067500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 132595635732                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    183801000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    183801000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       231000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       231000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 142663703232                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 142663703232                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 142663703232                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 142663703232                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14491081                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14491081                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222386                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222386                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256393                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256393                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247617                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247617                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24713467                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24713467                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24713467                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24713467                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050893                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050893                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289946                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289946                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052806                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052806                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000061                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000061                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149774                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149774                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149774                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149774                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        15400                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        15400                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38542.757206                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38542.757206                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        32274                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        26462                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             287                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.238908                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    92.202091                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607669                       # number of writebacks
system.cpu.dcache.writebacks::total            607669                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       351798                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       351798                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2715004                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2715004                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1354                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1354                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3066802                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3066802                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3066802                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3066802                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385700                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385700                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248938                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       248938                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12185                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12185                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           15                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           15                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634638                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634638                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634638                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634638                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4965601859                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4965601859                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10500826931                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10500826931                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    144262002                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    144262002                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       201000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       201000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15466428790                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15466428790                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15466428790                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15466428790                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  35770060494                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  35770060494                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026616                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026616                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024352                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024352                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047525                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047525                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000061                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000061                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025680                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025680                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025680                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025680                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        13400                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        13400                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1488848485257                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83044                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------