path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.502550                       # Number of seconds simulated
sim_ticks                                2502549875500                       # Number of ticks simulated
final_tick                               2502549875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  75474                       # Simulator instruction rate (inst/s)
host_op_rate                                    97450                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3170228022                       # Simulator tick rate (ticks/s)
host_mem_usage                                 386888                       # Number of bytes of host memory used
host_seconds                                   789.39                       # Real time elapsed on the host
sim_insts                                    59578267                       # Number of instructions simulated
sim_ops                                      76925839                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    118994504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            800128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9094928                       # Number of bytes read from this memory
system.physmem.bytes_read::total            128893400                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       800128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          800128                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3786176                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6802248                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14874313                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12502                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142142                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15029017                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59159                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813177                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47549304                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               319725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3634264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51504828                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          319725                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             319725                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1512927                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1205200                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2718127                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1512927                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47549304                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              319725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4839464                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54222954                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         64431                       # number of replacements
system.l2c.tagsinuse                     51237.782352                       # Cycle average of tags in use
system.l2c.total_refs                         2028510                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         15.624716                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2492014554000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36760.884600                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       47.476285                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           8187.042847                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           6242.378435                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.560927                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000724                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.124924                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.095251                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.781827                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        121963                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker         11826                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst              977935                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              383708                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1495432                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          675442                       # number of Writeback hits
system.l2c.Writeback_hits::total               675442                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               42                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  42                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            112737                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112737                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         121963                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker          11826                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst               977935                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               496445                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1608169                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        121963                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker         11826                       # number of overall hits
system.l2c.overall_hits::cpu.inst              977935                       # number of overall hits
system.l2c.overall_hits::cpu.data              496445                       # number of overall hits
system.l2c.overall_hits::total                1608169                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             12384                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23135                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          133229                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133229                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              12384                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             143920                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156364                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker           59                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu.inst             12384                       # number of overall misses
system.l2c.overall_misses::cpu.data            143920                       # number of overall misses
system.l2c.overall_misses::total               156364                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3091500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    659591498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data    562236498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1224979496                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data       944500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       944500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   7069904999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7069904999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      3091500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    659591498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   7632141497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8294884495                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      3091500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    659591498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   7632141497                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8294884495                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       122022                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker        11827                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst          990319                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          394399                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1518567                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       675442                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           675442                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         2951                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2951                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        245966                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           245966                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       122022                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker        11827                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst           990319                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           640365                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1764533                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       122022                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker        11827                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst          990319                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          640365                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1764533                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000085                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.012505                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.027107                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015235                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.985768                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.985768                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.541656                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541656                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000085                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.012505                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.224747                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.088615                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000085                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.012505                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.224747                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.088615                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52949.189367                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data   324.682021                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   324.682021                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53065.811490                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53048.556541                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53048.556541                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59159                       # number of writebacks
system.l2c.writebacks::total                    59159                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst              9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst               9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst              9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        12375                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        10629                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23064                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       133229                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133229                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         12375                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        143858                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156293                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        12375                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       143858                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156293                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    508160500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data    430170499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    940750999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116825000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    116825000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5436034999                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5436034999                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    508160500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   5866205498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6376785998                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    508160500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   5866205498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6376785998                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31373446015                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  31373446015                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 162795884015                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026950                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015188                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985768                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.985768                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541656                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541656                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.088575                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.088575                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits             15048164                       # DTB read hits
system.cpu.checker.dtb.read_misses               7309                       # DTB read misses
system.cpu.checker.dtb.write_hits            11293826                       # DTB write hits
system.cpu.checker.dtb.write_misses              2190                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults            177                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses         15055473                       # DTB read accesses
system.cpu.checker.dtb.write_accesses        11296016                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                  26341990                       # DTB hits
system.cpu.checker.dtb.misses                    9499                       # DTB misses
system.cpu.checker.dtb.accesses              26351489                       # DTB accesses
system.cpu.checker.itb.inst_hits             60744881                       # ITB inst hits
system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses         60749352                       # ITB inst accesses
system.cpu.checker.itb.hits                  60744881                       # DTB hits
system.cpu.checker.itb.misses                    4471                       # DTB misses
system.cpu.checker.itb.accesses              60749352                       # DTB accesses
system.cpu.checker.numCycles                 77204260                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51771660                       # DTB read hits
system.cpu.dtb.read_misses                      81258                       # DTB read misses
system.cpu.dtb.write_hits                    11880398                       # DTB write hits
system.cpu.dtb.write_misses                     17961                       # DTB write misses
system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     8043                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      3044                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    609                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1282                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51852918                       # DTB read accesses
system.cpu.dtb.write_accesses                11898359                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63652058                       # DTB hits
system.cpu.dtb.misses                           99219                       # DTB misses
system.cpu.dtb.accesses                      63751277                       # DTB accesses
system.cpu.itb.inst_hits                     13142261                       # ITB inst hits
system.cpu.itb.inst_misses                      12247                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     5262                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 13154508                       # ITB inst accesses
system.cpu.itb.hits                          13142261                       # DTB hits
system.cpu.itb.misses                           12247                       # DTB misses
system.cpu.itb.accesses                      13154508                       # DTB accesses
system.cpu.numCycles                        413642740                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 14974990                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11915620                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             753400                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10068197                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  7820088                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1448775                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               80927                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           33422471                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       99542070                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14974990                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9268863                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21759182                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6002262                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     163536                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               93319816                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2533                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        133610                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       208459                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          397                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13138017                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1024097                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6504                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          153128307                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.804842                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.182667                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131386008     85.80%     85.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1369017      0.89%     86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1759019      1.15%     87.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2640315      1.72%     89.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1819667      1.19%     90.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1142419      0.75%     91.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2920911      1.91%     93.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   807762      0.53%     93.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9283189      6.06%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            153128307                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.036203                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.240647                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35537493                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              93048586                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19509299                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1086349                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3946580                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2100058                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                174557                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116122172                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                568338                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3946580                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37621271                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                39594801                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       46881047                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18412397                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6672211                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              108597287                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  4175                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1156489                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4484156                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            30967                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           113073752                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             499820515                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        499727174                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             93341                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              77686691                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 35387060                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             898607                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         797702                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13307124                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21058263                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13875749                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1965166                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2564814                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   99781831                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1555350                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 124613166                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            199798                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23638127                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     65777806                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         268083                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     153128307                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.813783                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.516400                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           107849903     70.43%     70.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14560254      9.51%     79.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7302452      4.77%     84.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5913038      3.86%     88.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12593494      8.22%     96.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2809204      1.83%     98.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1536315      1.00%     99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              438168      0.29%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              125479      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       153128307                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   53462      0.61%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      2      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8367005     94.75%     95.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                409700      4.64%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            106530      0.09%      0.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58482659     46.93%     47.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                95330      0.08%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  11      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53414157     42.86%     89.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12512351     10.04%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              124613166                       # Type of FU issued
system.cpu.iq.rate                           0.301258                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8830169                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.070861                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          411460543                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         124996425                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     85630389                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               22925                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12868                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10343                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              133324707                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12098                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           646336                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5343093                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11106                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        35068                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2077574                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107202                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1049886                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3946580                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                29463666                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                540836                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           101593235                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21058263                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13875749                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             964547                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 125689                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 40656                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          35068                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         381127                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       332167                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               713294                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121438397                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52461807                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3174769                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        256054                       # number of nop insts executed
system.cpu.iew.exec_refs                     64853171                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11412736                       # Number of branches executed
system.cpu.iew.exec_stores                   12391364                       # Number of stores executed
system.cpu.iew.exec_rate                     0.293583                       # Inst execution rate
system.cpu.iew.wb_sent                      120063166                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      85640732                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  46459932                       # num instructions producing a value
system.cpu.iew.wb_consumers                  84649521                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.207040                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.548851                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       59728648                       # The number of committed instructions
system.cpu.commit.commitCommittedOps         77076220                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        24329020                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1287267                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            625309                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    149264139                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.516375                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.492760                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    121340444     81.29%     81.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13976446      9.36%     90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3929866      2.63%     93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2230737      1.49%     94.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1774137      1.19%     95.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1064202      0.71%     96.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1398926      0.94%     97.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       658331      0.44%     98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2891050      1.94%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    149264139                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             59728648                       # Number of instructions committed
system.cpu.commit.committedOps               77076220                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27513345                       # Number of memory references committed
system.cpu.commit.loads                      15715170                       # Number of loads committed
system.cpu.commit.membars                      413057                       # Number of memory barriers committed
system.cpu.commit.branches                    9904308                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68616986                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995953                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2891050                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    246021016                       # The number of ROB reads
system.cpu.rob.rob_writes                   206855771                       # The number of ROB writes
system.cpu.timesIdled                         1910853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       260514433                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4591368963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    59578267                       # Number of Instructions Simulated
system.cpu.committedOps                      76925839                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              59578267                       # Number of Instructions Simulated
system.cpu.cpi                               6.942846                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         6.942846                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.144033                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.144033                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                551124725                       # number of integer regfile reads
system.cpu.int_regfile_writes                87730819                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8186                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2858                       # number of floating regfile writes
system.cpu.misc_regfile_reads               131789755                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912697                       # number of misc regfile writes
system.cpu.icache.replacements                 991190                       # number of replacements
system.cpu.icache.tagsinuse                511.611770                       # Cycle average of tags in use
system.cpu.icache.total_refs                 12061455                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 991702                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  12.162378                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6426198000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.611770                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999242                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999242                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     12061455                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12061455                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12061455                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12061455                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12061455                       # number of overall hits
system.cpu.icache.overall_hits::total        12061455                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1076423                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1076423                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1076423                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1076423                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1076423                       # number of overall misses
system.cpu.icache.overall_misses::total       1076423                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16851120991                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16851120991                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16851120991                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16851120991                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16851120991                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16851120991                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13137878                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13137878                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13137878                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13137878                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13137878                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13137878                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081933                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.081933                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.081933                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.081933                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.081933                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.081933                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15654.738881                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15654.738881                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2871493                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               461                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  6228.835141                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        67899                       # number of writebacks
system.cpu.icache.writebacks::total             67899                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84680                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        84680                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        84680                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        84680                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        84680                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        84680                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991743                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       991743                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       991743                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       991743                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       991743                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       991743                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12825867499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12825867499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12825867499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12825867499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12825867499                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12825867499                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075487                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.075487                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.075487                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643139                       # number of replacements
system.cpu.dcache.tagsinuse                511.991335                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21733833                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 643651                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.766487                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.991335                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13904166                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13904166                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7257095                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7257095                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       283844                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       283844                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       285639                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285639                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21161261                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21161261                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21161261                       # number of overall hits
system.cpu.dcache.overall_hits::total        21161261                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       765252                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        765252                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2993311                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2993311                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13765                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13765                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3758563                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3758563                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3758563                       # number of overall misses
system.cpu.dcache.overall_misses::total       3758563                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14844603000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14844603000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 129412035593                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223977000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    223977000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       405000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       405000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 144256638593                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 144256638593                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 144256638593                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 144256638593                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14669418                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14669418                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10250406                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10250406                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       297609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       285658                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285658                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24919824                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24919824                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24919824                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24919824                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052166                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.052166                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292019                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.292019                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046252                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046252                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000067                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000067                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.150826                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.150826                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.150826                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.150826                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38380.795691                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38380.795691                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     32633902                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7260500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              7285                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             283                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  4479.602196                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607543                       # number of writebacks
system.cpu.dcache.writebacks::total            607543                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379767                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       379767                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744505                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2744505                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3124272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3124272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3124272                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3124272                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385485                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385485                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248806                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       248806                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12312                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12312                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634291                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634291                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634291                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634291                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6242554097                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6242554097                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9246380950                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9246380950                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    164108000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    164108000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       341500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       341500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15488935047                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15488935047                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15488935047                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15488935047                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41215087708                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41215087708                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026278                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026278                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024273                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024273                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041370                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041370                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000067                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000067                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025453                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025453                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1298563544001                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    88049                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------