path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.102937                       # Number of seconds simulated
sim_ticks                                1102937390000                       # Number of ticks simulated
final_tick                               1102937390000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  67484                       # Simulator instruction rate (inst/s)
host_op_rate                                    86868                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1208579190                       # Simulator tick rate (ticks/s)
host_mem_usage                                 412736                       # Number of bytes of host memory used
host_seconds                                   912.59                       # Real time elapsed on the host
sim_insts                                    61585042                       # Number of instructions simulated
sim_ops                                      79274675                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           408896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4378804                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           405888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5226160                       # Number of bytes read from this memory
system.physmem.bytes_read::total             59180644                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       408896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       405888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          814784                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4259456                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7286800                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6094848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           11                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6389                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68491                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6342                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             81685                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6257788                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66554                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823390                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        44208116                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           116                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              370734                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3970129                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1161                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              368006                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4738401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53657301                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         370734                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         368006                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             738740                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3861920                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              15413                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2729388                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6606721                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3861920                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       44208116                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          638                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          116                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             370734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3985543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1161                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             368006                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7467789                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               60264023                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6257788                       # Total number of read requests seen
system.physmem.writeReqs                       823390                       # Total number of write requests seen
system.physmem.cpureqs                         281560                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    400498432                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52696960                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               59180644                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7286800                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       80                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              12623                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                391400                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                391208                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                390865                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                391604                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                391517                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                390867                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                390930                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                391637                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                391401                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                390707                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               390849                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               391231                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               391237                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               390522                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               390468                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               391265                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 51411                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 51226                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 51010                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51681                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51542                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50958                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50977                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51664                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 52039                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51352                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51491                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51878                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51845                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51250                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51172                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51894                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     2242937                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1102936257500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                     105                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6094848                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  162835                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                2999773                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  66554                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                12623                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    493621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    430392                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    391768                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1441431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1086063                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1098338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1064335                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     26976                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     24854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     44565                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    63872                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    44300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    12061                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    11818                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    17153                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     5993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      138                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3067                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32700                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                   199170690855                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              238991050855                       # Sum of mem lat for all requests
system.physmem.totBusLat                  31288540000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8531820000                       # Total cycles spent in bank access
system.physmem.avgQLat                       31828.06                       # Average queueing delay per request
system.physmem.avgBankLat                     1363.41                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  38191.47                       # Average memory access latency
system.physmem.avgRdBW                         363.12                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          47.78                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  53.66                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.61                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.21                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.22                       # Average read queue length over time
system.physmem.avgWrQLen                        10.24                       # Average write queue length over time
system.physmem.readRowHits                    6213872                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    799892                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.15                       # Row buffer hit rate for writes
system.physmem.avgGap                       155756.04                       # Average gap between requests
system.l2c.replacements                         72539                       # number of replacements
system.l2c.tagsinuse                     53752.248637                       # Cycle average of tags in use
system.l2c.total_refs                         1841179                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        137732                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.367838                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        39388.476412                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       3.826353                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000803                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4008.993875                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2816.909683                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      12.612753                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3717.226162                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          3804.202595                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.601020                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000058                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.061172                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.042983                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000192                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.056720                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.058048                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.820194                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        21699                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4247                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             385844                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166771                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30512                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5160                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             591639                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198020                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1403892                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          581178                       # number of Writeback hits
system.l2c.Writeback_hits::total               581178                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1163                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             739                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1902                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           201                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           143                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               344                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48042                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58985                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107027                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         21699                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4247                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              385844                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214813                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30512                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5160                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              591639                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              257005                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1510919                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        21699                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4247                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             385844                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214813                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30512                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5160                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             591639                       # number of overall hits
system.l2c.overall_hits::cpu1.data             257005                       # number of overall hits
system.l2c.overall_hits::total                1510919                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           11                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6268                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6367                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           20                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6307                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6294                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25269                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5150                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3804                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8954                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          644                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          418                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1062                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63486                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76591                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140077                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           11                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6268                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69853                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6307                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             82885                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165346                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           11                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6268                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69853                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           20                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6307                       # number of overall misses
system.l2c.overall_misses::cpu1.data            82885                       # number of overall misses
system.l2c.overall_misses::total               165346                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       727500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    346856000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    362407499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1360500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    380856500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    395446999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1487772998                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8791989                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     11737000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     20528989                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       591000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2890499                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3481499                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3145264486                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4121590993                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7266855479                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       727500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    346856000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3507671985                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1360500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    380856500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4517037992                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8754628477                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       727500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    346856000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3507671985                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1360500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    380856500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4517037992                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8754628477                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        21710                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4249                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         392112                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         173138                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30532                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5160                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         597946                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204314                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1429161                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       581178                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           581178                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6313                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4543                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10856                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          845                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          561                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1406                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111528                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135576                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247104                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        21710                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4249                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          392112                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284666                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30532                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5160                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          597946                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          339890                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1676265                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        21710                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4249                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         392112                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284666                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30532                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5160                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         597946                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         339890                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1676265                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000507                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015985                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036774                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000655                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010548                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030806                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017681                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.815777                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.837332                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.824797                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.762130                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.745098                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.755334                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.569238                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.564930                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.566875                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000507                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015985                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.245386                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000655                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010548                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.243858                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098640                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000507                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015985                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.245386                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000655                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010548                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.243858                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098640                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66136.363636                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55337.587747                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56919.663735                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        68025                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60386.316791                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 62829.202256                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 58877.399106                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1707.182330                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3085.436383                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2292.717110                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   917.701863                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6915.069378                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3278.247646                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49542.646977                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53812.993602                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 51877.577896                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66136.363636                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55337.587747                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50215.051394                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        68025                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 60386.316791                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54497.653279                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52947.325469                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66136.363636                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55337.587747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50215.051394                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        68025                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 60386.316791                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54497.653279                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52947.325469                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66554                       # number of writebacks
system.l2c.writebacks::total                    66554                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            36                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                72                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             36                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 72                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            36                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                72                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           11                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6264                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6331                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           20                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6299                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6270                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25197                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5150                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3804                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8954                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          644                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          418                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1062                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63486                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76591                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140077                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           11                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6264                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69817                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6299                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        82861                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165274                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           11                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6264                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69817                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6299                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        82861                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165274                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       591272                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    268680120                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    282241162                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1109289                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    302073229                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    316163964                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1170952288                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51809007                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     38459231                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     90268238                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      6463131                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4201410                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10664541                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2358483918                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3163514299                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5521998217                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       591272                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93252                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    268680120                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2640725080                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1109289                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    302073229                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3479678263                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6692950505                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       591272                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93252                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    268680120                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2640725080                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1109289                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    302073229                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3479678263                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6692950505                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5299167                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12406738561                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2100314                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667521253                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167081659295                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1050184240                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  25918449225                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  26968633465                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5299167                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13456922801                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2100314                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180585970478                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 194050292760                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000507                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000471                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015975                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036566                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000655                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010534                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030688                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017631                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.815777                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.837332                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.824797                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.762130                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.745098                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.755334                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569238                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564930                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.566875                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000507                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000471                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015975                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.245259                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000655                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010534                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.243788                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098597                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000507                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000471                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015975                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.245259                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000655                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010534                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.243788                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098597                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        53752                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42892.739464                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44580.818512                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47955.743610                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50424.874641                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 46471.893003                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.001359                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10110.207939                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.331025                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.917702                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10051.220096                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.940678                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37149.669502                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41303.995234                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 39421.162768                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        53752                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42892.739464                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37823.525502                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47955.743610                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41994.162067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40496.088344                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        53752                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42892.739464                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37823.525502                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47955.743610                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41994.162067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40496.088344                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                5998436                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4575399                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           294209                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3753379                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2912017                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.583878                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 673016                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28669                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8902974                       # DTB read hits
system.cpu0.dtb.read_misses                     28685                       # DTB read misses
system.cpu0.dtb.write_hits                    5134917                       # DTB write hits
system.cpu0.dtb.write_misses                     5599                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1816                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1018                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   297                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      573                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8931659                       # DTB read accesses
system.cpu0.dtb.write_accesses                5140516                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14037891                       # DTB hits
system.cpu0.dtb.misses                          34284                       # DTB misses
system.cpu0.dtb.accesses                     14072175                       # DTB accesses
system.cpu0.itb.inst_hits                     4215172                       # ITB inst hits
system.cpu0.itb.inst_misses                      5141                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1342                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1479                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4220313                       # ITB inst accesses
system.cpu0.itb.hits                          4215172                       # DTB hits
system.cpu0.itb.misses                           5141                       # DTB misses
system.cpu0.itb.accesses                      4220313                       # DTB accesses
system.cpu0.numCycles                        67779631                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11746060                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      31992288                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    5998436                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3585033                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7509031                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1449341                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     60597                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              20626968                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4901                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        47542                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        85433                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          195                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4213506                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               157466                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2283                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41121561                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.005038                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.385329                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                33620027     81.76%     81.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  564307      1.37%     83.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  815894      1.98%     85.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  676094      1.64%     86.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  772709      1.88%     88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  559273      1.36%     90.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  668674      1.63%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  351557      0.85%     92.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3093026      7.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41121561                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.088499                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.472004                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12250531                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20568387                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6812697                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               512769                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                977177                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              933938                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64793                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              39972827                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213127                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                977177                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12817507                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5739937                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      12718334                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6708425                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2160181                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38878118                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1834                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                434730                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1233458                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents              20                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39234243                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175587138                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       175552572                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34566                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30916046                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8318196                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            410984                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        370136                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5348015                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7641998                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5680264                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1129998                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1207028                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36802265                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             895658                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37215076                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            80061                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6274404                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13150521                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        257091                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41121561                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.905002                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.512830                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           25997548     63.22%     63.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5725018     13.92%     77.14% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3161670      7.69%     84.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2471559      6.01%     90.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2093564      5.09%     95.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             947248      2.30%     98.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             486513      1.18%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             185061      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              53380      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41121561                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  25811      2.41%      2.41% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   454      0.04%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                841861     78.66%     81.12% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               202059     18.88%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52149      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22315653     59.96%     60.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46928      0.13%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              6      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           700      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9358800     25.15%     85.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5440823     14.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37215076                       # Type of FU issued
system.cpu0.iq.rate                          0.549060                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1070185                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028757                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         116727564                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         43980171                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34315180                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8451                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4750                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3900                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38228693                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4419                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          306291                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1370106                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2445                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13123                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       533688                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2192694                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5412                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                977177                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4122288                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                97984                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37816345                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            85218                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7641998                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5680264                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571541                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39816                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 2781                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13123                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        149547                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       116915                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              266462                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             36841770                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9218382                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           373306                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       118422                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14612857                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4852888                       # Number of branches executed
system.cpu0.iew.exec_stores                   5394475                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.543552                       # Inst execution rate
system.cpu0.iew.wb_sent                      36648414                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34319080                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18273947                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35157700                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.506333                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.519771                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6086541                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         638567                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           230552                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40144384                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.778927                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.740713                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28480985     70.95%     70.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5711149     14.23%     85.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1913332      4.77%     89.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       974787      2.43%     92.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       784907      1.96%     94.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       524754      1.31%     95.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       386537      0.96%     96.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       218696      0.54%     97.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1149237      2.86%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40144384                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23670531                       # Number of instructions committed
system.cpu0.commit.committedOps              31269562                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11418468                       # Number of memory references committed
system.cpu0.commit.loads                      6271892                       # Number of loads committed
system.cpu0.commit.membars                     229609                       # Number of memory barriers committed
system.cpu0.commit.branches                   4243643                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27627358                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489165                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1149237                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    75500320                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75691570                       # The number of ROB writes
system.cpu0.timesIdled                         360084                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26658070                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2138053443                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23589789                       # Number of Instructions Simulated
system.cpu0.committedOps                     31188820                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23589789                       # Number of Instructions Simulated
system.cpu0.cpi                              2.873261                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.873261                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.348037                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.348037                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               171728285                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34072180                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3295                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     900                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               12998314                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                450987                       # number of misc regfile writes
system.cpu0.icache.replacements                392135                       # number of replacements
system.cpu0.icache.tagsinuse               511.076170                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3790159                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                392647                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.652841                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6563458000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.076170                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.998196                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.998196                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3790159                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3790159                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3790159                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3790159                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3790159                       # number of overall hits
system.cpu0.icache.overall_hits::total        3790159                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       423214                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       423214                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       423214                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        423214                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       423214                       # number of overall misses
system.cpu0.icache.overall_misses::total       423214                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5793685997                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5793685997                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5793685997                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5793685997                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5793685997                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5793685997                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4213373                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4213373                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4213373                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4213373                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4213373                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4213373                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100445                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100445                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100445                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100445                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100445                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100445                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13689.731429                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13689.731429                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2401                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              146                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.445205                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30547                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30547                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30547                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30547                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30547                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30547                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       392667                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       392667                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       392667                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       392667                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       392667                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       392667                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4739152997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4739152997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4739152997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4739152997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4739152997                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4739152997                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7900500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7900500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7900500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7900500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093195                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093195                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093195                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093195                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093195                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093195                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                276137                       # number of replacements
system.cpu0.dcache.tagsinuse               461.136878                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9254727                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                276649                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.452957                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43495000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   461.136878                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.900658                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.900658                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5777010                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5777010                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3157960                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3157960                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139054                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139054                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137010                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137010                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8934970                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8934970                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8934970                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8934970                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392909                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392909                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1581686                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1581686                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8773                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8773                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7509                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7509                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1974595                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1974595                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1974595                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1974595                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5473319500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5473319500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  60618366371                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  60618366371                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     87499000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     87499000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     46786000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     46786000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  66091685871                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  66091685871                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  66091685871                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  66091685871                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6169919                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6169919                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4739646                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4739646                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       147827                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       147827                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144519                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144519                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10909565                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10909565                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10909565                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10909565                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063681                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.063681                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333714                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.333714                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059346                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059346                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051959                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051959                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.180997                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.180997                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.180997                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.180997                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9973.669212                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9973.669212                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6230.656545                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6230.656545                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9022                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         2690                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              641                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             80                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.074883                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    33.625000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256527                       # number of writebacks
system.cpu0.dcache.writebacks::total           256527                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       204116                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       204116                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1451395                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1451395                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          471                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          471                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1655511                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1655511                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1655511                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1655511                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188793                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188793                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130291                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130291                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8302                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8302                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7505                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7505                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       319084                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       319084                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       319084                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       319084                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2371443000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2371443000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4036122491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4036122491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     65692500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     65692500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31776000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31776000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6407565491                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6407565491                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6407565491                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6407565491                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13513513000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13513513000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1180350378                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1180350378                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14693863378                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14693863378                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030599                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030599                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027490                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027490                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056160                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056160                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051931                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051931                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029248                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029248                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029248                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029248                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7912.852325                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7912.852325                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4233.977348                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4233.977348                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9086614                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7469023                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           411441                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             6087298                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5252816                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            86.291422                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 771111                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             43004                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42908069                       # DTB read hits
system.cpu1.dtb.read_misses                     37093                       # DTB read misses
system.cpu1.dtb.write_hits                    6828111                       # DTB write hits
system.cpu1.dtb.write_misses                    10566                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2002                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2479                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   308                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      658                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42945162                       # DTB read accesses
system.cpu1.dtb.write_accesses                6838677                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49736180                       # DTB hits
system.cpu1.dtb.misses                          47659                       # DTB misses
system.cpu1.dtb.accesses                     49783839                       # DTB accesses
system.cpu1.itb.inst_hits                     8400139                       # ITB inst hits
system.cpu1.itb.inst_misses                      5511                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1527                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1516                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8405650                       # ITB inst accesses
system.cpu1.itb.hits                          8400139                       # DTB hits
system.cpu1.itb.misses                           5511                       # DTB misses
system.cpu1.itb.accesses                      8405650                       # DTB accesses
system.cpu1.numCycles                       408778710                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19802343                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      66108771                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9086614                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6023927                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14149480                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3968467                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     63429                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              77260462                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                4652                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42943                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       130023                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          107                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8398224                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               741385                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2977                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         114156752                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.701240                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.046062                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               100014473     87.61%     87.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  796994      0.70%     88.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  939704      0.82%     89.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1889255      1.65%     90.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1506031      1.32%     92.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  574931      0.50%     92.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2131854      1.87%     94.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  410857      0.36%     94.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5892653      5.16%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           114156752                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022229                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.161723                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                21320888                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             76914540                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12790943                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               524179                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2606202                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1106995                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                98605                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              75226388                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               330391                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2606202                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22704982                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31945118                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      40735326                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11835422                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4329702                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              69763643                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                18779                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                668299                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3087296                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             338                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           73772994                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            321197839                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       321138769                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            59070                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49056932                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                24716062                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            445445                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        388435                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7877150                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            13206045                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8148691                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1035919                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1598177                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  63545873                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1154873                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 89160933                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            94911                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       16250476                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     45782181                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        274059                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    114156752                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.781040                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.519067                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           83738528     73.35%     73.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8425243      7.38%     80.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4289902      3.76%     84.49% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3781770      3.31%     87.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10587758      9.27%     97.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1962324      1.72%     98.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1024618      0.90%     99.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             272656      0.24%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              73953      0.06%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      114156752                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  29608      0.38%      0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   998      0.01%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7547947     95.93%     96.32% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               289296      3.68%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           313997      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37637940     42.21%     42.57% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59271      0.07%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 10      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 1      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1510      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43972305     49.32%     91.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7175883      8.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              89160933                       # Type of FU issued
system.cpu1.iq.rate                          0.218115                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7867849                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088243                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         300473883                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         80959646                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     53671142                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14975                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8034                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6858                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96706888                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7897                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          342362                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3450901                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3895                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17010                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1308558                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31911884                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       888923                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2606202                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               24177339                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               360038                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           64805263                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           113338                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             13206045                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8148691                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            865764                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 64951                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3491                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17010                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        203575                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       156879                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              360454                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             86736990                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43278008                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2423943                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104517                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50391999                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7007502                       # Number of branches executed
system.cpu1.iew.exec_stores                   7113991                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.212186                       # Inst execution rate
system.cpu1.iew.wb_sent                      85759457                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     53678000                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 29917161                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53364078                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131313                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.560624                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       16174786                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         880814                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           314330                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    111550550                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.431692                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.400024                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     94808427     84.99%     84.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8234297      7.38%     92.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2114478      1.90%     94.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1250833      1.12%     95.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1245005      1.12%     96.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       571421      0.51%     97.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1000699      0.90%     97.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       504697      0.45%     98.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1820693      1.63%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    111550550                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38064892                       # Number of instructions committed
system.cpu1.commit.committedOps              48155494                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16595277                       # Number of memory references committed
system.cpu1.commit.loads                      9755144                       # Number of loads committed
system.cpu1.commit.membars                     190149                       # Number of memory barriers committed
system.cpu1.commit.branches                   5967637                       # Number of branches committed
system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42690457                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              534638                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1820693                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   173015978                       # The number of ROB reads
system.cpu1.rob.rob_writes                  131360292                       # The number of ROB writes
system.cpu1.timesIdled                        1408221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      294621958                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1796461003                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   37995253                       # Number of Instructions Simulated
system.cpu1.committedOps                     48085855                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             37995253                       # Number of Instructions Simulated
system.cpu1.cpi                             10.758678                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.758678                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092948                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092948                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               388090475                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56232580                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4956                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2332                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               18472941                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                405527                       # number of misc regfile writes
system.cpu1.icache.replacements                597992                       # number of replacements
system.cpu1.icache.tagsinuse               480.750463                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7754983                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                598504                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 12.957278                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74232640500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   480.750463                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.938966                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.938966                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      7754983                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7754983                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7754983                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7754983                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7754983                       # number of overall hits
system.cpu1.icache.overall_hits::total        7754983                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       643188                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       643188                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       643188                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        643188                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       643188                       # number of overall misses
system.cpu1.icache.overall_misses::total       643188                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8662129496                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8662129496                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8662129496                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8662129496                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8662129496                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8662129496                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8398171                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8398171                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8398171                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8398171                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8398171                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8398171                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.076587                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.076587                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.076587                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.076587                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.076587                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.076587                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13467.492391                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13467.492391                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         2692                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              184                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.630435                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        44654                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        44654                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        44654                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        44654                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        44654                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        44654                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       598534                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       598534                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       598534                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       598534                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       598534                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       598534                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7093435997                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7093435997                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7093435997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7093435997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7093435997                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7093435997                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3098500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3098500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071270                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071270                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071270                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.071270                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071270                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.071270                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                360685                       # number of replacements
system.cpu1.dcache.tagsinuse               474.635478                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                12674649                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                361036                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 35.106330                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           70356699000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   474.635478                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.927022                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.927022                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8306809                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8306809                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4139176                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4139176                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        97757                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        97757                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        94875                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        94875                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12445985                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12445985                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12445985                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12445985                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       399972                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       399972                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1557467                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1557467                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14022                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14022                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10623                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10623                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1957439                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1957439                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1957439                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1957439                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6115655000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6115655000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  61487432499                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  61487432499                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    129927000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    129927000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53882500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     53882500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  67603087499                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  67603087499                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  67603087499                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  67603087499                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8706781                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8706781                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5696643                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5696643                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       111779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       111779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105498                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       105498                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14403424                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14403424                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14403424                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14403424                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045938                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045938                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.273401                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.273401                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125444                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125444                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100694                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100694                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135901                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135901                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135901                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135901                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9265.939238                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9265.939238                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5072.248894                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5072.248894                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        30853                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        12637                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3329                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            157                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.267948                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    80.490446                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       324651                       # number of writebacks
system.cpu1.dcache.writebacks::total           324651                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171732                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       171732                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1395801                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1395801                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1444                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1444                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1567533                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1567533                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1567533                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1567533                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       228240                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       228240                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161666                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161666                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12578                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12578                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10618                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10618                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       389906                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       389906                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       389906                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       389906                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2856522500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2856522500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5131083207                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5131083207                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89046000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89046000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32648500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32648500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7987605707                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7987605707                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7987605707                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7987605707                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  35686741676                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  35686741676                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026214                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026214                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028379                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028379                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112526                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112526                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100646                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100646                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027070                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027070                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027070                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027070                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7079.503896                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7079.503896                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3074.825768                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3074.825768                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 540120016505                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   41707                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   48866                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------