path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.827515                       # Number of seconds simulated
sim_ticks                                2827514981500                       # Number of ticks simulated
final_tick                               2827514981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  72486                       # Simulator instruction rate (inst/s)
host_op_rate                                    87933                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1706351372                       # Simulator tick rate (ticks/s)
host_mem_usage                                 605296                       # Number of bytes of host memory used
host_seconds                                  1657.05                       # Real time elapsed on the host
sim_insts                                   120112531                       # Number of instructions simulated
sim_ops                                     145708890                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1298880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1333736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8603840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           183536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           661460                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       448448                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12533612                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1298880                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       183536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1482416                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8896000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8913564                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             22542                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21360                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134435                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2936                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10356                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         7007                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198694                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          139000                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143391                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           724                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              459372                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              471699                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3042898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           158                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               64911                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              233937                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       158601                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4432731                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         459372                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          64911                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             524282                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3146226                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6198                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3152437                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3146226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          724                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             459372                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             477897                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3042898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          158                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              64911                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             233951                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       158601                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7585168                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198695                       # Number of read requests accepted
system.physmem.writeReqs                       143391                       # Number of write requests accepted
system.physmem.readBursts                      198695                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     143391                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12706944                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8926464                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12533676                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8913564                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          66310                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12511                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12409                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13005                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12914                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14688                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12279                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12659                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12545                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12216                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11968                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11724                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10899                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12000                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12901                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12154                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11674                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9120                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9128                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9608                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9301                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8579                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8797                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8898                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8634                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8555                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8430                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8386                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7930                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8700                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8975                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8498                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7937                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    2827514698000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  195029                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 139000                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     63536                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     75209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13408                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10355                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8590                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      6561                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      5366                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4742                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      595                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      246                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      222                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        91952                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.267792                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     133.235046                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     298.839280                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          50134     54.52%     54.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17916     19.48%     74.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5936      6.46%     80.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3412      3.71%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2785      3.03%     87.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1606      1.75%     88.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          997      1.08%     90.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          910      0.99%     91.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8256      8.98%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          91952                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6854                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.967610                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      561.585770                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6852     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6854                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6854                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.349577                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.863128                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.733584                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5532     80.71%     80.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             528      7.70%     88.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             124      1.81%     90.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             151      2.20%     92.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              37      0.54%     92.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             137      2.00%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              51      0.74%     95.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              13      0.19%     95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              30      0.44%     96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.25%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.07%     96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.15%     96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             152      2.22%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.07%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              27      0.39%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.01%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.04%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.04%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.04%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.19%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6854                       # Writes before turning the bus around for reads
system.physmem.totQLat                     6593126991                       # Total ticks spent queuing
system.physmem.totMemAccLat               10315864491                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    992730000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       33207.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51957.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.16                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.43                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.15                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        28.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165438                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80631                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.32                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.80                       # Row buffer hit rate for writes
system.physmem.avgGap                      8265508.38                       # Average gap between requests
system.physmem.pageHitRate                      72.79                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  362418840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  197748375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 803470200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                466981200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184679495520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80961093990                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1625490282750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1892961490875                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.478934                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2704041495487                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94416920000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     29056546513                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  332738280                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  181553625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 745180800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                436823280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184679495520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            80279403345                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1626088257000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1892743451850                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.401821                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2705042490853                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94416920000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     28055246647                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          128                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          192                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          320                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               53824650                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         24914718                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1030270                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            32581460                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               24224214                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            74.349688                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               15556762                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             33886                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    72482                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               72482                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26840                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21370                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        24272                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        48210                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   483.737814                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3068.363590                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        46935     97.36%     97.36% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          960      1.99%     99.35% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          127      0.26%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767          144      0.30%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959           11      0.02%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           24      0.05%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        48210                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        19223                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9427.660612                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7974.318697                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        19122     99.47%     99.47% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           77      0.40%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839           23      0.12%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        19223                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  87324939152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.584645                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.504578                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  87261759152     99.93%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     45052000      0.05%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5      7883000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      5458000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      1586500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11       936000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1172500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1091000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17         1000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  87324939152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5998     77.94%     77.94% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1698     22.06%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7696                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        72482                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        72482                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7696                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7696                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        80178                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24348850                       # DTB read hits
system.cpu0.dtb.read_misses                     61646                       # DTB read misses
system.cpu0.dtb.write_hits                   18136813                       # DTB write hits
system.cpu0.dtb.write_misses                    10836                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3858                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      293                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2461                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      958                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24410496                       # DTB read accesses
system.cpu0.dtb.write_accesses               18147649                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         42485663                       # DTB hits
system.cpu0.dtb.misses                          72482                       # DTB misses
system.cpu0.dtb.accesses                     42558145                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    11063                       # Table walker walks requested
system.cpu0.itb.walker.walksShort               11063                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4358                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6586                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          119                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        10944                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean   511.878655                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  2393.914880                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095        10440     95.39%     95.39% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191          166      1.52%     96.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287          245      2.24%     99.15% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383           55      0.50%     99.65% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479           14      0.13%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575           14      0.13%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959            4      0.04%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::45056-49151            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        10944                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3006                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5482.679017                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2781     92.51%     92.51% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          206      6.85%     99.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           17      0.57%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3006                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  18373803416                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.969102                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.173359                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      568612000      3.09%      3.09% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    17804392916     96.90%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2         690500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         108000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  18373803416                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2539     87.95%     87.95% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          348     12.05%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2887                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11063                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11063                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2887                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2887                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        13950                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    74042794                       # ITB inst hits
system.cpu0.itb.inst_misses                     11063                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2625                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     2170                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                74053857                       # ITB inst accesses
system.cpu0.itb.hits                         74042794                       # DTB hits
system.cpu0.itb.misses                          11063                       # DTB misses
system.cpu0.itb.accesses                     74053857                       # DTB accesses
system.cpu0.numCycles                       211047403                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          21173136                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     200001666                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   53824650                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          39780976                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    180559136                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                5880452                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    163694                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               71518                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       416219                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       467581                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       105314                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 74043107                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               284080                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   5158                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         205896824                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.187509                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.306152                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                98736671     47.95%     47.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                31028549     15.07%     63.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                14918972      7.25%     70.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                61212632     29.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           205896824                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.255036                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.947662                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26444854                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            111284081                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 60438396                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              5147375                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               2582118                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             3181251                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               362597                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             158450982                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4186687                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               2582118                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                35356822                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               13355442                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      85192856                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 56532551                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             12877035                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             141523079                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1131567                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1510730                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                170563                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 62525                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8538727                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          145648252                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            652695637                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       157341344                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            11002                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            133402169                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12246080                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           2729481                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       2582524                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 22941481                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            25362929                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           19747073                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1756360                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2710793                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 138386443                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1765013                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                136262498                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           514521                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       11554986                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23816746                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        127231                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    205896824                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.661800                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       0.962021                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          127277158     61.82%     61.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           34398562     16.71%     78.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           31970025     15.53%     94.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           11080468      5.38%     99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1170573      0.57%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 38      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      205896824                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               11103787     43.69%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    71      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5926512     23.32%     67.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8382229     32.98%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2315      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             91815128     67.38%     67.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult              112435      0.08%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8235      0.01%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            25085333     18.41%     85.88% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           19239052     14.12%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             136262498                       # Type of FU issued
system.cpu0.iq.rate                          0.645649                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   25412599                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.186497                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         504310819                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        151713950                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    132552939                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              38121                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             13270                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses        11439                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             161648054                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  24728                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          380758                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2120893                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2730                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        20852                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1081680                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       121274                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       393141                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               2582118                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1967503                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               225282                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          140361265                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             25362929                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            19747073                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            903285                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 28583                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               172530                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         20852                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        314241                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       420118                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              734359                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            135106830                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             24606381                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1083325                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       209809                       # number of nop insts executed
system.cpu0.iew.exec_refs                    43646202                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                26044471                       # Number of branches executed
system.cpu0.iew.exec_stores                  19039821                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.640173                       # Inst execution rate
system.cpu0.iew.wb_sent                     134503420                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    132564378                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 67577240                       # num instructions producing a value
system.cpu0.iew.wb_consumers                109379746                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.628126                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.617822                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10448394                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1637782                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           672162                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    202592939                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.635502                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.338703                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    141057849     69.63%     69.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     33954375     16.76%     86.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     12905235      6.37%     92.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3389250      1.67%     94.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      4963565      2.45%     96.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      2666475      1.32%     98.20% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1522321      0.75%     98.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       575799      0.28%     99.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1558070      0.77%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    202592939                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           106280740                       # Number of instructions committed
system.cpu0.commit.committedOps             128748309                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      41907429                       # Number of memory references committed
system.cpu0.commit.loads                     23242036                       # Number of loads committed
system.cpu0.commit.membars                     664627                       # Number of memory barriers committed
system.cpu0.commit.branches                  25370057                       # Number of branches committed
system.cpu0.commit.fp_insts                     11428                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                112383608                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             4877012                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        86722676     67.36%     67.36% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult         109969      0.09%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8235      0.01%     67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       23242036     18.05%     85.50% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      18665393     14.50%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        128748309                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1558070                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   316922543                       # The number of ROB reads
system.cpu0.rob.rob_writes                  281696540                       # The number of ROB writes
system.cpu0.timesIdled                         138499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        5150579                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5443982755                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  106128897                       # Number of Instructions Simulated
system.cpu0.committedOps                    128596466                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.988595                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.988595                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.502868                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.502868                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               146588252                       # number of integer regfile reads
system.cpu0.int_regfile_writes               83723999                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     9570                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2716                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                476941595                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                51071402                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              282603834                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1261450                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           749987                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          496.992457                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           38690178                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           750499                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            51.552604                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        426635500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.992457                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970688                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.970688                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         83515372                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        83515372                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     22054482                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22054482                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     15385393                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15385393                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316703                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       316703                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371938                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       371938                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370232                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       370232                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     37439875                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        37439875                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     37756578                       # number of overall hits
system.cpu0.dcache.overall_hits::total       37756578                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       687176                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       687176                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1969830                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1969830                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153892                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       153892                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25692                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        25692                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20263                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20263                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2657006                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2657006                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2810898                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2810898                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  10005125000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  10005125000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36953361360                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  36953361360                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    414445500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    414445500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    533612500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    533612500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       572000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       572000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  46958486360                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  46958486360                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  46958486360                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  46958486360                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     22741658                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     22741658                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17355223                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17355223                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       470595                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       470595                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397630                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       397630                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390495                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       390495                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     40096881                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     40096881                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     40567476                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     40567476                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030217                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.030217                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113501                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.113501                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.327016                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.327016                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064613                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064613                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051891                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051891                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066265                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.066265                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069289                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.069289                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14559.770714                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         1927                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      5691402                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               46                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         211704                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    41.891304                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    26.883772                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       749987                       # number of writebacks
system.cpu0.dcache.writebacks::total           749987                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       277260                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       277260                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1634141                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1634141                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        19045                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        19045                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1911401                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1911401                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1911401                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1911401                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       409916                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       409916                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       335689                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       335689                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107270                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       107270                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6647                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6647                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20263                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20263                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       745605                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       745605                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       852875                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       852875                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31809                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31809                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60302                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60302                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5149096500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149096500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7778892390                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7778892390                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1793614000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1793614000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108165500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108165500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    513361500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    513361500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       560000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       560000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12927988890                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  12927988890                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14721602890                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  14721602890                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6623643500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6623643500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5395209000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5395209000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12018852500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12018852500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.018025                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.018025                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019342                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019342                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.227945                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227945                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016717                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016717                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051891                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051891                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018595                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.018595                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.021024                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.021024                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17261.149512                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17261.149512                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208231.742589                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208231.742589                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189352.086477                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189352.086477                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199311.009585                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199311.009585                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1312325                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.728748                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           72670068                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1312837                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            55.353458                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       8207375500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728748                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999470                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999470                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          135                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        149391678                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       149391678                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     72670068                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       72670068                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     72670068                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        72670068                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     72670068                       # number of overall hits
system.cpu0.icache.overall_hits::total       72670068                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1369337                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1369337                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1369337                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1369337                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1369337                       # number of overall misses
system.cpu0.icache.overall_misses::total      1369337                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14942606327                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14942606327                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14942606327                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14942606327                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14942606327                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14942606327                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     74039405                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     74039405                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     74039405                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     74039405                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     74039405                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     74039405                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018495                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.018495                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018495                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.018495                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018495                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.018495                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10912.292830                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10912.292830                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10912.292830                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10912.292830                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10912.292830                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10912.292830                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      2029991                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1804                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           126413                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.058404                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   120.266667                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1312325                       # number of writebacks
system.cpu0.icache.writebacks::total          1312325                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56467                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        56467                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        56467                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        56467                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        56467                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        56467                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1312870                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1312870                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1312870                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1312870                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1312870                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1312870                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13422835685                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  13422835685                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13422835685                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  13422835685                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13422835685                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  13422835685                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420651998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    420651998                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017732                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.017732                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.017732                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1922264                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1925121                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         2600                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       245295                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          283525                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16106.133558                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3424599                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          299662                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           11.428206                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14666.612197                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    13.987362                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.024801                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1424.509198                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.895179                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000854                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000063                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.086945                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983040                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          969                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15162                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           27                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          307                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          430                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          205                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          496                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4568                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7930                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2049                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059143                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.925415                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        69529329                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       69529329                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        59791                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        14320                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         74111                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       505100                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       505100                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1523954                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1523954                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       205881                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       205881                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1258248                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1258248                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       426377                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       426377                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        59791                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        14320                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1258248                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       632258                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1964617                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        59791                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        14320                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1258248                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       632258                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1964617                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          340                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          103                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          443                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55446                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55446                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20261                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20261                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        74580                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        74580                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        54597                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        54597                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        97319                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        97319                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          340                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          103                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        54597                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       171899                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       226939                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          340                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          103                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        54597                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       171899                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       226939                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     12449000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2707500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     15156500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    180664000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    180664000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     42645500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     42645500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       540498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       540498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   4119133500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   4119133500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3780116498                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3780116498                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3430160498                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3430160498                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     12449000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2707500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3780116498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   7549293998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  11344566996                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     12449000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2707500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3780116498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   7549293998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  11344566996                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        60131                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        14423                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        74554                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       505100                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       505100                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1523954                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1523954                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55447                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55447                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20261                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20261                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280461                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       280461                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1312845                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1312845                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       523696                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       523696                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        60131                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        14423                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1312845                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       804157                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2191556                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        60131                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        14423                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1312845                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       804157                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2191556                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.005942                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.265919                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.265919                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.041587                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.041587                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.185831                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.185831                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.041587                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.213763                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.103552                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.041587                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.213763                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.103552                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34213.318284                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3258.377520                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3258.377520                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2104.807265                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2104.807265                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       270249                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       270249                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55231.074014                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55231.074014                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69236.707108                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69236.707108                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35246.565398                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35246.565398                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69236.707108                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43917.032665                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 49989.499363                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69236.707108                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43917.032665                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 49989.499363                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           34                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       233393                       # number of writebacks
system.cpu0.l2cache.writebacks::total          233393                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        33060                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        33060                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           43                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           43                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          786                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          786                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           43                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        33846                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        33890                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           43                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        33846                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        33890                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          339                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          103                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          442                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       260432                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       260432                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55446                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55446                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20261                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20261                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41520                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41520                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        54554                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        54554                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        96533                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        96533                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          339                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          103                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        54554                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       138053                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       193049                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          339                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          103                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        54554                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       138053                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       260432                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       453481                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31809                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34813                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60302                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63306                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12489000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  22074812822                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  22074812822                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1462138500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1462138500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    360190499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    360190499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       468498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       468498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2502746000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2502746000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3450718498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3450718498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2793545998                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2793545998                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3450718498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5296291998                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8759499496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3450718498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5296291998                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  22074812822                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  30834312318                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6368846000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6766966500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5178267462                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5178267462                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11547113462                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11945233962                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.005929                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148042                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148042                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041554                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184330                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184330                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171674                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.088088                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171674                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.206922                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       234249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       234249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      4279317                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2162325                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        33276                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       327449                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       323077                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4372                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        121937                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2006842                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28493                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28493                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       739077                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1523954                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       209281                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       317808                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        85654                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42585                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       113145                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       298662                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       295385                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1312870                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       595361                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3427                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3918545                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2723305                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        31953                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       129711                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6803514                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    166426752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103211806                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        57692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       240524                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         269936774                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1020233                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3250109                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.119815                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.328862                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2865068     88.15%     88.15% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            380669     11.71%     99.87% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4372      0.13%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3250109                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    4279335949                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113715191                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1972888832                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1291542228                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     17537485                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     69622914                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                4034173                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2335207                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           244345                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2038897                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1508183                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            73.970534                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 793679                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              5620                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    15746                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               15746                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8388                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3065                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore         4293                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        11453                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   595.826421                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3233.762475                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095        10927     95.41%     95.41% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191          176      1.54%     96.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287          209      1.82%     98.77% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383           35      0.31%     99.07% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479           13      0.11%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575           23      0.20%     99.39% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671            3      0.03%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767           42      0.37%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863           20      0.17%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959            4      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        11453                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         3271                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7344.366479                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         2791     85.33%     85.33% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          443     13.54%     98.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151           31      0.95%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         3271                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  78450006060                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.184600                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.390418                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    63997466940     81.58%     81.58% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    14437247120     18.40%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2       10341500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3        2133500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4         875500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5         457000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6         962000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7          87500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8          30500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9          79000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10         14000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11         48000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12         54000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13         17000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14         17500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15        175000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  78450006060                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1233     71.11%     71.11% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          501     28.89%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1734                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15746                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15746                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1734                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1734                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        17480                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3564995                       # DTB read hits
system.cpu1.dtb.read_misses                     13832                       # DTB read misses
system.cpu1.dtb.write_hits                    3032176                       # DTB write hits
system.cpu1.dtb.write_misses                     1914                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1668                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       34                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   253                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      227                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3578827                       # DTB read accesses
system.cpu1.dtb.write_accesses                3034090                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6597171                       # DTB hits
system.cpu1.dtb.misses                          15746                       # DTB misses
system.cpu1.dtb.accesses                      6612917                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     6257                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                6257                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         3920                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2276                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore           61                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         6196                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   206.181407                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  1542.947362                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095         6076     98.06%     98.06% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191           60      0.97%     99.03% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287           39      0.63%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383            7      0.11%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479            5      0.08%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575            4      0.06%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671            4      0.06%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-36863            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         6196                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          896                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5713.555798                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          197     21.99%     21.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383          650     72.54%     94.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575           13      1.45%     95.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           24      2.68%     98.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959            5      0.56%     99.22% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            2      0.22%     99.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.45%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.11%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          896                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  13992892620                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.945402                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.227238                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0      764122764      5.46%      5.46% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    13228629356     94.54%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2         140500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  13992892620                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          692     82.87%     82.87% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          143     17.13%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          835                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6257                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6257                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          835                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          835                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         7092                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     7247489                       # ITB inst hits
system.cpu1.itb.inst_misses                      6257                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     899                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      342                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7253746                       # ITB inst accesses
system.cpu1.itb.hits                          7247489                       # DTB hits
system.cpu1.itb.misses                           6257                       # DTB misses
system.cpu1.itb.accesses                      7253746                       # DTB accesses
system.cpu1.numCycles                        32825676                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           8001289                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      21471337                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    4034173                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           2301862                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     23036367                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 699414                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     85773                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               29291                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       185520                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       275269                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles        17468                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7247139                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               103562                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2283                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          31980684                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.819942                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.194084                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                19847655     62.06%     62.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 4393311     13.74%     75.80% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1390148      4.35%     80.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 6349570     19.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            31980684                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.122897                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.654102                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 6559156                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             16660335                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  7594258                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               935690                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                231245                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              620374                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               121000                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              20120105                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               926045                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                231245                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 7803762                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2337008                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      11658570                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  7267589                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2682510                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              19097640                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               153089                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               210195                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 28229                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 13307                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1810658                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           18872486                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             89304984                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        22006430                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups                6                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             16903103                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1969383                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            373801                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        306197                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2490350                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             3798024                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            3334408                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           558239                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          459403                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  18396455                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             514218                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 18243143                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            80370                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1798248                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      4138161                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         41963                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     31980684                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.570443                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.921832                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           21156406     66.15%     66.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            5430198     16.98%     83.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3595564     11.24%     94.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            1572256      4.92%     99.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             226251      0.71%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       31980684                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                1148262     27.95%     27.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   668      0.02%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1340987     32.64%     60.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1618003     39.39%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               24      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             11255159     61.70%     61.70% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               26433      0.14%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3176      0.02%     61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             3744432     20.53%     82.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            3213919     17.62%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              18243143                       # Type of FU issued
system.cpu1.iq.rate                          0.555758                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4107920                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.225176                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          72655260                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         20717149                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     17851675                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              22351039                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           72767                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       344909                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          550                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         8264                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       279088                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        35940                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        54533                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                231245                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 541574                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               157299                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           18927437                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              3798024                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             3334408                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            272337                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  6587                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               145035                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          8264                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         30633                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       103644                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              134277                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             18042171                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              3670535                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           185229                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        16764                       # number of nop insts executed
system.cpu1.iew.exec_refs                     6830795                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 2603132                       # Number of branches executed
system.cpu1.iew.exec_stores                   3160260                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.549636                       # Inst execution rate
system.cpu1.iew.wb_sent                      17938795                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     17851675                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  8886835                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 13789507                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.543833                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.644464                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        1628624                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         472255                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           125883                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     31615084                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.541371                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.295044                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     23337715     73.82%     73.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      4942860     15.63%     89.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1433345      4.53%     93.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       542164      1.71%     95.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       455708      1.44%     97.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       302171      0.96%     98.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       181914      0.58%     98.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        99381      0.31%     98.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       319826      1.01%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     31615084                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            13986698                       # Number of instructions committed
system.cpu1.commit.committedOps              17115488                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       6508435                       # Number of memory references committed
system.cpu1.commit.loads                      3453115                       # Number of loads committed
system.cpu1.commit.membars                     191139                       # Number of memory barriers committed
system.cpu1.commit.branches                   2479082                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 15267561                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              414980                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        10578262     61.81%     61.81% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          25615      0.15%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3176      0.02%     61.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.97% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        3453115     20.18%     82.15% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       3055320     17.85%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         17115488                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               319826                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                    49145756                       # The number of ROB reads
system.cpu1.rob.rob_writes                   37850174                       # The number of ROB writes
system.cpu1.timesIdled                          55034                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         844992                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5621633430                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   13983634                       # Number of Instructions Simulated
system.cpu1.committedOps                     17112424                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.347435                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.347435                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.425997                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.425997                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                20215691                       # number of integer regfile reads
system.cpu1.int_regfile_writes               11658166                       # number of integer regfile writes
system.cpu1.cc_regfile_reads                 64782198                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                 5550427                       # number of cc regfile writes
system.cpu1.misc_regfile_reads               46731168                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                350339                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements           150744                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.669505                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            5845075                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           151083                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.687840                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104824569000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.669505                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921230                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.921230                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          339                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          328                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.662109                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12896760                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12896760                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3092594                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3092594                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2524465                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2524465                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42426                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        42426                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70168                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        70168                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61430                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        61430                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5617059                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5617059                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5659485                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5659485                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       178952                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       178952                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       316827                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       316827                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23604                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        23604                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17348                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17348                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23299                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23299                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       495779                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        495779                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       519383                       # number of overall misses
system.cpu1.dcache.overall_misses::total       519383                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3441746500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3441746500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11862734947                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  11862734947                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    362002500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    362002500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    631001500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    631001500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1169000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1169000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  15304481447                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  15304481447                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  15304481447                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  15304481447                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3271546                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3271546                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2841292                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2841292                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66030                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        66030                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87516                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        87516                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84729                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        84729                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6112838                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6112838                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6178868                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6178868                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.054700                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.054700                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111508                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.111508                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.357474                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.357474                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.198227                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.198227                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274983                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274983                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081105                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.081105                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084058                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.084058                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          358                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1808008                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               31                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          30216                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.548387                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    59.836113                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       150744                       # number of writebacks
system.cpu1.dcache.writebacks::total           150744                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62223                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        62223                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       237836                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       237836                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12586                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12586                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       300059                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       300059                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       300059                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       300059                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116729                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       116729                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78991                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        78991                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        22881                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        22881                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4762                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4762                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23299                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23299                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       195720                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       195720                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       218601                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       218601                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3069                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3069                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5480                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5480                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1778715000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1778715000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2939877456                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2939877456                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    425185000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    425185000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     98534500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     98534500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    607713500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    607713500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1158000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1158000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4718592456                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4718592456                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5143777456                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5143777456                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    437774500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    437774500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    301405500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    301405500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    739180000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    739180000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035680                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035680                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027801                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027801                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.346524                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.346524                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054413                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054413                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274983                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274983                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032018                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.032018                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035379                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035379                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18582.448320                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 20691.831163                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20691.831163                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26083.243916                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26083.243916                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24108.892581                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24108.892581                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23530.438818                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23530.438818                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142644.020854                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142644.020854                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125012.650353                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125012.650353                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134886.861314                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           551908                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.384443                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6675021                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           552420                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            12.083236                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      79408503500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.384443                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975360                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975360                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         15046317                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        15046317                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      6675021                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6675021                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6675021                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6675021                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6675021                       # number of overall hits
system.cpu1.icache.overall_hits::total        6675021                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       571924                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       571924                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       571924                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        571924                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       571924                       # number of overall misses
system.cpu1.icache.overall_misses::total       571924                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5247903529                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5247903529                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5247903529                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5247903529                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5247903529                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5247903529                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7246945                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7246945                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7246945                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7246945                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7246945                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7246945                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.078919                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.078919                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.078919                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.078919                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.078919                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.078919                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9175.875692                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9175.875692                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9175.875692                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9175.875692                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9175.875692                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9175.875692                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       518390                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          438                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            40965                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.654461                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          146                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       551908                       # number of writebacks
system.cpu1.icache.writebacks::total           551908                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19497                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        19497                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        19497                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        19497                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        19497                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        19497                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       552427                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       552427                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       552427                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       552427                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       552427                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       552427                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          103                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          103                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4796273338                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4796273338                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4796273338                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4796273338                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4796273338                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4796273338                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14117999                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14117999                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.076229                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.076229                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.076229                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8682.184864                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8682.184864                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8682.184864                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       114901                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       115599                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          633                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        47913                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           38341                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15301.887572                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1226523                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           53480                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           22.934237                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14854.525753                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     7.568708                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     3.883063                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   435.910048                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.906648                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000462                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000237                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026606                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.933953                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          923                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14155                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          616                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          296                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           33                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          802                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2695                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10658                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.056335                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.863953                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        24288275                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       24288275                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        12056                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         6824                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         18880                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        92484                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        92484                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       598066                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       598066                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        16973                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        16973                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       541415                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       541415                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        78226                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        78226                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        12056                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         6824                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       541415                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        95199                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         655494                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        12056                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6824                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       541415                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        95199                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        655494                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          455                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          292                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          747                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29477                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29477                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23299                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23299                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33181                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        33181                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        11002                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        11002                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        66142                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        66142                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          455                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          292                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        11002                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        99323                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       111072                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          455                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          292                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        11002                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        99323                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       111072                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10030500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5845500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     15876000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     63278000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     63278000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     61670500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     61670500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1141500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1141500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1906360500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1906360500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    658538999                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    658538999                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1560865998                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1560865998                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10030500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5845500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    658538999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3467226498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4141641497                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10030500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5845500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    658538999                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3467226498                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4141641497                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12511                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7116                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        19627                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        92484                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        92484                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       598066                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       598066                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29477                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29477                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23299                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23299                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50154                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50154                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       552417                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       552417                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       144368                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       144368                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        12511                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7116                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       552417                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       194522                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       766566                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        12511                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7116                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       552417                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       194522                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       766566                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.038060                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.661582                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.661582                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019916                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019916                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.458149                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.458149                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019916                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.510600                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.144896                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019916                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.510600                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.144896                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21253.012048                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2146.690640                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2146.690640                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2646.916177                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2646.916177                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 57453.376933                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 57453.376933                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59856.298764                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59856.298764                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23598.711832                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23598.711832                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59856.298764                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34908.596176                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 37287.898813                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59856.298764                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34908.596176                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 37287.898813                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        31325                       # number of writebacks
system.cpu1.l2cache.writebacks::total           31325                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           17                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total           18                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1215                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         1215                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           35                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           35                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           17                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1250                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         1273                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           17                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1250                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         1273                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          454                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          275                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          729                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        21206                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        21206                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29477                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29477                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23299                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23299                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31966                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        31966                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10997                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10997                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66107                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66107                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          454                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          275                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10997                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        98073                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       109799                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          454                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          275                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10997                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98073                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        21206                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       131005                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3069                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3172                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5480                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5583                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11270000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1346298482                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1346298482                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    600399000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    600399000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    432262000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    432262000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1075500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1075500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1610738500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1610738500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    592445999                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    592445999                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1162092498                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1162092498                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    592445999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2772830998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3376546997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    592445999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2772830998                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1346298482                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4722845479                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    413019000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    426364000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    283076496                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    283076496                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    696095496                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    709440496                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.037143                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637357                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637357                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019907                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.457906                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.457906                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.504174                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.143235                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.504174                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.170899                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15459.533608                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63486.677450                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20368.388913                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20368.388913                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18552.813425                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18552.813425                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      1510050                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       763127                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12108                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       172945                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       171137                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1808                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         26162                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       760461                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2411                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2411                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       125070                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       598066                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        92914                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        26023                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70036                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41455                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85358                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57012                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        54811                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       552427                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       220569                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           25                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1646728                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       729194                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        15588                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27029                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2418539                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     70023728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24695290                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        28464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50044                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          94797526                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     371473                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1121639                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.173444                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.382865                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            928905     82.82%     82.82% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            190926     17.02%     99.84% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1808      0.16%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1121639                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1469339490                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79587436                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    828867751                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    323642126                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      8481980                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     14527980                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31018                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31018                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180884                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40431500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               111500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                31500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6146000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            34110000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           186335542                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36458                       # number of replacements
system.iocache.tags.tagsinuse               14.549511                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         256320229000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.549511                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.909344                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.909344                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          252                       # number of overall misses
system.iocache.overall_misses::total              252                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32965876                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32965876                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4737835666                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4737835666                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32965876                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32965876                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32965876                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32965876                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 130816.968254                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130816.968254                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130816.968254                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130816.968254                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130816.968254                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           713                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   91                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.835165                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          252                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20365876                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20365876                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2926635666                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2926635666                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     20365876                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     20365876                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     20365876                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     20365876                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80816.968254                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80816.968254                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   131293                       # number of replacements
system.l2c.tags.tagsinuse                63152.978828                       # Cycle average of tags in use
system.l2c.tags.total_refs                     442353                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   195350                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.264413                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13838.997413                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    18.349981                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.060621                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8045.868087                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2735.320064                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33659.346102                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     6.413836                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909660                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1799.024775                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      856.706825                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2190.981465                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.211166                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000280                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.122770                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.041738                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.513601                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000098                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.027451                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013072                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.033432                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.963638                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        30319                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           26                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        33712                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          117                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         6038                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        24164                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          622                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4436                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        28625                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.462631                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000397                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.514404                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6100734                       # Number of tag accesses
system.l2c.tags.data_accesses                 6100734                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       264718                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          264718                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32582                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2383                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               34965                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2172                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           943                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3115                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4024                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1119                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5143                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          183                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           74                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        34982                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        48772                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46702                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           30                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           15                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         8142                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         6412                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3079                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           148391                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           183                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            74                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               34982                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               52796                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46702                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            30                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            15                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                8142                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                7531                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3079                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  153534                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          183                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           74                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              34982                       # number of overall hits
system.l2c.overall_hits::cpu0.data              52796                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46702                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           30                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           15                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               8142                       # number of overall hits
system.l2c.overall_hits::cpu1.data               7531                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3079                       # number of overall hits
system.l2c.overall_hits::total                 153534                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9630                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2300                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11930                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          789                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1228                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2017                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11769                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9002                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              20771                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           32                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19572                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9277                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134592                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2853                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1343                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         7007                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         174687                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19572                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21046                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134592                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2853                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10345                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         7007                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195458                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19572                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21046                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134592                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2853                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10345                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         7007                       # number of overall misses
system.l2c.overall_misses::total               195458                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     24914000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5940500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     30854500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4111000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2758000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      6869000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1778582000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1203023000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2981605000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      4841000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       388000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2598359001                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1294263000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  21242920310                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       929500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       133000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    386572500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    186522500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1271879384                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  26986808195                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      4841000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       388000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2598359001                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3072845000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  21242920310                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       929500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    386572500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1389545500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1271879384                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     29968413195                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      4841000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       388000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2598359001                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3072845000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  21242920310                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       929500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    386572500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1389545500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1271879384                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    29968413195                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       264718                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       264718                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        42212                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4683                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           46895                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2961                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2171                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5132                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15793                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10121                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25914                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          215                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           77                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        54554                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        58049                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       181294                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           37                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           16                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        10995                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         7755                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        10086                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       323078                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          215                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           77                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           54554                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           73842                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       181294                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           37                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           16                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           10995                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           17876                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        10086                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              348992                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          215                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           77                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          54554                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          73842                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       181294                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           37                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           16                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          10995                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          17876                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        10086                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             348992                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.228134                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.491138                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.254398                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.266464                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.565638                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.393024                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.745204                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.889438                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.801536                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.358764                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159813                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.259482                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173179                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.540696                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.358764                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.285014                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.259482                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.578709                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.560064                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.358764                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.285014                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.259482                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.578709                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.560064                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2587.123572                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2582.826087                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2586.295054                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5210.392902                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2245.928339                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3405.552801                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151124.309627                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133639.524550                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 143546.531221                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132758.992489                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139513.096906                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135496.845426                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138884.959047                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 154486.642939                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 132758.992489                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 146006.129431                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135496.845426                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134320.492992                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 153324.055270                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 132758.992489                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 146006.129431                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135496.845426                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134320.492992                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 153324.055270                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               244                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     81.333333                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102794                       # number of writebacks
system.l2c.writebacks::total                   102794                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           23                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            8                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           31                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 31                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                31                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3318                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3318                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9630                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2300                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11930                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          789                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1228                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2017                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11769                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9002                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         20771                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19549                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9277                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134592                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2845                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1343                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         7007                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       174656                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19549                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21046                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134592                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2845                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10345                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         7007                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195427                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19549                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21046                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134592                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2845                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10345                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         7007                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195427                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31809                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3066                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        37982                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30904                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60302                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5477                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        68886                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    726468500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    172914500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    899383000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     61180001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     94048000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    155228001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1660892000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1113003000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2773895000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      4521000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       358000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2400281501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1201493000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  19897000310                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       859500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker       123000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    357493000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    173092500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1201809384                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  25237031195                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      4521000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       358000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2400281501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2862385000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  19897000310                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       859500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    357493000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1286095500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1201809384                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  28010926195                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      4521000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       358000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2400281501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2862385000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  19897000310                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       859500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    357493000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1286095500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1201809384                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  28010926195                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    344048000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5796274000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11490000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    357780500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6509592500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4693778538                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    242067504                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4935846042                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    344048000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10490052538                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11490000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    599848004                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11445438542                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.228134                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.491138                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.254398                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.266464                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.565638                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.393024                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.745204                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.889438                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.801536                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159813                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173179                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.540600                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.285014                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.578709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.559976                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.285014                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.578709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.559976                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75438.058152                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75180.217391                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75388.348701                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77541.192649                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76586.319218                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76959.841844                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141124.309627                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123639.524550                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 133546.531221                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129513.096906                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128884.959047                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144495.643980                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136006.129431                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.492992                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 143331.915216                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136006.129431                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.492992                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 143331.915216                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               37982                       # Transaction distribution
system.membus.trans_dist::ReadResp             212889                       # Transaction distribution
system.membus.trans_dist::WriteReq              30904                       # Transaction distribution
system.membus.trans_dist::WriteResp             30904                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       139000                       # Transaction distribution
system.membus.trans_dist::CleanEvict            16061                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            72768                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40424                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14027                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40474                       # Transaction distribution
system.membus.trans_dist::ReadExResp            20691                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        174908                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13686                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       672318                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       793976                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 902910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27372                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19129032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19319536                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21637680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           119522                       # Total snoops (count)
system.membus.snoop_fanout::samples            588990                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  588990    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              588990                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81993500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11365991                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1011151356                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1153249220                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64060493                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       995943                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       537996                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       143832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          21510                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        20627                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          883                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              37985                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            476927                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30904                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30904                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       403719                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           92623                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          107653                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43539                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         151192                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50791                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50791                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       438958                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1238290                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       270024                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1508314                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35030546                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4521886                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39552432                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          444179                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           913848                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.335282                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.474132                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 608334     66.57%     66.57% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 304631     33.33%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    883      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             913848                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          880459353                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           356618                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         654259891                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         211427270                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1860                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2725                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------