path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.114023                       # Number of seconds simulated
sim_ticks                                1114022852000                       # Number of ticks simulated
final_tick                               1114022852000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  79652                       # Simulator instruction rate (inst/s)
host_op_rate                                   102538                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1440387686                       # Simulator tick rate (ticks/s)
host_mem_usage                                 404604                       # Number of bytes of host memory used
host_seconds                                   773.42                       # Real time elapsed on the host
sim_insts                                    61604368                       # Number of instructions simulated
sim_ops                                      79304455                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         1024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           409408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4367220                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           406208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5247536                       # Number of bytes read from this memory
system.physmem.bytes_read::total             59191204                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       409408                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       406208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          815616                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4263872                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7291216                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6094848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           16                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6397                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68310                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6347                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82019                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6257953                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66623                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823459                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43768208                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           919                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           115                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              367504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3920225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           804                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              364632                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4710438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53132845                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         367504                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         364632                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             732136                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3827455                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              15260                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2702228                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6544943                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3827455                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43768208                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          919                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          115                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             367504                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3935485                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          804                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             364632                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7412667                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               59677788                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6257953                       # Total number of read requests seen
system.physmem.writeReqs                       823459                       # Total number of write requests seen
system.physmem.cpureqs                         242171                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    400508992                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52701376                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               59191204                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7291216                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      127                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              12548                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                391121                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                391049                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                391102                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                391240                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                391825                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                391535                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                391243                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                391065                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                391488                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                391482                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               390728                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               390299                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               390904                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               390678                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               391045                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               391022                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 49919                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 49928                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 51967                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51963                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 52290                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51965                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51872                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51692                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51908                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51949                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51308                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51011                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51439                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51134                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51585                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51529                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32580                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1114021721000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                     105                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6094848                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  163000                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 756836                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  66623                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    508306                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    436400                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    409055                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1494610                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1111724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1109849                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1096192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      9300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      6855                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     11963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    16960                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    11777                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     8816                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     8727                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    12128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     5024                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3064                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32793                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32597                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        38811                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11677.106800                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     598.829081                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   25969.144286                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95          10478     27.00%     27.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159         4256     10.97%     37.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223         2718      7.00%     44.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287         2024      5.22%     50.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351         1422      3.66%     53.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415         1213      3.13%     56.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479          997      2.57%     59.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543          905      2.33%     61.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607          654      1.69%     63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671          573      1.48%     65.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735          456      1.17%     66.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799          470      1.21%     67.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863          308      0.79%     68.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927          261      0.67%     68.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991          192      0.49%     69.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055          284      0.73%     70.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119          136      0.35%     70.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183          144      0.37%     70.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247          111      0.29%     71.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311          147      0.38%     71.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375           83      0.21%     71.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439          412      1.06%     72.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503         1956      5.04%     77.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567          510      1.31%     79.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631           94      0.24%     79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695          178      0.46%     79.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759           53      0.14%     79.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823          122      0.31%     80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887           38      0.10%     80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951           83      0.21%     80.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015           40      0.10%     80.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079           68      0.18%     80.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143           23      0.06%     80.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207           47      0.12%     81.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271           17      0.04%     81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335           43      0.11%     81.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399           13      0.03%     81.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463           28      0.07%     81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527           13      0.03%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591           25      0.06%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655           10      0.03%     81.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719           18      0.05%     81.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783            7      0.02%     81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847           19      0.05%     81.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911            4      0.01%     81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975           20      0.05%     81.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039            6      0.02%     81.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103           20      0.05%     81.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167            6      0.02%     81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231            9      0.02%     81.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295            7      0.02%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359           18      0.05%     81.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423            3      0.01%     81.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487           11      0.03%     81.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551            6      0.02%     81.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615           12      0.03%     81.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679            6      0.02%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743            2      0.01%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807            6      0.02%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871            7      0.02%     81.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935            5      0.01%     81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999           10      0.03%     81.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063            2      0.01%     81.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127           40      0.10%     82.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191            1      0.00%     82.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255            7      0.02%     82.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319            2      0.01%     82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383            5      0.01%     82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447            3      0.01%     82.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511            4      0.01%     82.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575            3      0.01%     82.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4639            9      0.02%     82.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703            1      0.00%     82.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767            2      0.01%     82.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831            2      0.01%     82.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895            2      0.01%     82.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959            2      0.01%     82.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023            5      0.01%     82.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5087            1      0.00%     82.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151            7      0.02%     82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215            4      0.01%     82.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279            2      0.01%     82.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343            2      0.01%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407            2      0.01%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471            2      0.01%     82.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535            2      0.01%     82.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5599            3      0.01%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5663            3      0.01%     82.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5727            2      0.01%     82.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5791            1      0.00%     82.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5855            1      0.00%     82.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919            2      0.01%     82.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5983            2      0.01%     82.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047            3      0.01%     82.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111            2      0.01%     82.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175            5      0.01%     82.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6239            3      0.01%     82.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303            4      0.01%     82.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6367            2      0.01%     82.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6431            4      0.01%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495            1      0.00%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559            1      0.00%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6623            1      0.00%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6687            2      0.01%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751            2      0.01%     82.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815           14      0.04%     82.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879            3      0.01%     82.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943            3      0.01%     82.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7007            2      0.01%     82.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071            2      0.01%     82.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199            3      0.01%     82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7263            1      0.00%     82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7327            1      0.00%     82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455            6      0.02%     82.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7519            1      0.00%     82.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583            4      0.01%     82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711            6      0.02%     82.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7775            2      0.01%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839            2      0.01%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903            2      0.01%     82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967            7      0.02%     82.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031            1      0.00%     82.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095            7      0.02%     82.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159            4      0.01%     82.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223          316      0.81%     83.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8287            1      0.00%     83.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8991            2      0.01%     83.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9247            5      0.01%     83.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9375            1      0.00%     83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9503            1      0.00%     83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9695            1      0.00%     83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-10015            2      0.01%     83.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271           15      0.04%     83.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10399            1      0.00%     83.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10527            1      0.00%     83.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10783            1      0.00%     83.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11039            3      0.01%     83.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11295            3      0.01%     83.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11551            1      0.00%     83.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11807            2      0.01%     83.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12063            1      0.00%     83.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319            5      0.01%     83.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12575            1      0.00%     83.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12831            2      0.01%     83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12895            1      0.00%     83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13087            1      0.00%     83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343            2      0.01%     83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13535            1      0.00%     83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13599            1      0.00%     83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14367            4      0.01%     83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15135            3      0.01%     83.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15391            1      0.00%     83.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15455            1      0.00%     83.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15775            1      0.00%     83.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16671            3      0.01%     83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16927            1      0.00%     83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17183            1      0.00%     83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17247            1      0.00%     83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17375            1      0.00%     83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17439            2      0.01%     83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17695            2      0.01%     83.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17759            1      0.00%     83.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17984-18015            1      0.00%     83.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18207            3      0.01%     83.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463            1      0.00%     83.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18591            1      0.00%     83.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18719            2      0.01%     83.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18975            2      0.01%     83.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19231            1      0.00%     83.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19487            4      0.01%     83.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19584-19615            1      0.00%     83.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19999            3      0.01%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20096-20127            1      0.00%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20255            1      0.00%     83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20511           12      0.03%     83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20767            1      0.00%     83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21279            1      0.00%     83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21535            2      0.01%     83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21791            1      0.00%     83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21952-21983            2      0.01%     83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22047            1      0.00%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22559            4      0.01%     83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22687            1      0.00%     83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22815            3      0.01%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23327            1      0.00%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23583            1      0.00%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24000-24031            1      0.00%     83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24095            2      0.01%     83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24192-24223            1      0.00%     83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24351            1      0.00%     83.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24607            2      0.01%     83.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24704-24735            2      0.01%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25375            1      0.00%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25408-25439            1      0.00%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25631            2      0.01%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25887            1      0.00%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26048-26079            1      0.00%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26143            4      0.01%     83.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26335            1      0.00%     83.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26399            1      0.00%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26655            1      0.00%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27167            3      0.01%     83.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27423            2      0.01%     83.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27487            1      0.00%     83.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27679            2      0.01%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27935            1      0.00%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28447            1      0.00%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28703            1      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28959            1      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29471            2      0.01%     83.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30495            1      0.00%     83.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30528-30559            1      0.00%     83.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30751            3      0.01%     83.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30912-30943            1      0.00%     83.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31007            2      0.01%     83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31071            1      0.00%     83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31775            2      0.01%     83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31808-31839            1      0.00%     83.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32223            1      0.00%     83.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32287            1      0.00%     83.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32415            1      0.00%     83.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32543            2      0.01%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32799            2      0.01%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33311            1      0.00%     83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33375            1      0.00%     83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33567            5      0.01%     83.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33631            2      0.01%     83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33695            3      0.01%     83.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33759            2      0.01%     83.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823           43      0.11%     83.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34496-34527            1      0.00%     83.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34847            2      0.01%     83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35136-35167            1      0.00%     83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35871            1      0.00%     83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36127            1      0.00%     83.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36288-36319            1      0.00%     83.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36383            1      0.00%     83.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37824-37855            1      0.00%     83.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37919            1      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38175            1      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39232-39263            1      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39455            1      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39488-39519            1      0.00%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40256-40287            1      0.00%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40832-40863            1      0.00%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40991            1      0.00%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41503            2      0.01%     84.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41664-41695            1      0.00%     84.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42271            1      0.00%     84.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43039            1      0.00%     84.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44127            1      0.00%     84.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45599            1      0.00%     84.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46111            2      0.01%     84.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46367            2      0.01%     84.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46879            1      0.00%     84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-47007            1      0.00%     84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48671            1      0.00%     84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48927            1      0.00%     84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49183            1      0.00%     84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49472-49503            1      0.00%     84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51231            2      0.01%     84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51776-51807            1      0.00%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52255            2      0.01%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53279            1      0.00%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54528-54559            2      0.01%     84.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54784-54815            1      0.00%     84.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56064-56095            1      0.00%     84.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56320-56351            1      0.00%     84.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57280-57311            1      0.00%     84.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57600-57631            2      0.01%     84.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57792-57823            1      0.00%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57856-57887            1      0.00%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58624-58655            1      0.00%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59840-59871            1      0.00%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59968-59999            1      0.00%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60416-60447            1      0.00%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61440-61471            4      0.01%     84.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62208-62239            1      0.00%     84.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62400-62431            1      0.00%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62464-62495            1      0.00%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63519            2      0.01%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63744-63775            1      0.00%     84.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64512-64543            1      0.00%     84.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65152-65183            6      0.02%     84.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65311            6      0.02%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65408-65439            1      0.00%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567         5797     14.94%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129920-129951            1      0.00%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130880-130911            1      0.00%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130944-130975            1      0.00%     99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103          326      0.84%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127            2      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::133632-133663            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::160768-160799            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::165568-165599            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::169728-169759            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::175552-175583            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::189440-189471            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196352-196383            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196639            6      0.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          38811                       # Bytes accessed per row activation
system.physmem.totQLat                   182252409750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              221627859750                       # Sum of mem lat for all requests
system.physmem.totBusLat                  31289130000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8086320000                       # Total cycles spent in bank access
system.physmem.avgQLat                       29123.92                       # Average queueing delay per request
system.physmem.avgBankLat                     1292.19                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  35416.11                       # Average memory access latency
system.physmem.avgRdBW                         359.52                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          47.31                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  53.13                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.54                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.18                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.20                       # Average read queue length over time
system.physmem.avgWrQLen                        11.52                       # Average write queue length over time
system.physmem.readRowHits                    6237911                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    804550                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.68                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.70                       # Row buffer hit rate for writes
system.physmem.avgGap                       157316.33                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           57                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          345                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              402                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           57                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          345                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          402                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           57                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          345                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             402                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     61845817                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7306747                       # Transaction distribution
system.membus.trans_dist::ReadResp            7306747                       # Transaction distribution
system.membus.trans_dist::WriteReq             767893                       # Transaction distribution
system.membus.trans_dist::WriteResp            767893                       # Transaction distribution
system.membus.trans_dist::Writeback             66623                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            33809                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          17757                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12548                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138043                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137663                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1970999                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11650                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          850                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4366027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12189696                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12189696                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave      2382510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port     14160695                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio        11650                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.local_cpu_timer.pio          850                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               16555723                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389777                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17723636                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        23300                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1700                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20138869                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave      2389777                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port     66482420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio        23300                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio         1700                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            68897653                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               68897653                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1475761000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy          8620588249                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.8                       # Layer utilization (%)
system.membus.reqLayer3.occupancy             9828000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy              756000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4823074562                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        13762899732                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
system.l2c.tags.replacements                         72713                       # number of replacements
system.l2c.tags.tagsinuse                     53848.744123                       # Cycle average of tags in use
system.l2c.tags.total_refs                         1839089                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                        137893                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                         13.337073                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks        39490.919089                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker       5.921030                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker       0.000842                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst          4011.444595                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data          2831.104153                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker       9.348710                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst          3706.565293                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data          3793.440412                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks           0.602584                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker      0.000090                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst            0.061210                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data            0.043199                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker      0.000143                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst            0.056558                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data            0.057883                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total                0.821667                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        22072                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4261                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             386985                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166655                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        31010                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5009                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             589730                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198052                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1403774                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          581377                       # number of Writeback hits
system.l2c.Writeback_hits::total               581377                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1341                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             735                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2076                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           210                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           150                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               360                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48293                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58659                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106952                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         22072                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4261                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              386985                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214948                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         31010                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5009                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              589730                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              256711                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1510726                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        22072                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4261                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             386985                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214948                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        31010                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5009                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             589730                       # number of overall hits
system.l2c.overall_hits::cpu1.data             256711                       # number of overall hits
system.l2c.overall_hits::total                1510726                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6279                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6380                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6315                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6244                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25250                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5158                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3783                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8941                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          636                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          418                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1054                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63263                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76953                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140216                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6279                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69643                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6315                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83197                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165466                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           16                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6279                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69643                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6315                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83197                       # number of overall misses
system.l2c.overall_misses::total               165466                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1558000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       130250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    460466000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    469540999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1630500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    488082250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    485700250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1907108249                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9003592                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12282479                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21286071                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       512478                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3025371                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3537849                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4258752123                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5521303068                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9780055191                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1558000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       130250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    460466000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4728293122                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1630500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    488082250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6007003318                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11687163440                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1558000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       130250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    460466000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4728293122                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1630500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    488082250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6007003318                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11687163440                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        22088                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4263                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         393264                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         173035                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        31024                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5009                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         596045                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204296                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1429024                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       581377                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           581377                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6499                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4518                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           11017                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          846                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          568                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1414                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111556                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135612                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247168                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        22088                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4263                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          393264                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284591                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        31024                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5009                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          596045                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          339908                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1676192                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        22088                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4263                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         393264                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284591                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        31024                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5009                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         596045                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         339908                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1676192                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000724                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000469                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015966                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036871                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010595                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030563                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017669                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.793661                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.837317                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.811564                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.751773                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.735915                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.745403                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.567096                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.567450                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567290                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000724                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000469                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015966                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244713                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010595                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.244763                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098715                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000724                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000469                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015966                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244713                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010595                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.244763                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098715                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        97375                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        65125                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73334.288900                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73595.767868                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 116464.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77289.350752                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77786.715247                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 75529.039564                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1745.558744                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3246.756278                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2380.725981                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   805.783019                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7237.729665                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3356.592979                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67318.213221                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71749.029512                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69749.922912                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        97375                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        65125                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73334.288900                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 67893.300432                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 116464.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 77289.350752                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72202.162554                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70631.812215                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        97375                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        65125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73334.288900                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 67893.300432                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 116464.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 77289.350752                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72202.162554                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70631.812215                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66623                       # number of writebacks
system.l2c.writebacks::total                    66623                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            26                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                74                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            26                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           16                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6276                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6343                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6307                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6218                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25176                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5158                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3783                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8941                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          636                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          418                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1054                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63263                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76953                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140216                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6276                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69606                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6307                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83171                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165392                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6276                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69606                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6307                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83171                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165392                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1354500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       105750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    380765750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    387112499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1453000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    407670750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    405239750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1583701999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51696595                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     37937764                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     89634359                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      6384131                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4197915                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10582046                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3459046363                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4543162420                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8002208783                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1354500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       105750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    380765750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   3846158862                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1453000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    407670750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4948402170                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9585910782                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1354500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       105750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    380765750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   3846158862                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1453000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    407670750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4948402170                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9585910782                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      7151250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12399747242                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2451249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593597491                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167002947232                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1054895750                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  25482276685                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  26537172435                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      7151250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13454642992                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2451249                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180075874176                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 193540119667                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000724                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000469                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015959                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036657                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010581                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030436                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017618                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.793661                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.837317                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.811564                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.751773                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.735915                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.745403                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.567096                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.567450                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567290                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000724                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000469                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015959                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244583                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010581                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.244687                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098671                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000724                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000469                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015959                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244583                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010581                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.244687                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098671                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        52875                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60670.132250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61029.875296                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64637.823054                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65172.040849                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62905.227161                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.604692                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.486386                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.093278                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.941824                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.858852                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.891841                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54677.242037                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59038.145621                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57070.582409                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        52875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60670.132250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55256.139729                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64637.823054                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57958.733083                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        52875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57958.733083                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   135543504                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2708876                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2708875                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767893                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767893                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           581377                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           33332                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         18117                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          51449                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           258856                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          258856                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side       787342                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side      1073883                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma        13468                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma        55968                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side      1192763                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side      4801194                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma        14594                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma        72477                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count                      8011689                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side     25176640                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side     34854805                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma        17052                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma        88352                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side     38149824                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side     47763808                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma        20036                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma       124096                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size                 146194613                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             146194613                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4803948                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4894718895                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1774755611                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1516721983                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9224710                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          34035182                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy        2687171756                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy        3246383092                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           9605952                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy          41732428                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      45913386                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7278157                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7278157                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7946                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7946                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          726                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          494                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382510                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12189696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12189696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio         8024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio          726                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio          494                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side     12189696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                14572206                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1452                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          271                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2389777                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio        16048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio         1452                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio          271                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             51148561                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                51148561                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21350000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4018000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               369000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               297000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6094848000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374564000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         16693526268                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6007013                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4581243                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           296095                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3784394                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2916091                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.055692                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 673819                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28621                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8911671                       # DTB read hits
system.cpu0.dtb.read_misses                     28579                       # DTB read misses
system.cpu0.dtb.write_hits                    5140325                       # DTB write hits
system.cpu0.dtb.write_misses                     5457                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1825                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      935                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   297                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      555                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8940250                       # DTB read accesses
system.cpu0.dtb.write_accesses                5145782                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14051996                       # DTB hits
system.cpu0.dtb.misses                          34036                       # DTB misses
system.cpu0.dtb.accesses                     14086032                       # DTB accesses
system.cpu0.itb.inst_hits                     4224524                       # ITB inst hits
system.cpu0.itb.inst_misses                      5106                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1346                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1478                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4229630                       # ITB inst accesses
system.cpu0.itb.hits                          4224524                       # DTB hits
system.cpu0.itb.misses                           5106                       # DTB misses
system.cpu0.itb.accesses                      4229630                       # DTB accesses
system.cpu0.numCycles                        69191123                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11726999                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32040106                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6007013                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3589910                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7522223                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1454890                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     60839                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              19594371                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4906                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        47034                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1322790                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          216                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4222942                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               157135                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2060                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41323427                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.001891                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.382270                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                33808589     81.81%     81.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  565594      1.37%     83.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  817189      1.98%     85.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  676917      1.64%     86.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  774557      1.87%     88.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  561158      1.36%     90.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  668023      1.62%     91.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  352527      0.85%     92.50% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3098873      7.50%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41323427                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.086818                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.463067                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12228313                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20776644                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6830919                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               507068                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                980483                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              935966                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64632                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40044073                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213118                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                980483                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12794933                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5974902                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      12785484                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6719608                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2068017                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38935181                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1840                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                426390                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1152446                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             100                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39283995                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175854037                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       175819876                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34161                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30939461                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8344533                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            411347                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        370357                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5351975                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7655764                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5689444                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1124222                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1281984                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36848399                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             895286                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37254672                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            81509                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6299557                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13203578                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256355                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41323427                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.901539                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.514633                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           26248165     63.52%     63.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5684023     13.75%     77.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3115322      7.54%     84.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2467752      5.97%     90.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2139591      5.18%     95.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             926164      2.24%     98.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             502996      1.22%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             185723      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              53691      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41323427                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  27493      2.57%      2.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   452      0.04%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                842638     78.71%     81.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               200034     18.68%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52214      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22336809     59.96%     60.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46914      0.13%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  6      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              3      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           704      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9369783     25.15%     85.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5448235     14.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37254672                       # Type of FU issued
system.cpu0.iq.rate                          0.538431                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1070617                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028738                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         117010237                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         44051144                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34347967                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8478                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4654                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3872                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38268613                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4462                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          307627                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1377452                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2519                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13094                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       537577                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2192819                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5737                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                980483                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4321779                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               103852                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37861161                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            83824                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7655764                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5689444                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571291                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39684                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                13815                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13094                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        150380                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       118124                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              268504                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             36875907                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9227090                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           378765                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       117476                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14627584                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4856181                       # Number of branches executed
system.cpu0.iew.exec_stores                   5400494                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.532957                       # Inst execution rate
system.cpu0.iew.wb_sent                      36680744                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34351839                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18317228                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35218038                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.496478                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.520109                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6105741                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         638931                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           232529                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40342944                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.775737                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.743782                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28719843     71.19%     71.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5706970     14.15%     85.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1863125      4.62%     89.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       981446      2.43%     92.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       776304      1.92%     94.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       515472      1.28%     95.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       394004      0.98%     96.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       214891      0.53%     97.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1170889      2.90%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40342944                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23687602                       # Number of instructions committed
system.cpu0.commit.committedOps              31295507                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11430179                       # Number of memory references committed
system.cpu0.commit.loads                      6278312                       # Number of loads committed
system.cpu0.commit.membars                     229695                       # Number of memory barriers committed
system.cpu0.commit.branches                   4246577                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27650890                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489495                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1170889                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    75722045                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75784919                       # The number of ROB writes
system.cpu0.timesIdled                         368023                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27867696                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2158812857                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23606860                       # Number of Instructions Simulated
system.cpu0.committedOps                     31214765                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23606860                       # Number of Instructions Simulated
system.cpu0.cpi                              2.930975                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.930975                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.341183                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.341183                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               171887932                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34101589                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3230                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     874                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               12983242                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                451267                       # number of misc regfile writes
system.cpu0.icache.tags.replacements                393301                       # number of replacements
system.cpu0.icache.tags.tagsinuse               511.011114                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs                 3798020                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs                393813                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs                  9.644222                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle            6979217250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.011114                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998069                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total        0.998069                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3798020                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3798020                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3798020                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3798020                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3798020                       # number of overall hits
system.cpu0.icache.overall_hits::total        3798020                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       424793                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       424793                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       424793                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        424793                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       424793                       # number of overall misses
system.cpu0.icache.overall_misses::total       424793                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5908836480                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5908836480                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5908836480                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5908836480                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5908836480                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5908836480                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4222813                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4222813                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4222813                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4222813                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4222813                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4222813                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100595                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100595                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100595                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100595                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100595                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100595                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.919608                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13909.919608                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13909.919608                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3571                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              182                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.620879                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30958                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30958                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30958                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30958                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30958                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30958                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       393835                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       393835                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       393835                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       393835                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       393835                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       393835                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4811729884                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4811729884                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4811729884                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4811729884                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4811729884                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4811729884                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9686500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9686500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9686500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      9686500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093264                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093264                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093264                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093264                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093264                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093264                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.628916                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.628916                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.628916                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.628916                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.628916                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.628916                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements                276277                       # number of replacements
system.cpu0.dcache.tags.tagsinuse               458.508643                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs                 9265297                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs                276789                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs                 33.474224                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle              49564250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   458.508643                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.895525                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total        0.895525                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5784459                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5784459                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3159328                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3159328                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139329                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139329                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137110                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137110                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8943787                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8943787                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8943787                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8943787                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392022                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392022                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1584787                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1584787                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8757                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8757                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7526                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7526                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1976809                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1976809                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1976809                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1976809                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5532398989                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5532398989                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  77338129003                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  77338129003                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     88246985                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     88246985                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     46297127                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     46297127                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  82870527992                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  82870527992                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  82870527992                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  82870527992                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6176481                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6176481                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4744115                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4744115                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148086                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       148086                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144636                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144636                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10920596                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10920596                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10920596                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10920596                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063470                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.063470                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.334053                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.334053                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059135                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059135                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052034                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052034                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.181017                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.181017                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.181017                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.181017                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14112.470701                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14112.470701                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48800.330267                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48800.330267                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10077.307868                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10077.307868                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6151.624635                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6151.624635                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9474                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         7234                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              614                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            133                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.429967                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    54.390977                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256588                       # number of writebacks
system.cpu0.dcache.writebacks::total           256588                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203202                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       203202                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1454368                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1454368                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          460                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          460                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1657570                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1657570                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1657570                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1657570                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188820                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188820                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130419                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130419                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8297                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8297                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7522                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7522                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       319239                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       319239                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       319239                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       319239                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2408343372                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2408343372                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5110867707                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5110867707                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     66642015                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     66642015                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31254873                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31254873                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         3000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         3000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7519211079                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7519211079                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7519211079                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7519211079                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13504631783                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13504631783                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1180253969                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1180253969                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14684885752                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14684885752                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030571                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030571                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027491                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027491                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056028                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056028                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052006                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052006                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029233                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029233                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029233                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029233                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8032.061589                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8032.061589                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4155.128024                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4155.128024                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9066954                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7451944                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           406719                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             6049384                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5236824                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            86.567889                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 772531                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             42321                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42909677                       # DTB read hits
system.cpu1.dtb.read_misses                     36560                       # DTB read misses
system.cpu1.dtb.write_hits                    6823585                       # DTB write hits
system.cpu1.dtb.write_misses                    10691                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2017                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2608                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   306                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      688                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42946237                       # DTB read accesses
system.cpu1.dtb.write_accesses                6834276                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49733262                       # DTB hits
system.cpu1.dtb.misses                          47251                       # DTB misses
system.cpu1.dtb.accesses                     49780513                       # DTB accesses
system.cpu1.itb.inst_hits                     8323198                       # ITB inst hits
system.cpu1.itb.inst_misses                      5400                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1529                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1523                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8328598                       # ITB inst accesses
system.cpu1.itb.hits                          8323198                       # DTB hits
system.cpu1.itb.misses                           5400                       # DTB misses
system.cpu1.itb.accesses                      8328598                       # DTB accesses
system.cpu1.numCycles                       410695591                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19628666                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      66104666                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9066954                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6009355                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14131573                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3952223                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     62853                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              77248707                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                4835                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42228                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1436171                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          176                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8321388                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               704092                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2736                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         115246116                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.694374                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.038205                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               101121884     87.74%     87.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  796637      0.69%     88.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  937162      0.81%     89.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1885853      1.64%     90.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1499695      1.30%     92.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  570142      0.49%     92.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2110638      1.83%     94.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  410756      0.36%     94.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5913349      5.13%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           115246116                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022077                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.160958                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                21155925                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             78195753                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12775663                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               524358                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2594417                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1105836                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                98153                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              75067660                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               326745                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2594417                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22501379                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               33242741                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      40762154                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11860446                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4284979                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              69913296                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                18816                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                670004                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3042907                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             379                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           73978163                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            321899381                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       321840484                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            58897                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49060581                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                24917582                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            444517                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        387690                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7870912                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            13163327                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8127092                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1028302                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1543452                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  63442447                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1157372                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 89134089                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93553                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       16181139                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     45168283                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        276533                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    115246116                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.773424                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.513958                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           84850695     73.63%     73.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8420843      7.31%     80.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4255514      3.69%     84.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3817238      3.31%     87.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10566074      9.17%     97.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1932638      1.68%     98.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1074262      0.93%     99.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             253370      0.22%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              75482      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      115246116                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  32069      0.41%      0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   996      0.01%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7550960     95.79%     96.21% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               298953      3.79%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           314062      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37650996     42.24%     42.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59191      0.07%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1510      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.66% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43937068     49.29%     91.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7171235      8.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              89134089                       # Type of FU issued
system.cpu1.iq.rate                          0.217032                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7882978                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088440                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         301522554                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         80789150                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     53744584                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15343                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8026                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6801                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96694852                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   8153                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          340284                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3407112                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3737                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        16742                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1286559                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31912923                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       915604                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2594417                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               25467221                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               361914                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           64703269                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           112618                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             13163327                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8127092                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            869000                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 64609                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 6290                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         16742                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        200151                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       154994                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              355145                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             86813167                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43279828                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2320922                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       103450                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50389574                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 6997831                       # Number of branches executed
system.cpu1.iew.exec_stores                   7109746                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.211381                       # Inst execution rate
system.cpu1.iew.wb_sent                      85834090                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     53751385                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 29958578                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53322000                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.130879                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.561843                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       16054832                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         880839                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           310229                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    112651699                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.427506                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.393608                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     95929787     85.16%     85.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8195439      7.28%     92.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2121242      1.88%     94.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1255081      1.11%     95.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1260461      1.12%     96.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       575308      0.51%     97.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       943355      0.84%     97.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       590559      0.52%     98.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1780467      1.58%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    112651699                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38067147                       # Number of instructions committed
system.cpu1.commit.committedOps              48159329                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16596748                       # Number of memory references committed
system.cpu1.commit.loads                      9756215                       # Number of loads committed
system.cpu1.commit.membars                     190139                       # Number of memory barriers committed
system.cpu1.commit.branches                   5967970                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42694003                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              534679                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1780467                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   174041277                       # The number of ROB reads
system.cpu1.rob.rob_writes                  131120872                       # The number of ROB writes
system.cpu1.timesIdled                        1414866                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      295449475                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1816711228                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   37997508                       # Number of Instructions Simulated
system.cpu1.committedOps                     48089690                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             37997508                       # Number of Instructions Simulated
system.cpu1.cpi                             10.808488                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.808488                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092520                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092520                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               388394171                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56329363                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5049                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2330                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               18495746                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                405487                       # number of misc regfile writes
system.cpu1.icache.tags.replacements                596092                       # number of replacements
system.cpu1.icache.tags.tagsinuse               480.837460                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs                 7679654                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs                596604                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs                 12.872280                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle           74828235500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.837460                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.939136                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total        0.939136                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      7679654                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7679654                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7679654                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7679654                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7679654                       # number of overall hits
system.cpu1.icache.overall_hits::total        7679654                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       641686                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       641686                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       641686                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        641686                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       641686                       # number of overall misses
system.cpu1.icache.overall_misses::total       641686                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8725652874                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8725652874                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8725652874                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8725652874                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8725652874                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8725652874                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8321340                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8321340                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8321340                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8321340                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8321340                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8321340                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.077113                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.077113                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.077113                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.077113                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.077113                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.077113                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13598.010357                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13598.010357                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3474                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              210                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.542857                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        45060                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        45060                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        45060                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        45060                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        45060                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        45060                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       596626                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       596626                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       596626                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       596626                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       596626                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       596626                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7121155232                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7121155232                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7121155232                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7121155232                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7121155232                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7121155232                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3411250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3411250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3411250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3411250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071698                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071698                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071698                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.071698                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071698                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.071698                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11935.710532                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11935.710532                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11935.710532                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11935.710532                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11935.710532                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements                360464                       # number of replacements
system.cpu1.dcache.tags.tagsinuse               473.569939                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs                12678323                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs                360816                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs                 35.137918                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle           70878166000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.569939                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924941                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total        0.924941                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8311494                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8311494                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4138859                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4138859                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        97571                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        97571                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        94878                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        94878                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12450353                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12450353                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12450353                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12450353                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       398176                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       398176                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1558152                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1558152                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13940                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13940                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10599                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10599                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1956328                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1956328                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1956328                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1956328                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6132182064                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6132182064                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  75676889684                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  75676889684                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    129078996                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    129078996                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53253915                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     53253915                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  81809071748                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  81809071748                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  81809071748                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  81809071748                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8709670                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8709670                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5697011                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5697011                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       111511                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       111511                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105477                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       105477                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14406681                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14406681                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14406681                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14406681                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045717                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045717                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.273503                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.273503                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125010                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125010                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100486                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100486                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135793                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135793                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135793                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135793                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15400.682271                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15400.682271                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48568.361549                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 48568.361549                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9259.612339                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9259.612339                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5024.428248                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5024.428248                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41817.666438                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 41817.666438                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41817.666438                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 41817.666438                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        29976                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        17316                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3303                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            173                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.075386                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   100.092486                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       324789                       # number of writebacks
system.cpu1.dcache.writebacks::total           324789                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       170095                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       170095                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1396532                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1396532                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1437                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1437                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1566627                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1566627                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1566627                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1566627                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       228081                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       228081                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161620                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161620                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12503                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12503                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10598                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10598                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       389701                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       389701                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       389701                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       389701                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2839406051                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2839406051                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6490016907                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6490016907                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88435503                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88435503                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32057085                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32057085                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9329422958                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   9329422958                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9329422958                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   9329422958                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  34787133815                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  34787133815                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026187                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026187                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028369                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028369                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112123                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112123                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100477                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100477                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027050                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027050                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027050                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027050                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7073.142686                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7073.142686                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3024.824023                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3024.824023                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                         0                       # number of replacements
system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 644226028268                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   41725                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   48857                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------