path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.826673                       # Number of seconds simulated
sim_ticks                                2826672558500                       # Number of ticks simulated
final_tick                               2826672558500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 170041                       # Simulator instruction rate (inst/s)
host_op_rate                                   206302                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4002646805                       # Simulator tick rate (ticks/s)
host_mem_usage                                 627056                       # Number of bytes of host memory used
host_seconds                                   706.20                       # Real time elapsed on the host
sim_insts                                   120082757                       # Number of instructions simulated
sim_ops                                     145690782                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         1856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1308688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1308456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8387648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           193312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           594324                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       432320                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12228268                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1308688                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       193312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1502000                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8790464                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8808028                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           29                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             22699                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20965                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       131057                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3088                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9307                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6755                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                193926                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          137351                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               141742                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           657                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              462978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              462896                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2967322                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           158                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               68389                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              210256                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       152943                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4326029                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         462978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          68389                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             531367                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3109827                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6200                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3116041                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3109827                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             462978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             469096                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2967322                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          158                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              68389                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             210270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       152943                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7442070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        193927                       # Number of read requests accepted
system.physmem.writeReqs                       141742                       # Number of write requests accepted
system.physmem.readBursts                      193927                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     141742                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12400768                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10496                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8820224                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12228332                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8808028                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      164                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11912                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11892                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12330                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12174                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14942                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12676                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12556                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12785                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12022                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12081                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11226                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10162                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11365                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11848                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11951                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11840                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8683                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8758                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9038                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8776                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8736                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9287                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9143                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9209                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8594                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8600                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8159                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7478                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8406                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8230                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8500                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8219                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          60                       # Number of times write queue was full causing retry
system.physmem.totGap                    2826672288500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3091                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  190257                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 137351                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     58372                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     70356                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12836                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8377                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      6463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      5422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4671                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1517                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      747                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      311                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      270                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    10498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      187                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        84506                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      251.118169                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     142.721377                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.168687                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          42580     50.39%     50.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17667     20.91%     71.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6229      7.37%     78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3460      4.09%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2829      3.35%     86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1565      1.85%     87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          960      1.14%     89.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          994      1.18%     90.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8222      9.73%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          84506                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6824                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.393318                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      563.270042                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6822     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6824                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6824                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.195780                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.530637                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.731147                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5748     84.23%     84.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             362      5.30%     89.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              98      1.44%     90.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              53      0.78%     91.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             250      3.66%     95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              24      0.35%     95.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              17      0.25%     96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              13      0.19%     96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               6      0.09%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.12%     96.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.15%     96.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             144      2.11%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              13      0.19%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.10%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               6      0.09%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.10%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.06%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             7      0.10%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.07%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             5      0.07%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.13%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             5      0.07%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6824                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10004432906                       # Total ticks spent queuing
system.physmem.totMemAccLat               13637470406                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    968810000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51632.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  70382.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.39                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.33                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.32                       # Average write queue length when enqueuing
system.physmem.readRowHits                     161584                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     85488                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.39                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.02                       # Row buffer hit rate for writes
system.physmem.avgGap                      8421010.84                       # Average gap between requests
system.physmem.pageHitRate                      74.51                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  316830360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  168399330                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 723046380                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                373908600                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           4521291840.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4723358580                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              248942400                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy        9096613470                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        6505168320                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       667621594905                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             694301661855                       # Total energy per rank (pJ)
system.physmem_0.averagePower              245.625060                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2815660418258                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      439528927                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1920369500                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2778771385500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  16940567035                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      8652241815                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  19948465723                       # Time in different power states
system.physmem_1.actEnergy                  286542480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  152300940                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 660414300                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                345490920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           4558170240.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4719582900                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              238189440                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy        8751236790                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        6789483360                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       667674392880                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             694177600920                       # Total energy per rank (pJ)
system.physmem_1.averagePower              245.581186                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2815698296531                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      410333187                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1936500000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2778826050750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  17681028809                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      8627428782                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  19191216972                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          112                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          176                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          288                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             18                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           62                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              102                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           62                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          102                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               23882865                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         15636955                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           931558                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            14470894                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                9520533                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.790911                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3844072                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             34146                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        1359371                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           1203202                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          156169                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        49075                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    66298                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               66298                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25087                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        19168                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        22043                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        44255                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   493.831206                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3088.958464                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        43053     97.28%     97.28% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          899      2.03%     99.32% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          141      0.32%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767           95      0.21%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959           32      0.07%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           18      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343            1      0.00%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535           14      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        44255                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        16149                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11407.424608                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9685.730755                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9901.207568                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383        14668     90.83%     90.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1230      7.62%     98.45% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          211      1.31%     99.75% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535           16      0.10%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071            4      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-245759           17      0.11%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        16149                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  86482404152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.594104                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.503301                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  86424292152     99.93%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     40499500      0.05%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5      7958000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4655000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      1502500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11       969000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1099000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1428000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17         1000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  86482404152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5106     78.70%     78.70% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1382     21.30%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6488                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        66298                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        66298                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6488                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6488                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        72786                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17693188                       # DTB read hits
system.cpu0.dtb.read_misses                     55688                       # DTB read misses
system.cpu0.dtb.write_hits                   14580631                       # DTB write hits
system.cpu0.dtb.write_misses                    10610                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3435                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      159                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2213                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      845                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17748876                       # DTB read accesses
system.cpu0.dtb.write_accesses               14591241                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32273819                       # DTB hits
system.cpu0.dtb.misses                          66298                       # DTB misses
system.cpu0.dtb.accesses                     32340117                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    11677                       # Table walker walks requested
system.cpu0.itb.walker.walksShort               11677                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3850                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6772                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         1055                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        10622                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1021.559028                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  3971.298769                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095         9829     92.53%     92.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191          232      2.18%     94.72% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287          234      2.20%     96.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383          118      1.11%     98.03% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479           84      0.79%     98.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575           68      0.64%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671           21      0.20%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767           17      0.16%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863           11      0.10%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959            4      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-53247            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        10622                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3671                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12324.162354                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11375.149198                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5369.602272                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          593     16.15%     16.15% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         2793     76.08%     92.24% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          150      4.09%     96.32% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           91      2.48%     98.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           38      1.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3671                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  22057105212                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.847252                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.360404                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     3373925500     15.30%     15.30% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    18678889712     84.68%     99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        3873000      0.02%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         379500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4          37500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  22057105212                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2281     87.19%     87.19% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          335     12.81%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2616                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11677                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11677                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2616                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2616                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        14293                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    37442886                       # ITB inst hits
system.cpu0.itb.inst_misses                     11677                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2325                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     2439                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                37454563                       # ITB inst accesses
system.cpu0.itb.hits                         37442886                       # DTB hits
system.cpu0.itb.misses                          11677                       # DTB misses
system.cpu0.itb.accesses                     37454563                       # DTB accesses
system.cpu0.numPwrStateTransitions               3670                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1835                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1504014886.326976                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   24031487578.448807                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1058     57.66%     57.66% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          770     41.96%     99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            2      0.11%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499970835992                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1835                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON    66805242090                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759867316410                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       133611951                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          19303849                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     111829084                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   23882865                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          14567807                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    107369786                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2747392                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    153767                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               58387                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       435607                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       423633                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles        97811                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 37442098                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               257331                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   6030                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         129216536                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.043099                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.255701                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67189169     52.00%     52.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                21288743     16.48%     68.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 8719000      6.75%     75.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                32019624     24.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           129216536                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.178748                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.836969                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                19892285                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             62318410                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 41002144                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              4961574                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1042123                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             8668351                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               335752                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             109935605                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              3778741                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1042123                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                25542587                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12841185                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      37729185                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 40176897                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             11884559                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             104971930                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1005936                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1490559                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                163297                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 57296                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               7681326                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          109147487                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            479167735                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       120008007                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             9453                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             98091135                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                11056341                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1226764                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1083940                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12369905                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            18622381                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           16045587                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1690063                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2196173                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 102089116                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1690972                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                100270845                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           450536                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9007472                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     21276029                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        120459                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    129216536                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.775991                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.026149                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           73187499     56.64%     56.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           23243158     17.99%     74.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           22432715     17.36%     91.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            9250445      7.16%     99.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1102673      0.85%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 46      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      129216536                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                9305182     40.57%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    67      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5565388     24.27%     64.84% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8055351     35.12%     99.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead             2851      0.01%     99.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite            6938      0.03%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             66163298     65.98%     65.99% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               92264      0.09%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8058      0.01%     66.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.09% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            18375460     18.33%     84.41% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           15618206     15.58%     99.99% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead           3108      0.00%     99.99% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite          8177      0.01%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             100270845                       # Type of FU issued
system.cpu0.iq.rate                          0.750463                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   22935777                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.228738                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         353112143                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        112794988                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     98251090                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              32395                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             11310                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         9716                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             123183269                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  21080                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          364715                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1893331                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2466                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        18814                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       881018                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       109546                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       360879                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1042123                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1649895                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               244572                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          103932598                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             18622381                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            16045587                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            874828                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 27967                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               192686                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         18814                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        252890                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       404204                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              657094                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             99256545                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             17939836                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           948116                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       152510                       # number of nop insts executed
system.cpu0.iew.exec_refs                    33405569                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                16813883                       # Number of branches executed
system.cpu0.iew.exec_stores                  15465733                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.742872                       # Inst execution rate
system.cpu0.iew.wb_sent                      98711091                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     98260806                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 51187228                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 84552650                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.735419                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.605389                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts        8010093                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1570513                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           599985                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    127532122                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.744084                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.464109                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     83238506     65.27%     65.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     24683933     19.36%     84.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      8242078      6.46%     91.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3223359      2.53%     93.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      3451127      2.71%     96.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      1466865      1.15%     97.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1171264      0.92%     98.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       549844      0.43%     98.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1505146      1.18%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    127532122                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            78880347                       # Number of instructions committed
system.cpu0.commit.committedOps              94894659                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      31893618                       # Number of memory references committed
system.cpu0.commit.loads                     16729049                       # Number of loads committed
system.cpu0.commit.membars                     646523                       # Number of memory barriers committed
system.cpu0.commit.branches                  16211772                       # Number of branches committed
system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 81832780                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             1927003                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        62903043     66.29%     66.29% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          89941      0.09%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8057      0.01%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       16726793     17.63%     84.02% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      15157121     15.97%     99.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead         2256      0.00%     99.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite         7448      0.01%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         94894659                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1505146                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   224742704                       # The number of ROB reads
system.cpu0.rob.rob_writes                  207484818                       # The number of ROB writes
system.cpu0.timesIdled                         136289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        4395415                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5519733867                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   78758295                       # Number of Instructions Simulated
system.cpu0.committedOps                     94772607                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.696481                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.696481                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.589455                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.589455                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               110218064                       # number of integer regfile reads
system.cpu0.int_regfile_writes               59484746                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     8170                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                349694687                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                40999571                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              254801117                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1223326                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           712506                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          498.213160                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           28740042                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           713018                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            40.307597                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        296154500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.213160                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.973073                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.973073                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          347                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63341698                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63341698                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     15523802                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15523802                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     11993925                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      11993925                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307586                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       307586                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       362517                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       362517                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360768                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       360768                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     27517727                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        27517727                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     27825313                       # number of overall hits
system.cpu0.dcache.overall_hits::total       27825313                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       649486                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       649486                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1895154                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1895154                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       148364                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       148364                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25286                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        25286                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20247                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20247                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2544640                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2544640                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2693004                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2693004                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9367064500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   9367064500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33076385872                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  33076385872                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    412133000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    412133000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    479472000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    479472000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       454500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       454500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  42443450372                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  42443450372                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  42443450372                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  42443450372                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16173288                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16173288                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13889079                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13889079                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       455950                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       455950                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387803                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387803                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381015                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381015                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30062367                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30062367                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30518317                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30518317                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040158                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.040158                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136449                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.136449                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.325395                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.325395                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065203                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065203                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084645                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.084645                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088242                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.088242                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14422.273151                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14422.273151                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17453.138833                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17453.138833                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16298.861030                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16298.861030                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23681.137946                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23681.137946                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16679.550102                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16679.550102                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15760.633988                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15760.633988                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          689                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      4988118                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               32                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         201830                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.531250                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    24.714453                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       712509                       # number of writebacks
system.cpu0.dcache.writebacks::total           712509                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       261058                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       261058                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1569543                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1569543                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18570                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18570                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1830601                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1830601                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1830601                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1830601                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       388428                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       388428                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325611                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       325611                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102372                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       102372                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6716                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6716                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20247                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20247                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       714039                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       714039                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       816411                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       816411                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20577                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19269                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19269                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39846                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5013254500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5013254500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6647950897                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6647950897                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1709667500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1709667500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108314000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108314000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459237000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459237000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       442500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       442500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11661205397                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11661205397                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13370872897                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13370872897                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4595503500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4595503500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4595503500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4595503500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024017                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024017                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023444                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023444                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224525                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224525                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017318                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017318                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023752                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023752                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026752                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026752                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12906.521929                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12906.521929                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20416.849852                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20416.849852                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16700.538233                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16700.538233                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16127.754616                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16127.754616                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22681.730627                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22681.730627                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16331.328397                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16331.328397                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16377.624624                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16377.624624                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223332.045488                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223332.045488                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115331.614215                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115331.614215                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1246758                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.757641                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36137139                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1247269                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            28.973011                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6586723000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.757641                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999527                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999527                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         76124237                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        76124237                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     36137142                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36137142                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36137142                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36137142                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36137142                       # number of overall hits
system.cpu0.icache.overall_hits::total       36137142                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1301318                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1301318                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1301318                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1301318                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1301318                       # number of overall misses
system.cpu0.icache.overall_misses::total      1301318                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14070925518                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14070925518                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14070925518                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14070925518                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14070925518                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14070925518                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     37438460                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     37438460                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     37438460                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     37438460                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     37438460                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     37438460                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034759                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.034759                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034759                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.034759                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034759                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.034759                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10812.826318                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10812.826318                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10812.826318                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10812.826318                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10812.826318                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10812.826318                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1742114                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1649                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           114160                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.260284                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   126.846154                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1246758                       # number of writebacks
system.cpu0.icache.writebacks::total          1246758                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54000                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        54000                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        54000                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        54000                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        54000                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        54000                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1247318                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1247318                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1247318                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1247318                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1247318                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1247318                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3008                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3008                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12734729518                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  12734729518                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12734729518                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  12734729518                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12734729518                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  12734729518                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    287646998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    287646998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    287646998                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    287646998                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033316                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033316                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033316                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.033316                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033316                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.033316                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10209.689524                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10209.689524                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10209.689524                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10209.689524                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10209.689524                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10209.689524                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1845705                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1848223                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         2284                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       235089                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          270085                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15641.965642                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1885208                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          285711                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.598304                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14498.888394                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.509265                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.944405                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1130.623578                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.884942                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000702                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000058                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.069008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.954710                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          275                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15342                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           64                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          136                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           72                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          282                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1456                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7618                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4683                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1303                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.016785                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.936401                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        67537653                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       67537653                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        55283                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        14603                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         69886                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       482862                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       482862                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1445066                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1445066                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       220992                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       220992                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1177410                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1177410                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       389847                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       389847                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        55283                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        14603                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1177410                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       610839                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1858135                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        55283                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        14603                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1177410                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       610839                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1858135                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          528                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          200                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          728                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55774                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55774                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20246                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20246                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        49029                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        49029                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        69866                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        69866                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       107548                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       107548                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          528                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          200                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        69866                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       156577                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       227171                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          528                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          200                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        69866                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       156577                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       227171                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     17967500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4680500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     22648000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     38083500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total     38083500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9705500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9705500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       424500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       424500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3399006998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   3399006998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3707068000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3707068000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3498037999                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3498037999                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     17967500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4680500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3707068000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6897044997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  10626760997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     17967500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4680500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3707068000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6897044997                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  10626760997                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        55811                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        14803                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        70614                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       482862                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       482862                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1445066                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1445066                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55774                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55774                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20246                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20246                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270021                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       270021                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1247276                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1247276                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       497395                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       497395                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        55811                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        14803                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1247276                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       767416                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2085306                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        55811                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        14803                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1247276                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       767416                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2085306                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009461                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.013511                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.010310                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.181575                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.181575                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056015                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056015                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.216223                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.216223                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009461                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.013511                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056015                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.204031                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.108939                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009461                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.013511                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056015                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.204031                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.108939                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34029.356061                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23402.500000                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.890110                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   682.818159                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   682.818159                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   479.378643                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   479.378643                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       424500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       424500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69326.459810                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69326.459810                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53059.685684                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53059.685684                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32525.365409                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32525.365409                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34029.356061                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23402.500000                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53059.685684                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44048.902438                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46778.686527                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34029.356061                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23402.500000                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53059.685684                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44048.902438                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46778.686527                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          192                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10583                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       229428                       # number of writebacks
system.cpu0.l2cache.writebacks::total          229428                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5884                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5884                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           42                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           42                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          782                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          782                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           42                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6666                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6712                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           42                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6666                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6712                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          526                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          198                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          724                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       262267                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       262267                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55774                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55774                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20246                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20246                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43145                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43145                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        69824                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        69824                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       106766                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       106766                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          526                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          198                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        69824                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       149911                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       220459                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          526                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          198                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        69824                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       149911                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       262267                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       482726                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23585                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19269                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19269                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42854                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     14785500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3455500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     18241000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17281059402                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17281059402                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    963844000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    963844000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    306251499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    306251499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       352500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       352500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2242873000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2242873000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3286309500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3286309500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2812269499                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2812269499                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     14785500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3455500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3286309500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5055142499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8359692999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     14785500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3455500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3286309500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5055142499                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17281059402                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  25640752401                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    265086000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4430574500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4695660500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    265086000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4430574500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4695660500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009425                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013376                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010253                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159784                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159784                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.055981                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.055981                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.214650                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.214650                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009425                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.013376                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.055981                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.195345                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.105720                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009425                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.013376                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.055981                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.195345                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231489                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25194.751381                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65891.093435                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17281.242156                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17281.242156                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15126.518769                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15126.518769                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       352500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       352500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51984.540503                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51984.540503                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47065.614975                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47065.614975                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26340.496965                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26340.496965                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47065.614975                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33720.957762                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37919.490694                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47065.614975                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33720.957762                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53116.576279                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215316.834330                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199095.208819                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111192.453446                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109573.447053                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      4070347                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2055545                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        32650                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       214495                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       212607                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1888                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        104418                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1897981                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19269                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19269                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       712665                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1476401                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict        88407                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       330099                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87722                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42827                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       113743                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       288516                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284937                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1247318                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       587795                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3260                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp           16                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3747367                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2580614                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        32197                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119234                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6479412                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    159666240                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98907572                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        59212                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       223244                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         258856268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     926807                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18833272                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      3029449                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.088921                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.286812                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2761954     91.17%     91.17% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            265607      8.77%     99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              1888      0.06%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3029449                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    4055747992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114619003                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1874463037                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1221112489                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     17401984                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     63454935                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               33856624                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         11500186                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           284574                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            18698220                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5965214                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            31.902577                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               12503434                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7767                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        9010077                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           8973983                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           36094                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        10763                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    21842                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               21842                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8830                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5887                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore         7125                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        14717                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   626.588299                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3443.893339                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095        14047     95.45%     95.45% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191          191      1.30%     96.75% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287          228      1.55%     98.29% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383          115      0.78%     99.08% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479           21      0.14%     99.22% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575           23      0.16%     99.37% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671            7      0.05%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767           61      0.41%     99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863            9      0.06%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959            3      0.02%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055            7      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::57344-61439            4      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        14717                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5501                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11163.061262                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9675.830911                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6263.258432                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1953     35.50%     35.50% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2904     52.79%     88.29% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          452      8.22%     96.51% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          149      2.71%     99.22% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           15      0.27%     99.49% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           22      0.40%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            4      0.07%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5501                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  77610116560                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.192083                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.397646                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    62747643816     80.85%     80.85% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    14840857744     19.12%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2       12907000      0.02%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3        3989500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4        1311000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5         947500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6        1279000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7         355000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8         209000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9         144500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10        123000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11         26500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12        158000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13         24500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14          7000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15        133500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  77610116560                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1910     75.26%     75.26% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          628     24.74%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2538                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21842                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21842                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2538                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2538                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24380                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10130559                       # DTB read hits
system.cpu1.dtb.read_misses                     18924                       # DTB read misses
system.cpu1.dtb.write_hits                    6492882                       # DTB write hits
system.cpu1.dtb.write_misses                     2918                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1948                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       62                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   418                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      414                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10149483                       # DTB read accesses
system.cpu1.dtb.write_accesses                6495800                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16623441                       # DTB hits
system.cpu1.dtb.misses                          21842                       # DTB misses
system.cpu1.dtb.accesses                     16645283                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     6562                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                6562                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2897                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         3033                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          632                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         5930                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   575.716695                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  2785.933852                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095         5654     95.35%     95.35% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191          104      1.75%     97.10% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287           84      1.42%     98.52% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383           46      0.78%     99.29% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479           13      0.22%     99.51% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575            9      0.15%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671           14      0.24%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-32767            3      0.05%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-36863            2      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::36864-40959            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         5930                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1787                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12039.171796                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10885.386949                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5807.969289                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          326     18.24%     18.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1260     70.51%     88.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          112      6.27%     95.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           73      4.09%     99.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959            5      0.28%     99.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            6      0.34%     99.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.22%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1787                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  17460932916                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.922072                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.268326                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1361890264      7.80%      7.80% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    16097906652     92.19%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        1078000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3          58000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  17460932916                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          986     85.37%     85.37% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          169     14.63%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1155                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6562                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6562                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1155                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1155                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         7717                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    43481037                       # ITB inst hits
system.cpu1.itb.inst_misses                      6562                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1123                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      565                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                43487599                       # ITB inst accesses
system.cpu1.itb.hits                         43481037                       # DTB hits
system.cpu1.itb.misses                           6562                       # DTB misses
system.cpu1.itb.accesses                     43487599                       # DTB accesses
system.cpu1.numPwrStateTransitions               5583                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2792                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    993380119.566619                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25601801103.735863                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1979     70.88%     70.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          809     28.98%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 959983178648                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2792                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    53155264670                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773517293830                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       106311330                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          10498191                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108665043                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   33856624                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          27442631                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     92291638                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3748932                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     86712                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               30975                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       185919                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       298023                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles        23349                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 43479865                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               112855                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2560                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         105289273                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.278878                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.339497                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                48625526     46.18%     46.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                13920511     13.22%     59.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 7498101      7.12%     66.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                35245135     33.47%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           105289273                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.318467                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.022140                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                13318727                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             62566078                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 26583147                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1076022                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1745299                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             4334852                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               132018                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              67655162                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              1099039                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1745299                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17698509                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2385948                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      57515508                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 23258780                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2685229                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              54782270                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               214949                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               261715                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 37045                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 16294                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1684754                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           54670319                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            258827504                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        58243055                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             1689                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             52176795                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2493524                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1869295                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1798183                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 13052424                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            10386014                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6834101                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           620797                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          744232                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  53921335                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             577687                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 53701083                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93984                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        3580846                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      5052182                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         42977                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    105289273                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.510034                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.848273                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           72135914     68.51%     68.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           16498960     15.67%     84.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           13045494     12.39%     96.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3324500      3.16%     99.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             284390      0.27%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                 15      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      105289273                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2891632     45.26%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   674      0.01%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                   0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1660257     25.99%     71.25% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1834987     28.72%     99.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead              656      0.01%     99.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite            1067      0.02%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             36615420     68.18%     68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46378      0.09%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc                 0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3321      0.01%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            10339913     19.25%     87.53% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6693876     12.47%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead            720      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite          1389      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              53701083                       # Type of FU issued
system.cpu1.iq.rate                          0.505130                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    6389273                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.118978                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         219168744                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         58087331                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     51738316                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads               5952                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              2080                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         1787                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              60086458                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   3832                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           90387                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       431562                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          735                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         9576                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       270603                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        51945                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        76138                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1745299                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 526771                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               105542                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           54540026                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             10386014                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6834101                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            292206                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  7827                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                90888                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          9576                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         43509                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       122774                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              166283                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             53458422                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10243364                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           220834                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        41004                       # number of nop insts executed
system.cpu1.iew.exec_refs                    16887479                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                11797622                       # Number of branches executed
system.cpu1.iew.exec_stores                   6644115                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.502848                       # Inst execution rate
system.cpu1.iew.wb_sent                      53318700                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     51740103                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 25143993                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 38375917                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.486685                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.655202                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        3338971                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         534710                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           155407                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    103400366                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.492755                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.151487                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     77772385     75.21%     75.21% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     14344116     13.87%     89.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6076791      5.88%     94.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       698306      0.68%     95.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1980317      1.92%     97.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      1651720      1.60%     99.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       355943      0.34%     99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       123415      0.12%     99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       397373      0.38%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    103400366                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            41357318                       # Number of instructions committed
system.cpu1.commit.committedOps              50951031                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16517950                       # Number of memory references committed
system.cpu1.commit.loads                      9954452                       # Number of loads committed
system.cpu1.commit.membars                     209769                       # Number of memory barriers committed
system.cpu1.commit.branches                  11645067                       # Number of branches committed
system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 45808028                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             3371132                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        34384478     67.49%     67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          45282      0.09%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3321      0.01%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        9953936     19.54%     87.12% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       6562230     12.88%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead          516      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite         1268      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         50951031                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               397373                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   137214928                       # The number of ROB reads
system.cpu1.rob.rob_writes                  110460111                       # The number of ROB writes
system.cpu1.timesIdled                          59286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1022057                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5546467999                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   41324462                       # Number of Instructions Simulated
system.cpu1.committedOps                     50918175                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.572600                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.572600                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.388712                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.388712                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                56077052                       # number of integer regfile reads
system.cpu1.int_regfile_writes               35632532                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     1385                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                190521590                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                15513949                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              212156067                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                383841                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           187625                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.246001                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           15706444                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           187980                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            83.553804                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      89314291000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.246001                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920402                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.920402                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         32901851                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        32901851                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      9540637                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9540637                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      5911714                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       5911714                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49749                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49749                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78973                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78973                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71099                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71099                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     15452351                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        15452351                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     15502100                       # number of overall hits
system.cpu1.dcache.overall_hits::total       15502100                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       214896                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       214896                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       395681                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       395681                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30189                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30189                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18483                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18483                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23644                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23644                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       610577                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        610577                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       640766                       # number of overall misses
system.cpu1.dcache.overall_misses::total       640766                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3583570500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3583570500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10071608465                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  10071608465                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363005500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    363005500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    554928000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    554928000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       408500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       408500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  13655178965                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  13655178965                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  13655178965                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  13655178965                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9755533                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9755533                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6307395                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6307395                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79938                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79938                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97456                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97456                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94743                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94743                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16062928                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16062928                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16142866                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16142866                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022028                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.022028                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.062733                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.062733                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377655                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377655                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.189655                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.189655                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249559                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249559                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038012                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038012                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039693                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.039693                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16675.836218                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16675.836218                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25453.859207                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25453.859207                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19639.966456                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19639.966456                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.140416                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.140416                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22364.384779                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22364.384779                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21310.710876                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21310.710876                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          381                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1471779                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               29                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          39630                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.137931                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    37.138002                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       187625                       # number of writebacks
system.cpu1.dcache.writebacks::total           187625                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        78547                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        78547                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       305511                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       305511                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13157                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13157                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       384058                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       384058                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       384058                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       384058                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       136349                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       136349                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        90170                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        90170                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28879                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        28879                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5326                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5326                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23644                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23644                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       226519                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       226519                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       255398                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       255398                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14314                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14314                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11648                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11648                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25962                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25962                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1988454500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1988454500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2445262471                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2445262471                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    492196500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    492196500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93636000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93636000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    531294000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    531294000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       398500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       398500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4433716971                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4433716971                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4925913471                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4925913471                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2472670000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2472670000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2472670000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2472670000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013977                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013977                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014296                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014296                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.361267                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.361267                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054650                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054650                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249559                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249559                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014102                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.014102                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015821                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.015821                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14583.564969                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14583.564969                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27118.359443                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27118.359443                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17043.405243                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17043.405243                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17580.923770                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17580.923770                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.563356                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.563356                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19573.267457                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19573.267457                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19287.204563                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19287.204563                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.865167                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.865167                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95241.891996                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95241.891996                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           599092                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.435973                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           42856272                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           599604                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            71.474293                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      79139515500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.435973                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975461                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975461                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         87558770                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        87558770                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     42856272                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       42856272                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     42856272                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        42856272                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     42856272                       # number of overall hits
system.cpu1.icache.overall_hits::total       42856272                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       623309                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       623309                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       623309                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        623309                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       623309                       # number of overall misses
system.cpu1.icache.overall_misses::total       623309                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5905173986                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5905173986                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5905173986                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5905173986                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5905173986                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5905173986                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     43479581                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     43479581                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     43479581                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     43479581                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     43479581                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     43479581                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014336                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014336                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014336                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014336                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014336                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014336                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9473.910991                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9473.910991                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9473.910991                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9473.910991                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9473.910991                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9473.910991                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       533657                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          290                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            42078                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.682566                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          290                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       599092                       # number of writebacks
system.cpu1.icache.writebacks::total           599092                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        23701                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        23701                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        23701                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        23701                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        23701                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        23701                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       599608                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       599608                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       599608                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       599608                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       599608                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       599608                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          101                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          101                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5403181271                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5403181271                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5403181271                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5403181271                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5403181271                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5403181271                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9499999                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9499999                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9499999                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9499999                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013791                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013791                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013791                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013791                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013791                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013791                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9011.189429                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9011.189429                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9011.189429                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9011.189429                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9011.189429                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9011.189429                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       194821                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       195463                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          575                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59841                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           44456                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14684.761874                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            706823                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           58616                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           12.058534                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14300.099102                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.020323                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.955758                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   371.686691                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.872809                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000612                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000180                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.022686                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.896287                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          332                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13796                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          205                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          117                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1791                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8656                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3349                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.020264                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001953                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.842041                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        27731086                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       27731086                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        17081                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7133                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         24214                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       114521                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       114521                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       659711                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       659711                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27226                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27226                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       575115                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       575115                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        98702                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        98702                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        17081                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7133                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       575115                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       125928                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         725257                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        17081                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7133                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       575115                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       125928                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        725257                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          517                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          296                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          813                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29667                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29667                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23643                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23643                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33950                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        33950                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        24491                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        24491                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        71832                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        71832                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          517                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          296                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        24491                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       105782                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       131086                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          517                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          296                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        24491                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       105782                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       131086                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     11135000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6028000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     17163000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     12712500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     12712500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     18521500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     18521500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       382999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       382999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1470067999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1470067999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1003037500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1003037500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1657187499                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1657187499                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     11135000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6028000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1003037500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3127255498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4147455998                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     11135000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6028000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1003037500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3127255498                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4147455998                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17598                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7429                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        25027                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114522                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       114522                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       659711                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       659711                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29667                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29667                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23643                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23643                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61176                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61176                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       599606                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       599606                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       170534                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       170534                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17598                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7429                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       599606                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       231710                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       856343                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17598                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7429                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       599606                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       231710                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       856343                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.029378                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.039844                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.032485                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000009                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000009                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554956                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554956                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.040845                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.040845                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.421218                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.421218                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.029378                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.039844                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.040845                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.456528                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.153077                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.029378                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.039844                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.040845                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.456528                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.153077                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21537.717602                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20364.864865                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21110.701107                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   428.506421                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   428.506421                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   783.381974                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   783.381974                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       382999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       382999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43300.971988                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43300.971988                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40955.350945                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40955.350945                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23070.323797                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23070.323797                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21537.717602                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20364.864865                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40955.350945                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29563.210168                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31639.198679                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21537.717602                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20364.864865                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40955.350945                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29563.210168                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31639.198679                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          182                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    30.333333                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             827                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        31720                       # number of writebacks
system.cpu1.l2cache.writebacks::total           31720                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          426                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          426                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           74                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           74                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            7                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          500                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          509                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            7                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          500                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          509                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          516                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          295                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          811                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25186                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        25186                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29667                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29667                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23643                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23643                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33524                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33524                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        24484                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        24484                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        71758                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        71758                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          516                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          295                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        24484                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       105282                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       130577                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          516                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          295                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        24484                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       105282                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25186                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       155763                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14314                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14415                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11648                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11648                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25962                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26063                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8020500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4240500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     12261000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1092841786                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1092841786                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    456571000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    456571000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    353660000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    353660000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       322999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       322999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1211819000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1211819000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    855998500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    855998500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1224293499                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1224293499                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      8020500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4240500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    855998500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2436112499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3304371999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      8020500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4240500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    855998500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2436112499                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1092841786                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4397213785                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2358114500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2366856500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2358114500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2366856500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.029322                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.039709                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032405                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000009                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000009                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.547993                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.547993                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.040833                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040833                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.420784                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.420784                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.029322                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.039709                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.040833                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.454370                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.152482                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.029322                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.039709                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.040833                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.454370                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.181893                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15118.372380                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43390.843564                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.860788                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.860788                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14958.338620                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14958.338620                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       322999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       322999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36147.804558                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.804558                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34961.546316                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34961.546316                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17061.421709                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17061.421709                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34961.546316                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23138.926873                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.926764                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34961.546316                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23138.926873                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28230.155974                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.826184                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.999306                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90829.462291                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90812.895676                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1681326                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       850022                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12491                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       115149                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       106381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8768                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         43982                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       852476                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11648                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11648                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       147635                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       672194                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        29901                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        30357                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        73327                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42065                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86118                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        68535                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        65700                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       599608                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       274791                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          374                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1798508                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       885295                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        16392                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        38202                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2738397                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     76718288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29683872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29716                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         106502268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     347702                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              4882288                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1207717                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.121214                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.347910                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1070093     88.60%     88.60% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            128856     10.67%     99.27% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              8768      0.73%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1207717                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1656031495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80775328                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    899618286                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    396030671                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      8974477                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     20614978                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59420                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59420                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56598                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180864                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71542                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484040                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40387001                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               330000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                32000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               574500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               53000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6115000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            33791000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187784301                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84716000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36458                       # number of replacements
system.iocache.tags.tagsinuse               14.554359                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         255387586000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.554359                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.909647                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.909647                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36476                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
system.iocache.overall_misses::total            36476                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     40605876                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     40605876                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4346476425                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4346476425                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4387082301                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4387082301                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4387082301                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4387082301                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36476                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36476                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36476                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36476                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 161134.428571                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 161134.428571                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119988.858906                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 119988.858906                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120273.119339                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120273.119339                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120273.119339                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120273.119339                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           191                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    63.666667                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36476                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36476                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36476                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36476                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     28005876                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     28005876                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2533401277                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2533401277                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2561407153                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2561407153                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2561407153                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2561407153                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111134.428571                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111134.428571                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69937.093557                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69937.093557                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70221.711619                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70221.711619                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70221.711619                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70221.711619                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   137443                       # number of replacements
system.l2c.tags.tagsinuse                65137.298659                       # Cycle average of tags in use
system.l2c.tags.total_refs                     547823                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   202801                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.701284                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              87493786000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    6068.008119                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.951872                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.052619                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7988.261154                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6937.855049                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37116.430492                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     3.708460                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909745                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1897.444635                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3115.453147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1993.223368                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.092590                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000228                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.121891                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.105863                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.566352                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000057                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.028953                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.047538                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030414                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993916                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        33259                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           25                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32074                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          185                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5974                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        27100                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4863                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        27079                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.507492                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000381                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.489410                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6288814                       # Number of tag accesses
system.l2c.tags.data_accesses                 6288814                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       261149                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          261149                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           41513                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4842                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               46355                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2681                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          2272                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              4953                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4003                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1563                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5566                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          282                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           80                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        50115                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        57309                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46378                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           44                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           17                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        21480                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11675                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         4930                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           192310                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           282                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            80                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               50115                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               61312                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46378                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            44                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            17                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               21480                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               13238                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         4930                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  197876                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          282                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           80                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              50115                       # number of overall hits
system.l2c.overall_hits::cpu0.data              61312                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46378                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           44                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           17                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              21480                       # number of overall hits
system.l2c.overall_hits::cpu1.data              13238                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         4930                       # number of overall hits
system.l2c.overall_hits::total                 197876                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data           453                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           282                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total               735                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           99                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           81                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             180                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11239                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8266                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19505                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           29                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19709                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9351                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131214                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3001                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1024                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6755                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         171094                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           29                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19709                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20590                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       131214                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3001                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9290                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6755                       # number of demand (read+write) misses
system.l2c.demand_misses::total                190599                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           29                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19709                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20590                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       131214                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3001                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9290                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6755                       # number of overall misses
system.l2c.overall_misses::total               190599                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      8930500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       709000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      9639500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       540000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       293500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       833500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1649495000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    781758500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2431253500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      5602000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       249000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2048083000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1082250500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  16438409497                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       622500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        89500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    340295000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    119337000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    980449226                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  21015387223                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5602000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       249000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2048083000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2731745500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  16438409497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       622500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        89500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    340295000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    901095500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    980449226                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23446640723                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5602000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       249000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2048083000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2731745500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  16438409497                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       622500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        89500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    340295000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    901095500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    980449226                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23446640723                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       261149                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       261149                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41966                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5124                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           47090                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2780                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2353                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5133                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15242                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9829                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25071                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          311                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           83                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        69824                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        66660                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       177592                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           51                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           18                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        24481                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        12699                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11685                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       363404                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          311                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           83                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           69824                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           81902                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       177592                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           51                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           18                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           24481                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           22528                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11685                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              388475                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          311                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           83                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          69824                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          81902                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       177592                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           51                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           18                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          24481                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          22528                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11685                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             388475                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.010794                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.055035                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.015608                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.035612                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.034424                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.035067                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.737370                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.840981                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.777991                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.093248                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.036145                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.282267                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.140279                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.137255                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.122585                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.080636                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.470809                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.093248                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.036145                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.282267                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.251398                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.137255                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.122585                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.412376                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.490634                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.093248                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.036145                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.282267                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.251398                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.137255                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.122585                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.412376                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.490634                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19714.128035                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2514.184397                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13114.965986                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5454.545455                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3623.456790                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4630.555556                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146765.281609                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94575.187515                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 124647.705716                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 193172.413793                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        83000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 103916.129687                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115736.338360                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88928.571429                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        89500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113393.868710                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116540.039062                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 122829.481005                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 193172.413793                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 103916.129687                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 132673.409422                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88928.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        89500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 113393.868710                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 96996.286329                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123015.549520                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 193172.413793                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 103916.129687                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 132673.409422                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88928.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        89500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 113393.868710                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 96996.286329                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123015.549520                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               153                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     76.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              101145                       # number of writebacks
system.l2c.writebacks::total                   101145                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            8                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           12                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         4176                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         4176                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data          453                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          282                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          735                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           99                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           81                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          180                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11239                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8266                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19505                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           29                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19701                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9351                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131214                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2998                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1023                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6755                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       171082                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           29                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19701                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20590                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131214                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2998                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9289                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6755                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           190587                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           29                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19701                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20590                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131214                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2998                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9289                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6755                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          190587                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14311                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        37997                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19269                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11648                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30917                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39846                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        25959                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        68914                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     10270000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6598500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     16868500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      2606000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1791000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4397000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1537104501                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    699098500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2236203001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      5312000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       219000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1850579001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    988740500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15126263509                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       552500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        79500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    310216001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    108988500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    912899226                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  19303849737                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5312000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       219000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1850579001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2525845001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  15126263509                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       552500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        79500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    310216001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    808087000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    912899226                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21540052738                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5312000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       219000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1850579001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2525845001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15126263509                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       552500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        79500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    310216001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    808087000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    912899226                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21540052738                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    210941500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4060149000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6923000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2100456000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6378469500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    210941500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4060149000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6923000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2100456000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6378469500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.010794                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.055035                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.015608                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.035612                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.034424                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.035067                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.737370                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.840981                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.777991                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.093248                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.036145                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.282152                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.140279                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.137255                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.122462                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.080558                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.470776                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.093248                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.036145                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.282152                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.251398                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.137255                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.122462                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.412331                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.490603                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.093248                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.036145                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.282152                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.251398                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738851                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.137255                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.122462                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.412331                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.578092                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.490603                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22671.081678                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23398.936170                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22950.340136                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26323.232323                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22111.111111                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24427.777778                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136765.237210                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84575.187515                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 114647.680133                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 93933.252170                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105736.338360                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103474.316544                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106538.123167                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112833.902672                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93933.252170                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 122673.385187                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103474.316544                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86993.971364                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113019.527764                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93933.252170                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 122673.385187                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103474.316544                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86993.971364                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113019.527764                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197314.914711                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.133324                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167867.713241                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101896.024695                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80914.364960                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92556.947790                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        505078                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       284284                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          621                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               37997                       # Transaction distribution
system.membus.trans_dist::ReadResp             209330                       # Transaction distribution
system.membus.trans_dist::WriteReq              30917                       # Transaction distribution
system.membus.trans_dist::WriteResp             30917                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       137351                       # Transaction distribution
system.membus.trans_dist::CleanEvict            16880                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            65170                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          38916                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39129                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19493                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        171334                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4604                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13758                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       638434                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       760140                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 833089                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162792                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27516                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18718152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18908748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21226892                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           127972                       # Total snoops (count)
system.membus.snoopTraffic                      36480                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            419691                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.012454                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.110902                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  414464     98.75%     98.75% # Request fanout histogram
system.membus.snoop_fanout::1                    5227      1.25%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              419691                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81605499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11449000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           986014542                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1099737525                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            7231369                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1045202                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       540825                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       201129                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          29372                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        28126                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1246                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              38000                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            522906                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30917                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30917                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       362294                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          129646                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          111513                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43869                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         155382                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50631                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50631                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       484911                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4651                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp         3495                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1260717                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       366727                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1627444                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35956648                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5894436                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41851084                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          396095                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15886732                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           901981                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.407509                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.494174                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 535662     59.39%     59.39% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 365073     40.47%     99.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1246      0.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             901981                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          896811514                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2185239                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         675176627                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         261628851                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1835                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2792                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------