path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.004001                       # Number of seconds simulated
sim_ticks                                1004001369000                       # Number of ticks simulated
final_tick                               1004001369000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  89245                       # Simulator instruction rate (inst/s)
host_op_rate                                   114826                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1450204701                       # Simulator tick rate (ticks/s)
host_mem_usage                                 385792                       # Number of bytes of host memory used
host_seconds                                   692.32                       # Real time elapsed on the host
sim_insts                                    61785538                       # Number of instructions simulated
sim_ops                                      79495701                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     44040192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           411712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4381300                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           403392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5239536                       # Number of bytes read from this memory
system.physmem.bytes_read::total             54478052                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       411712                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       403392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          815104                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4277248                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7304336                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       5505024                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6433                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68530                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           18                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6303                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             81894                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               5668214                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66832                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823604                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43864673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           637                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           127                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              410071                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             4363839                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              401784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             5218654                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                54260934                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         410071                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         401784                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             811855                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4260201                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              16932                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2998092                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                7275225                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4260201                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43864673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          127                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             410071                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            4380771                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1147                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             401784                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            8216746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               61536159                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           64                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          382                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              446                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           64                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          382                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          446                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           64                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          382                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             446                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         72797                       # number of replacements
system.l2c.tagsinuse                     53893.248657                       # Cycle average of tags in use
system.l2c.total_refs                         1879341                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        137955                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.622855                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        39653.380215                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       3.693619                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000676                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4026.678241                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2797.052262                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      11.937877                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3656.015551                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          3744.490216                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.605063                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000056                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.061442                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.042680                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000182                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.055786                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.057136                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.822346                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        32914                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         5095                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             390213                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166351                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        51484                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5864                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             597704                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198321                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1447946                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          581607                       # number of Writeback hits
system.l2c.Writeback_hits::total               581607                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1028                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             797                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1825                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           197                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           161                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               358                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48089                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58157                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106246                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         32914                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5095                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              390213                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214440                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         51484                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5864                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              597704                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              256478                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1554192                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        32914                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5095                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             390213                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214440                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        51484                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5864                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             597704                       # number of overall hits
system.l2c.overall_hits::cpu1.data             256478                       # number of overall hits
system.l2c.overall_hits::total                1554192                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6309                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6299                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           18                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6265                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6179                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25082                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5132                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3726                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8858                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          658                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          399                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1057                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63592                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76934                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140526                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6309                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69891                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           18                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6265                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83113                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165608                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6309                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69891                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           18                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6265                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83113                       # number of overall misses
system.l2c.overall_misses::total               165608                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       521500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       112000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    336617000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    331223999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       949000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    333434500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    325052500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1327910499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     20016979                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     27954998                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     47971977                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1517000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7957998                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      9474998                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3416178492                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4069563497                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7485741989                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       521500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       112000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    336617000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3747402491                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       949000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    333434500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4394615997                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8813652488                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       521500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       112000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    336617000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3747402491                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       949000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    333434500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4394615997                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8813652488                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        32924                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5097                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         396522                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         172650                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        51502                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5864                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         603969                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204500                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1473028                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       581607                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           581607                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6160                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4523                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10683                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          855                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          560                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1415                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111681                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135091                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246772                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        32924                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5097                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          396522                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284331                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        51502                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5864                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          603969                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          339591                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1719800                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        32924                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5097                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         396522                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284331                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        51502                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5864                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         603969                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         339591                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1719800                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000304                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000392                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015911                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036484                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000350                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010373                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030215                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017028                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.833117                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.823790                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.829168                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.769591                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.712500                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.746996                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.569408                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.569498                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.569457                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000304                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000392                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.245809                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000350                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010373                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.244744                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.096295                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000304                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000392                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.245809                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000350                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010373                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.244744                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.096295                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52150                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        56000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53355.048344                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52583.584537                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52722.222222                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53221.787709                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52606.004208                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52942.767682                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3900.424591                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7502.683306                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5415.666855                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2305.471125                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 19944.857143                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  8964.047304                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53720.255567                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52896.814113                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53269.444722                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        56000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53355.048344                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 53617.811893                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52722.222222                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53221.787709                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52875.193977                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53219.968166                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        56000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53355.048344                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 53617.811893                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52722.222222                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53221.787709                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52875.193977                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53219.968166                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66832                       # number of writebacks
system.l2c.writebacks::total                    66832                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6302                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6262                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           18                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6258                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6155                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25007                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5132                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3726                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8858                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          658                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          399                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1057                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63592                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76934                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140526                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6302                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69854                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           18                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6258                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83089                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165533                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6302                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69854                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           18                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6258                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83089                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165533                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        88000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    259390500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253074999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       729000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    256738000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    248671000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1019091499                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    205375466                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    149167996                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    354543462                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     26341496                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     15988493                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     42329989                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2637739492                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3117564497                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5755303989                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        88000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    259390500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2890814491                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       729000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    256738000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3366235497                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6774395488                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        88000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    259390500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2890814491                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       729000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    256738000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3366235497                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6774395488                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5539000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12385867978                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2149000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154396291480                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166789847458                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1090238997                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31486348998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  32576587995                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5539000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13476106975                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2149000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185882640478                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199366435453                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000304                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000392                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015893                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036270                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000350                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010361                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030098                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016977                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.833117                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.823790                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.829168                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.769591                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.712500                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.746996                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569408                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.569498                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.569457                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000304                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000392                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015893                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.245678                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000350                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010361                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.244674                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.096251                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000304                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000392                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015893                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.245678                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000350                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010361                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.244674                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.096251                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41160.028562                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40414.404184                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41025.567274                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40401.462226                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40752.249330                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40018.602104                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.352120                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.227139                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40032.668693                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40071.411028                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.293283                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41479.108882                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40522.584254                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40955.438773                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41160.028562                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41383.664371                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41025.567274                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40513.611874                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40924.743030                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41160.028562                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41383.664371                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41025.567274                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40924.743030                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8992964                       # DTB read hits
system.cpu0.dtb.read_misses                     35495                       # DTB read misses
system.cpu0.dtb.write_hits                    5204763                       # DTB write hits
system.cpu0.dtb.write_misses                     6364                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2149                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1250                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   357                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      536                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 9028459                       # DTB read accesses
system.cpu0.dtb.write_accesses                5211127                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14197727                       # DTB hits
system.cpu0.dtb.misses                          41859                       # DTB misses
system.cpu0.dtb.accesses                     14239586                       # DTB accesses
system.cpu0.itb.inst_hits                     4345219                       # ITB inst hits
system.cpu0.itb.inst_misses                      5468                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1393                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1660                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4350687                       # ITB inst accesses
system.cpu0.itb.hits                          4345219                       # DTB hits
system.cpu0.itb.misses                           5468                       # DTB misses
system.cpu0.itb.accesses                      4350687                       # DTB accesses
system.cpu0.numCycles                        69454344                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 6140299                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           4680843                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            325697                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              3967848                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 3011514                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  689087                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              31971                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          11903950                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32719278                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6140299                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3700601                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7697719                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1567081                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     66811                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              21663795                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4784                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        55267                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        90495                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4343360                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               170443                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2579                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          42607741                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.991445                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.370542                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                34918154     81.95%     81.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  615023      1.44%     83.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  811777      1.91%     85.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  689946      1.62%     86.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  788421      1.85%     88.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  570027      1.34%     90.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  709248      1.66%     91.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  365635      0.86%     92.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3139510      7.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            42607741                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.088408                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.471090                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12410407                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             21637687                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6924723                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               574768                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1060156                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              960041                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                65781                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40808812                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               215037                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1060156                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12993427                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5870248                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      13615125                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6864393                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2204392                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              39624437                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 2198                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                433654                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1244123                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents              41                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39987634                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            178950817                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       178916692                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34125                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31114791                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8872842                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            451750                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        410482                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5405254                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7790925                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5788375                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1121917                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1222446                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  37402937                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             939151                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37702557                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            87742                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6716452                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     14173286                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        260083                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     42607741                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.884876                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.498206                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           27166804     63.76%     63.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5957097     13.98%     77.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3214078      7.54%     85.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2477962      5.82%     91.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2111115      4.95%     96.06% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             940986      2.21%     98.26% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             497762      1.17%     99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             188040      0.44%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              53897      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       42607741                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  24897      2.34%      2.34% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   455      0.04%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                841667     79.11%     81.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               196890     18.51%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52279      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22610692     59.97%     60.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48707      0.13%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           696      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9470500     25.12%     85.36% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5519656     14.64%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37702557                       # Type of FU issued
system.cpu0.iq.rate                          0.542839                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1063909                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028218                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         119197860                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         45066260                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34725350                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8284                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4664                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3878                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38709880                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4307                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          311315                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1483597                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3551                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13024                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       603760                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2189792                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5367                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1060156                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4217100                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                98020                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           38461133                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            95338                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7790925                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5788375                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            610075                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39436                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 2994                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13024                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        172050                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       129143                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              301193                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             37281122                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9309198                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           421435                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       119045                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14772448                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4922535                       # Number of branches executed
system.cpu0.iew.exec_stores                   5463250                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.536772                       # Inst execution rate
system.cpu0.iew.wb_sent                      37065432                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34729228                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18441672                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35371865                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.500030                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.521366                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6577828                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         679068                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           261125                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     41583448                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.756316                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.712971                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     29716852     71.46%     71.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5893148     14.17%     85.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1935709      4.65%     90.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       983715      2.37%     92.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       787040      1.89%     94.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       514741      1.24%     95.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       394337      0.95%     96.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       216625      0.52%     97.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1141281      2.74%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     41583448                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23837222                       # Number of instructions committed
system.cpu0.commit.committedOps              31450221                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11491943                       # Number of memory references committed
system.cpu0.commit.loads                      6307328                       # Number of loads committed
system.cpu0.commit.membars                     231960                       # Number of memory barriers committed
system.cpu0.commit.branches                   4279027                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27769802                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489719                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1141281                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    77601886                       # The number of ROB reads
system.cpu0.rob.rob_writes                   77118702                       # The number of ROB writes
system.cpu0.timesIdled                         360842                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26846603                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  1938505291                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23756480                       # Number of Instructions Simulated
system.cpu0.committedOps                     31369479                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23756480                       # Number of Instructions Simulated
system.cpu0.cpi                              2.923596                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.923596                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.342045                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.342045                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               173851540                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34503400                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3265                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     914                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               46745590                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                520572                       # number of misc regfile writes
system.cpu0.icache.replacements                396597                       # number of replacements
system.cpu0.icache.tagsinuse               510.934010                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3914161                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                397109                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.856641                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            7097415000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.934010                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.997918                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.997918                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3914161                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3914161                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3914161                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3914161                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3914161                       # number of overall hits
system.cpu0.icache.overall_hits::total        3914161                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       429060                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       429060                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       429060                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        429060                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       429060                       # number of overall misses
system.cpu0.icache.overall_misses::total       429060                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5859924996                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5859924996                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5859924996                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5859924996                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5859924996                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5859924996                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4343221                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4343221                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4343221                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4343221                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4343221                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4343221                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.098788                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.098788                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.098788                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.098788                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.098788                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.098788                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.588673                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.588673                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.588673                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13657.588673                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.588673                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13657.588673                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2603                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              172                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.133721                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31940                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        31940                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        31940                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        31940                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        31940                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        31940                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       397120                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       397120                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       397120                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       397120                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       397120                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       397120                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4781055496                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4781055496                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4781055496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4781055496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4781055496                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4781055496                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8271000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      8271000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.091434                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.091434                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.091434                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.091434                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.091434                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.091434                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12039.321857                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12039.321857                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12039.321857                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12039.321857                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12039.321857                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12039.321857                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                275715                       # number of replacements
system.cpu0.dcache.tagsinuse               460.505640                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9383873                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                276227                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.971599                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              50121000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   460.505640                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.899425                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.899425                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5832717                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5832717                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3162819                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3162819                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174349                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       174349                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171411                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       171411                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8995536                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8995536                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8995536                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8995536                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       389324                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       389324                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1581862                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1581862                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8809                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8809                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7464                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7464                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1971186                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1971186                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1971186                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1971186                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5380617500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5380617500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  64543979864                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  64543979864                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     88840500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     88840500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     65914500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     65914500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  69924597364                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  69924597364                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  69924597364                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  69924597364                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6222041                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6222041                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4744681                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4744681                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       183158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       178875                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       178875                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10966722                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10966722                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10966722                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10966722                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062572                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.062572                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333397                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.333397                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048095                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048095                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.041727                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.041727                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.179742                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.179742                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.179742                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.179742                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10085.196958                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10085.196958                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8830.988746                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8830.988746                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35473.363429                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35473.363429                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35473.363429                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35473.363429                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         7710                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3643                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              580                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             95                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.293103                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    38.347368                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256563                       # number of writebacks
system.cpu0.dcache.writebacks::total           256563                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       201019                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       201019                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1451459                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1451459                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          444                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          444                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1652478                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1652478                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1652478                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1652478                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188305                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188305                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130403                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130403                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8365                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8365                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7460                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7460                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       318708                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       318708                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       318708                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       318708                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2330576500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2330576500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4457768490                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4457768490                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     67402500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     67402500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     50994500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     50994500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6788344990                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6788344990                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6788344990                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6788344990                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13509879500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13509879500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1216585395                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1216585395                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14726464895                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14726464895                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030264                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030264                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027484                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027484                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.045671                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.045671                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.041705                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.041705                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029061                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029061                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029061                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029061                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8057.680813                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8057.680813                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6835.723861                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6835.723861                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    43128318                       # DTB read hits
system.cpu1.dtb.read_misses                     43709                       # DTB read misses
system.cpu1.dtb.write_hits                    6848528                       # DTB write hits
system.cpu1.dtb.write_misses                    11704                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2308                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     3032                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   376                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      614                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                43172027                       # DTB read accesses
system.cpu1.dtb.write_accesses                6860232                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49976846                       # DTB hits
system.cpu1.dtb.misses                          55413                       # DTB misses
system.cpu1.dtb.accesses                     50032259                       # DTB accesses
system.cpu1.itb.inst_hits                     9000425                       # ITB inst hits
system.cpu1.itb.inst_misses                      6008                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1553                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1639                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 9006433                       # ITB inst accesses
system.cpu1.itb.hits                          9000425                       # DTB hits
system.cpu1.itb.misses                           6008                       # DTB misses
system.cpu1.itb.accesses                      9006433                       # DTB accesses
system.cpu1.numCycles                       411196854                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 9419862                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           7750034                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            456519                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              6563236                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 5515830                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  808543                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              49558                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          20407169                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      70137907                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9419862                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6324373                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14954252                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                4469714                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     69962                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              78537497                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                4608                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        48031                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       137349                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          105                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8998373                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               846947                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3472                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         117207584                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.722166                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.072596                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               102261187     87.25%     87.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  819653      0.70%     87.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  985556      0.84%     88.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 2033886      1.74%     90.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1605966      1.37%     91.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  588504      0.50%     92.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2242580      1.91%     94.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  432923      0.37%     94.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 6237329      5.32%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           117207584                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022908                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.170570                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                22086254                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             78170196                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 13474165                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               527031                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2949938                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1142917                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               100567                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              79224649                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               333390                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2949938                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                23604711                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               32726720                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      41122515                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 12389079                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4414621                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              72870010                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                19270                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                676690                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3162757                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           33999                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           77285870                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            335898709                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       335839792                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            58917                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49079142                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                28206728                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            460869                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        403889                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7994466                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            13706939                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8341114                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1036889                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1489334                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  65799753                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1184242                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 90434427                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           105475                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       18495331                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     52692216                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        284904                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    117207584                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.771575                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.509324                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           86216438     73.56%     73.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8629120      7.36%     80.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4443515      3.79%     84.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3900369      3.33%     88.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10705508      9.13%     97.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1918417      1.64%     98.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1028985      0.88%     99.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             292713      0.25%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              72519      0.06%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      117207584                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  27077      0.34%      0.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   994      0.01%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7551420     96.03%     96.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               284170      3.61%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           313737      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             38536009     42.61%     42.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59463      0.07%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  9      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 3      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1448      0.00%     43.03% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     43.03% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     43.03% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.03% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            44313821     49.00%     92.03% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7209923      7.97%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              90434427                       # Type of FU issued
system.cpu1.iq.rate                          0.219930                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7863661                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.086954                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         306085964                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         85487883                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     54343960                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14808                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8052                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6813                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              97976579                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7772                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          344186                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3955729                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         4256                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17131                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1493245                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31918877                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      1021818                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2949938                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               24820563                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               368762                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           67089139                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           132396                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             13706939                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8341114                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            882128                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 65563                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3455                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17131                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        238596                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       168339                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              406935                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             87595702                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43496570                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2838725                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       105144                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50630638                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7094868                       # Number of branches executed
system.cpu1.iew.exec_stores                   7134068                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.213026                       # Inst execution rate
system.cpu1.iew.wb_sent                      86451134                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     54350773                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30183399                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53726330                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.132177                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.561799                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       18453809                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         899338                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           357846                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    114304625                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.421644                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.382099                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     97479553     85.28%     85.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8276936      7.24%     92.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2163829      1.89%     94.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1249082      1.09%     95.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1246649      1.09%     96.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       573488      0.50%     97.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1001794      0.88%     97.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       527131      0.46%     98.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1786163      1.56%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    114304625                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38098697                       # Number of instructions committed
system.cpu1.commit.committedOps              48195861                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16599079                       # Number of memory references committed
system.cpu1.commit.loads                      9751210                       # Number of loads committed
system.cpu1.commit.membars                     196398                       # Number of memory barriers committed
system.cpu1.commit.branches                   5978782                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42713997                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              536442                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1786163                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   178079063                       # The number of ROB reads
system.cpu1.rob.rob_writes                  136331127                       # The number of ROB writes
system.cpu1.timesIdled                        1409981                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      293989270                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1596154251                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38029058                       # Number of Instructions Simulated
system.cpu1.committedOps                     48126222                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             38029058                       # Number of Instructions Simulated
system.cpu1.cpi                             10.812702                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.812702                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092484                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092484                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               391789649                       # number of integer regfile reads
system.cpu1.int_regfile_writes               57184516                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4895                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2332                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               89371872                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                414539                       # number of misc regfile writes
system.cpu1.icache.replacements                604043                       # number of replacements
system.cpu1.icache.tagsinuse               477.396851                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 8346622                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                604555                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 13.806224                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74944474500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   477.396851                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.932416                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.932416                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      8346622                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        8346622                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      8346622                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         8346622                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      8346622                       # number of overall hits
system.cpu1.icache.overall_hits::total        8346622                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       651698                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       651698                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       651698                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        651698                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       651698                       # number of overall misses
system.cpu1.icache.overall_misses::total       651698                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8706583495                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8706583495                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8706583495                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8706583495                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8706583495                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8706583495                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8998320                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8998320                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8998320                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8998320                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8998320                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8998320                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.072424                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.072424                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.072424                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.072424                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.072424                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.072424                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13359.843816                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13359.843816                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13359.843816                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13359.843816                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13359.843816                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13359.843816                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         1860                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              164                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.341463                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        47118                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        47118                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        47118                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        47118                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        47118                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        47118                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       604580                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       604580                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       604580                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       604580                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       604580                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       604580                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7117577996                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7117577996                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7117577996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7117577996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7117577996                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7117577996                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3208500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3208500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3208500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3208500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067188                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067188                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067188                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.067188                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067188                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.067188                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.764557                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11772.764557                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11772.764557                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11772.764557                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11772.764557                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11772.764557                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                360631                       # number of replacements
system.cpu1.dcache.tagsinuse               472.241123                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                12789913                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                361011                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 35.428042                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           71012585000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   472.241123                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.922346                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.922346                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8401496                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8401496                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4150430                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4150430                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       102060                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       102060                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        98301                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        98301                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12551926                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12551926                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12551926                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12551926                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       394540                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       394540                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1551061                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1551061                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14054                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14054                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10582                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10582                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1945601                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1945601                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1945601                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1945601                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5828870500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   5828870500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  56343693023                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  56343693023                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    129108000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    129108000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     64979500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     64979500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  62172563523                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  62172563523                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  62172563523                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  62172563523                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8796036                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8796036                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5701491                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5701491                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       116114                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       116114                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       108883                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       108883                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14497527                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14497527                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14497527                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14497527                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.044854                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.044854                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272045                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.272045                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121036                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121036                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097187                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097187                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134202                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.134202                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134202                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.134202                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36325.904025                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 36325.904025                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9186.566102                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9186.566102                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  6140.568891                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  6140.568891                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31955.454136                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        23777                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        10847                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3216                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            162                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.393346                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    66.956790                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       325044                       # number of writebacks
system.cpu1.dcache.writebacks::total           325044                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       165979                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       165979                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1389692                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1389692                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1430                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1430                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1555671                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1555671                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1555671                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1555671                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       228561                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       228561                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161369                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161369                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12624                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12624                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10579                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10579                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       389930                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       389930                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       389930                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       389930                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2788566500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2788566500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5142243728                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5142243728                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88146000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88146000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     43823500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     43823500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7930810228                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7930810228                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7930810228                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7930810228                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168983572500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40847570579                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40847570579                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209831143079                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025985                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025985                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028303                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028303                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.108721                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.108721                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097159                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097159                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026896                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026896                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026896                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026896                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6982.414449                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6982.414449                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4142.499291                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4142.499291                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 479854932995                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   43104                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   52217                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------