path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.569716                       # Number of seconds simulated
sim_ticks                                2569716290500                       # Number of ticks simulated
final_tick                               2569716290500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  91215                       # Simulator instruction rate (inst/s)
host_op_rate                                   117813                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3779331614                       # Simulator tick rate (ticks/s)
host_mem_usage                                 391064                       # Number of bytes of host memory used
host_seconds                                   679.94                       # Real time elapsed on the host
sim_insts                                    62020337                       # Number of instructions simulated
sim_ops                                      80105642                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           383040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4310004                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           438272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5311600                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129982372                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       383040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       438272                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          821312                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4277376                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7306512                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              5985                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             67416                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             83020                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15105505                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66834                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               824118                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46517845                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           249                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              149059                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1677230                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           374                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              170553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2066999                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50582382                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         149059                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         170553                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             319612                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1664532                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6616                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1172167                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2843315                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1664532                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46517845                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          249                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             149059                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1683845                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          374                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             170553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3239165                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53425697                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          320                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          320                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          125                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              149                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          125                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          149                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          125                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             149                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         72902                       # number of replacements
system.l2c.tagsinuse                     52914.655952                       # Cycle average of tags in use
system.l2c.total_refs                         2024041                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        138037                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         14.663032                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        37560.940783                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       3.394478                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000176                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4213.394018                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2969.636370                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      12.170115                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.970249                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          4028.311406                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          4125.838357                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.573134                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000052                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.064291                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.045313                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000186                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.061467                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.062955                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.807414                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        50859                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         5940                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             395141                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             161674                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        79156                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6590                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             619717                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             202375                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1521452                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          646021                       # number of Writeback hits
system.l2c.Writeback_hits::total               646021                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             861                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1085                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1946                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           209                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           164                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               373                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            50919                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            55813                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106732                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         50859                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5940                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              395141                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              212593                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         79156                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6590                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              619717                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              258188                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1628184                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        50859                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5940                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             395141                       # number of overall hits
system.l2c.overall_hits::cpu0.data             212593                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        79156                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6590                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             619717                       # number of overall hits
system.l2c.overall_hits::cpu1.data             258188                       # number of overall hits
system.l2c.overall_hits::total                1628184                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5853                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6139                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6809                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6537                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25366                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5294                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4767                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             10061                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          775                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          577                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1352                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          62637                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          77700                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140337                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5853                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             68776                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6809                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             84237                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165703                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5853                       # number of overall misses
system.l2c.overall_misses::cpu0.data            68776                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6809                       # number of overall misses
system.l2c.overall_misses::cpu1.data            84237                       # number of overall misses
system.l2c.overall_misses::total               165703                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       521500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        53000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    306091000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    320158000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       783000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    356464000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    341134500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1325309000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     18664500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     31259000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     49923500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1307000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6272500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      7579500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3285106999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4081053500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7366160499                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       521500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        53000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    306091000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3605264999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       783000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       104000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    356464000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4422188000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8691469499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       521500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        53000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    306091000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3605264999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       783000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       104000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    356464000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4422188000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8691469499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        50869                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5941                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         400994                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         167813                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        79171                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6592                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         626526                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         208912                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1546818                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       646021                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           646021                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6155                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5852                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           12007                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          984                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          741                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1725                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       113556                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       133513                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247069                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        50869                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5941                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          400994                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          281369                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        79171                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6592                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          626526                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          342425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1793887                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        50869                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5941                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         400994                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         281369                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        79171                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6592                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         626526                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         342425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1793887                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014596                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036582                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010868                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.031291                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016399                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.860114                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.814593                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.837928                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787602                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.778677                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.783768                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.551596                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.581966                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.568007                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014596                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244433                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010868                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.246001                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.092371                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014596                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244433                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010868                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.246001                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.092371                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52150                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        53000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52296.429182                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52151.490471                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52200                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52351.887208                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52185.176687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52247.457226                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3525.595013                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6557.373610                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4962.081304                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1686.451613                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10870.883882                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5606.139053                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52446.748711                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52523.211068                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52489.083413                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        53000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52296.429182                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52200                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52452.095007                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        53000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52200                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52452.095007                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66834                       # number of writebacks
system.l2c.writebacks::total                    66834                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            25                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                73                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 73                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                73                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5849                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6101                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6803                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6512                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25293                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5294                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4767                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        10061                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          775                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          577                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1352                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        62637                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        77700                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140337                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5849                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        68738                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6803                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        84212                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165630                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5849                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        68738                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6803                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        84212                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165630                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        41000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    234434500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    244221500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    273121500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    260689500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1013589000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    211949500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    190864500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    402814000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31033000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23118500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     54151500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2507451999                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3115007000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5622458999                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        41000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    234434500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2751673499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    273121500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3375696500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6636047999                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        41000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    234434500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2751673499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    273121500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3375696500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6636047999                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5501500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  21616744000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2009500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    713445484                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31812115712                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  32525561196                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5501500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  22330189484                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2009500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 164486076196                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036356                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031171                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016352                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.860114                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.814593                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.837928                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787602                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.778677                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.783768                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.551596                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.581966                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.568007                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244298                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.245928                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.092330                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244298                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.245928                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.092330                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40065.495375                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40065.495375                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12222008                       # DTB read hits
system.cpu0.dtb.read_misses                     34799                       # DTB read misses
system.cpu0.dtb.write_hits                    5155654                       # DTB write hits
system.cpu0.dtb.write_misses                     4970                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2546                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1270                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   369                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      661                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12256807                       # DTB read accesses
system.cpu0.dtb.write_accesses                5160624                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         17377662                       # DTB hits
system.cpu0.dtb.misses                          39769                       # DTB misses
system.cpu0.dtb.accesses                     17417431                       # DTB accesses
system.cpu0.itb.inst_hits                     4312814                       # ITB inst hits
system.cpu0.itb.inst_misses                      5659                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1615                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1550                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4318473                       # ITB inst accesses
system.cpu0.itb.hits                          4312814                       # DTB hits
system.cpu0.itb.misses                           5659                       # DTB misses
system.cpu0.itb.accesses                      4318473                       # DTB accesses
system.cpu0.numCycles                        91755333                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 5952266                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           4505075                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            304047                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              3800923                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 2764349                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  686219                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              29965                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          12225669                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      31634782                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    5952266                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3450568                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7438203                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1498517                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     86111                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              25429329                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                5796                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        56004                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        89121                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          253                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4310960                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               168036                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2895                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          46396814                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.887686                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.274992                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                38966492     83.99%     83.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  608768      1.31%     85.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  793531      1.71%     87.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  678621      1.46%     88.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  615872      1.33%     89.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  550838      1.19%     90.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  680018      1.47%     92.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  365085      0.79%     93.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3137589      6.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            46396814                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.064871                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.344773                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12690058                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             25456221                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6703467                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               545759                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1001309                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              958631                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                66338                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              39766150                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               219028                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1001309                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                13289637                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                7972865                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      15343248                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6631332                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2158423                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38589176                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  848                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                416461                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1242307                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             106                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           38596643                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175113710                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       175069465                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            44245                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30775876                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 7820767                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            452714                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        409285                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5195885                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7781233                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5757511                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1120127                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1192401                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36577178                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             791583                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 40176979                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            83237                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5967561                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13599049                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        145097                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     46396814                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.865943                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.513269                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           30520128     65.78%     65.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5937185     12.80%     78.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3046653      6.57%     85.14% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2264959      4.88%     90.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2893477      6.24%     96.26% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             928258      2.00%     98.26% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             563400      1.21%     99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             186019      0.40%     99.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              56735      0.12%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       46396814                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  26385      1.46%      1.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   453      0.03%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      1.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               1567613     86.92%     88.41% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               209022     11.59%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            25309      0.06%      0.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             21935197     54.60%     54.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48039      0.12%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 3      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           725      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     54.78% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            12687286     31.58%     86.36% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5480393     13.64%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              40176979                       # Type of FU issued
system.cpu0.iq.rate                          0.437871                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1803473                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.044888                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         128665759                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         43343315                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34031138                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11205                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6096                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         4927                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              41949154                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   5989                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          311358                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1414489                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         4027                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13694                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       607908                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      5397304                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5188                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1001309                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                6077720                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               124694                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37485087                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            95046                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7781233                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5757511                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            467034                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 52649                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4313                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13694                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        153875                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       138964                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              292839                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             39778235                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             12530314                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           398744                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       116326                       # number of nop insts executed
system.cpu0.iew.exec_refs                    17957262                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4780864                       # Number of branches executed
system.cpu0.iew.exec_stores                   5426948                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.433525                       # Inst execution rate
system.cpu0.iew.wb_sent                      39572300                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34036065                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18213937                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35297892                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.370944                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.516006                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      23601687                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps        31186721                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        6143896                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         646486                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           256571                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     45430638                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.686469                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.654503                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     33717084     74.22%     74.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5850006     12.88%     87.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1884843      4.15%     91.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       960822      2.11%     93.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       731888      1.61%     94.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       454898      1.00%     95.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       476885      1.05%     97.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       212485      0.47%     97.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1141727      2.51%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     45430638                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23601687                       # Number of instructions committed
system.cpu0.commit.committedOps              31186721                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11516347                       # Number of memory references committed
system.cpu0.commit.loads                      6366744                       # Number of loads committed
system.cpu0.commit.membars                     228774                       # Number of memory barriers committed
system.cpu0.commit.branches                   4268909                       # Number of branches committed
system.cpu0.commit.fp_insts                      4838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27636133                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              492618                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1141727                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    80832744                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75665562                       # The number of ROB writes
system.cpu0.timesIdled                         511317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       45358519                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5047039822                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23536584                       # Number of Instructions Simulated
system.cpu0.committedOps                     31121618                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23536584                       # Number of Instructions Simulated
system.cpu0.cpi                              3.898413                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        3.898413                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.256515                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.256515                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               183926116                       # number of integer regfile reads
system.cpu0.int_regfile_writes               33429350                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     4511                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     934                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               45525801                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                515221                       # number of misc regfile writes
system.cpu0.icache.replacements                402234                       # number of replacements
system.cpu0.icache.tagsinuse               511.630403                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3875529                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                402746                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.622762                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6260006000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.630403                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.999278                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999278                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3875529                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3875529                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3875529                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3875529                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3875529                       # number of overall hits
system.cpu0.icache.overall_hits::total        3875529                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       435289                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       435289                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       435289                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        435289                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       435289                       # number of overall misses
system.cpu0.icache.overall_misses::total       435289                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6419795491                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6419795491                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   6419795491                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6419795491                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   6419795491                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6419795491                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4310818                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4310818                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4310818                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4310818                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4310818                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4310818                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100976                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100976                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100976                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100976                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100976                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100976                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14748.352223                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14748.352223                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1456992                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              163                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  8938.601227                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks        31582                       # number of writebacks
system.cpu0.icache.writebacks::total            31582                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        32527                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        32527                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        32527                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        32527                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        32527                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        32527                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       402762                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       402762                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       402762                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       402762                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       402762                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       402762                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4809385492                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4809385492                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4809385492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4809385492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4809385492                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4809385492                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7376000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7376000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7376000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7376000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093431                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093431                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093431                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                272390                       # number of replacements
system.cpu0.dcache.tagsinuse               477.646995                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9259935                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                272772                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.947528                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              49645000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   477.646995                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.932904                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.932904                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5751664                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5751664                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3128629                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3128629                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172667                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       172667                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       169954                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       169954                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8880293                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8880293                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8880293                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8880293                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       380393                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       380393                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1568163                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1568163                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9112                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9112                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7881                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7881                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1948556                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1948556                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1948556                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1948556                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5112833000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5112833000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  57745298395                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  57745298395                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100839000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    100839000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     84292000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     84292000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  62858131395                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  62858131395                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  62858131395                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  62858131395                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6132057                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6132057                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4696792                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4696792                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       181779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       181779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       177835                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       177835                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10828849                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10828849                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10828849                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10828849                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062034                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.062034                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333880                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.333880                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.050127                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.050127                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.044316                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.044316                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.179941                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.179941                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.179941                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.179941                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      3762493                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      1470000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              438                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             79                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8590.166667                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       253456                       # number of writebacks
system.cpu0.dcache.writebacks::total           253456                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       195063                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       195063                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1436472                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1436472                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          621                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          621                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1631535                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1631535                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1631535                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1631535                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       185330                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       185330                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131691                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       131691                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8491                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8491                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7877                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7877                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       317021                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       317021                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       317021                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       317021                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2232196000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2232196000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4281157492                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4281157492                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     67651500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     67651500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     60619000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     60619000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6513353492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6513353492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6513353492                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6513353492                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  24166586500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  24166586500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    850308391                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    850308391                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  25016894891                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  25016894891                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030223                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030223                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.028038                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028038                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046711                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046711                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.044294                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.044294                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029276                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029276                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029276                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029276                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7967.436109                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7967.436109                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7695.696331                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7695.696331                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    40314372                       # DTB read hits
system.cpu1.dtb.read_misses                     47835                       # DTB read misses
system.cpu1.dtb.write_hits                    7207214                       # DTB write hits
system.cpu1.dtb.write_misses                    14308                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2204                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     3789                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   426                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      618                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                40362207                       # DTB read accesses
system.cpu1.dtb.write_accesses                7221522                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         47521586                       # DTB hits
system.cpu1.dtb.misses                          62143                       # DTB misses
system.cpu1.dtb.accesses                     47583729                       # DTB accesses
system.cpu1.itb.inst_hits                     9199147                       # ITB inst hits
system.cpu1.itb.inst_misses                      6537                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1398                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1778                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 9205684                       # ITB inst accesses
system.cpu1.itb.hits                          9199147                       # DTB hits
system.cpu1.itb.misses                           6537                       # DTB misses
system.cpu1.itb.accesses                      9205684                       # DTB accesses
system.cpu1.numCycles                       321589455                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 9609219                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           7804241                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            456907                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              6466725                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 5325877                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  844527                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              50619                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          21504333                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      71435147                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9609219                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6170404                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     15136389                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                4734420                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     89053                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              66067639                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5715                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        64771                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       143196                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           87                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  9197098                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               766779                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3914                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         106241109                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.815152                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.196213                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                91113370     85.76%     85.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  835957      0.79%     86.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1038807      0.98%     87.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 2054123      1.93%     89.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1283354      1.21%     90.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  639035      0.60%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2277082      2.14%     93.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  459375      0.43%     93.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 6540006      6.16%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           106241109                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.029880                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.222131                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                23013271                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             65947642                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 13617278                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               534194                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               3128724                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1272359                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               103085                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              80569967                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               342001                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               3128724                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                24438096                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               29197230                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      32706540                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 12706787                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4063732                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              74758294                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2356                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                627503                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2908939                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           45012                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           79187879                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            346602336                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       346555262                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            47074                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             50022423                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                29165455                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            496148                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        429704                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7532124                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            14054260                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8745175                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1095062                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1520090                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  67170682                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             857343                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 88258087                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           108704                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       18559774                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     53338169                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        154632                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    106241109                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.830734                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.556038                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           76008182     71.54%     71.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8446540      7.95%     79.49% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4482838      4.22%     83.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3826420      3.60%     87.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            9985833      9.40%     96.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1963466      1.85%     98.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1174590      1.11%     99.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             267511      0.25%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              85729      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      106241109                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  34820      0.48%      0.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   995      0.01%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               6868408     95.11%     95.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               317335      4.39%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            81809      0.09%      0.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             39074007     44.27%     44.37% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               63191      0.07%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 10      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 5      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1634      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     44.44% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            41444924     46.96%     91.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7592491      8.60%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              88258087                       # Type of FU issued
system.cpu1.iq.rate                          0.274443                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7221558                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.081823                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         290137702                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         86602000                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     55480726                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11865                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6384                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5360                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              95391603                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6233                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          377691                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      4014151                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         6631                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        21303                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1605227                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     28717238                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      1149940                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               3128724                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               22478642                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               328290                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           68173106                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           141945                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             14054260                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8745175                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            539434                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 62530                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3755                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         21303                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        237741                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       202628                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              440369                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             85609132                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             40707747                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2648955                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       145081                       # number of nop insts executed
system.cpu1.iew.exec_refs                    48220727                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7143156                       # Number of branches executed
system.cpu1.iew.exec_stores                   7512980                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.266206                       # Inst execution rate
system.cpu1.iew.wb_sent                      84396881                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     55486086                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30755357                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 55849815                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.172537                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.550680                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      38569031                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps        49069302                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts       19027054                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         702711                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           384240                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    103162057                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.475653                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.464816                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     86125230     83.49%     83.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8314170      8.06%     91.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2284328      2.21%     93.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1318858      1.28%     95.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1066734      1.03%     96.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       616185      0.60%     96.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1058049      1.03%     97.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       494277      0.48%     98.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1884226      1.83%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    103162057                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38569031                       # Number of instructions committed
system.cpu1.commit.committedOps              49069302                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      17180057                       # Number of memory references committed
system.cpu1.commit.loads                     10040109                       # Number of loads committed
system.cpu1.commit.membars                     207982                       # Number of memory barriers committed
system.cpu1.commit.branches                   6108113                       # Number of branches committed
system.cpu1.commit.fp_insts                      5310                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 43785233                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              563417                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1884226                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   168322862                       # The number of ROB reads
system.cpu1.rob.rob_writes                  139443210                       # The number of ROB writes
system.cpu1.timesIdled                        1396987                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      215348346                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4817788385                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38483753                       # Number of Instructions Simulated
system.cpu1.committedOps                     48984024                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             38483753                       # Number of Instructions Simulated
system.cpu1.cpi                              8.356499                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.356499                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.119667                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.119667                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               385614321                       # number of integer regfile reads
system.cpu1.int_regfile_writes               58138574                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     3969                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    1880                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               91635789                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                441645                       # number of misc regfile writes
system.cpu1.icache.replacements                628575                       # number of replacements
system.cpu1.icache.tagsinuse               498.649539                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 8518604                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                629087                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 13.541218                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           73946666000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   498.649539                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.973925                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.973925                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      8518604                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        8518604                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      8518604                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         8518604                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      8518604                       # number of overall hits
system.cpu1.icache.overall_hits::total        8518604                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       678443                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       678443                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       678443                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        678443                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       678443                       # number of overall misses
system.cpu1.icache.overall_misses::total       678443                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9864551499                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9864551499                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9864551499                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9864551499                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9864551499                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9864551499                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      9197047                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      9197047                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      9197047                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      9197047                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      9197047                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      9197047                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073767                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.073767                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073767                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.073767                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073767                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.073767                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14539.985672                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14539.985672                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       932999                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              153                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  6098.032680                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks        30976                       # number of writebacks
system.cpu1.icache.writebacks::total            30976                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49327                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        49327                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        49327                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        49327                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        49327                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        49327                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       629116                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       629116                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       629116                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       629116                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       629116                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       629116                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7390302499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7390302499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7390302499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7390302499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7390302499                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7390302499                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2676000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2676000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2676000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      2676000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.068404                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.068404                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.068404                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                365990                       # number of replacements
system.cpu1.dcache.tagsinuse               486.374853                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                13437990                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                366502                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 36.665530                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           70078369000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   486.374853                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.949951                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.949951                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8795505                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8795505                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4385128                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4385128                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       106581                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       106581                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data       102282                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total       102282                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     13180633                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        13180633                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     13180633                       # number of overall hits
system.cpu1.dcache.overall_hits::total       13180633                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       408153                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       408153                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1582783                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1582783                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13916                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13916                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10800                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10800                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1990936                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1990936                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1990936                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1990936                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5766799000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   5766799000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  55285236443                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  55285236443                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    141367500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    141367500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     89573500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     89573500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  61052035443                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  61052035443                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  61052035443                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  61052035443                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9203658                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9203658                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5967911                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5967911                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       120497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       120497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       113082                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       113082                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     15171569                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     15171569                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     15171569                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     15171569                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.044347                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.044347                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.265216                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.265216                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.115488                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.115488                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095506                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095506                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.131228                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.131228                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.131228                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.131228                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8293.842593                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8293.842593                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     12254574                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      5966500                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3013                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            167                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4067.233322                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       330007                       # number of writebacks
system.cpu1.dcache.writebacks::total           330007                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       172901                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       172901                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1420692                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1420692                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1265                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1265                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1593593                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1593593                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1593593                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1593593                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       235252                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       235252                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162091                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       162091                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12651                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12651                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10796                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10796                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       397343                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       397343                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       397343                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       397343                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2772800000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2772800000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5167139074                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5167139074                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88580000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88580000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57154000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57154000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7939939074                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7939939074                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7939939074                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7939939074                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  41654166350                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  41654166350                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025561                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025561                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027160                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027160                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.104990                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.104990                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095471                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095471                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026190                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026190                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026190                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026190                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7001.818038                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7001.818038                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5293.997777                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5293.997777                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1308136748055                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   42935                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   54742                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------