path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.605644                       # Number of seconds simulated
sim_ticks                                2605643988500                       # Number of ticks simulated
final_tick                               2605643988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  56388                       # Simulator instruction rate (inst/s)
host_op_rate                                    72604                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2339801960                       # Simulator tick rate (ticks/s)
host_mem_usage                                 475216                       # Number of bytes of host memory used
host_seconds                                  1113.62                       # Real time elapsed on the host
sim_insts                                    62794806                       # Number of instructions simulated
sim_ops                                      80853196                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           394240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4377212                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           429184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5246712                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131559796                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       394240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       429184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          823424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4275584                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7304720                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6160                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68468                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6706                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82008                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15302188                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66806                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               824090                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46480075                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           295                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              151302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1679896                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           393                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              164713                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2013595                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50490319                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         151302                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         164713                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             316016                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1640893                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6524                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1156004                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2803422                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1640893                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46480075                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          295                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             151302                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1686421                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          393                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             164713                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3169600                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53293741                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15302188                       # Number of read requests accepted
system.physmem.writeReqs                       824090                       # Number of write requests accepted
system.physmem.readBursts                    15302188                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     824090                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                974626176                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   4713856                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7328128                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131559796                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7304720                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    73654                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709569                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14159                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              956238                       # Per bank write bursts
system.physmem.perBankRdBursts::1              951013                       # Per bank write bursts
system.physmem.perBankRdBursts::2              950196                       # Per bank write bursts
system.physmem.perBankRdBursts::3              950464                       # Per bank write bursts
system.physmem.perBankRdBursts::4              956634                       # Per bank write bursts
system.physmem.perBankRdBursts::5              950822                       # Per bank write bursts
system.physmem.perBankRdBursts::6              949869                       # Per bank write bursts
system.physmem.perBankRdBursts::7              949811                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956681                       # Per bank write bursts
system.physmem.perBankRdBursts::9              951277                       # Per bank write bursts
system.physmem.perBankRdBursts::10             949961                       # Per bank write bursts
system.physmem.perBankRdBursts::11             949024                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956331                       # Per bank write bursts
system.physmem.perBankRdBursts::13             950586                       # Per bank write bursts
system.physmem.perBankRdBursts::14             950041                       # Per bank write bursts
system.physmem.perBankRdBursts::15             949586                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7062                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6963                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7126                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7116                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7811                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7409                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7013                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7004                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7458                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7561                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6914                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6583                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7179                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7101                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7219                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6983                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2605642823000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  163263                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66806                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1074226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1009957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    967065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1078396                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    970167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1034458                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2664402                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2566961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3342237                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    136100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   116220                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   107345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                   103465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    19833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    18840                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18525                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      210                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      112                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3035                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1012463                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      969.866853                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     900.909804                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     207.662919                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24967      2.47%      2.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        21104      2.08%      4.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8681      0.86%      5.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2506      0.25%      5.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2720      0.27%      5.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2029      0.20%      6.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8638      0.85%      6.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1014      0.10%      7.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       940804     92.92%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1012463                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6706                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2270.880853                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    84552.226363                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143         6700     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::262144-524287            1      0.01%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-786431            1      0.01%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.01%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6706                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6706                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.074560                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.020748                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.396636                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3829     57.10%     57.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 48      0.72%     57.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1779     26.53%     84.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                878     13.09%     97.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 53      0.79%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 31      0.46%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 34      0.51%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 40      0.60%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 12      0.18%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6706                       # Writes before turning the bus around for reads
system.physmem.totQLat                   395588666000                       # Total ticks spent queuing
system.physmem.totMemAccLat              681123678500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76142670000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25976.81                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44726.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         374.04                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.94                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.92                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.05                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14234195                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96378                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.16                       # Row buffer hit rate for writes
system.physmem.avgGap                       161577.45                       # Average gap between requests
system.physmem.pageHitRate                      93.40                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2260536385250                       # Time in different power states
system.physmem.memoryStateTime::REF       87007960000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      258093332250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          147                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              172                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          147                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          172                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54224369                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16352672                       # Transaction distribution
system.membus.trans_dist::ReadResp           16352672                       # Transaction distribution
system.membus.trans_dist::WriteReq             769183                       # Transaction distribution
system.membus.trans_dist::WriteResp            769183                       # Transaction distribution
system.membus.trans_dist::Writeback             66806                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35949                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          18292                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14159                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138125                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137746                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384364                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13834                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1976897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4377155                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34654787                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27668                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17753988                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20178873                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141289401                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141289401                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487962500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11808000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy             1796000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17659548997                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4847870095                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37379122644                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    72974                       # number of replacements
system.l2c.tags.tagsinuse                53023.948009                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1873330                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   138152                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.559920                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37706.296895                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.412172                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000364                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4169.126027                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2962.597547                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.621110                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4061.748879                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4107.145016                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.575352                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000083                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063616                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.045206                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000177                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.061977                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.062670                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.809081                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65174                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3154                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9081                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52631                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994476                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18850449                       # Number of tag accesses
system.l2c.tags.data_accesses                18850449                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        22712                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4441                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             393676                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             165723                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        33196                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5802                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             607870                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             201576                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1434996                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          583128                       # number of Writeback hits
system.l2c.Writeback_hits::total               583128                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1123                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             727                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1850                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           207                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           158                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               365                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            47567                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            59393                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106960                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         22712                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4441                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              393676                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              213290                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         33196                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5802                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              607870                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              260969                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1541956                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        22712                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4441                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             393676                       # number of overall hits
system.l2c.overall_hits::cpu0.data             213290                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        33196                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5802                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             607870                       # number of overall hits
system.l2c.overall_hits::cpu1.data             260969                       # number of overall hits
system.l2c.overall_hits::total                1541956                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6041                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6321                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6670                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6363                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25425                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5691                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4436                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             10127                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          767                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          589                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1356                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63545                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76877                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140422                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6041                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69866                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6670                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83240                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165847                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           12                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6041                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69866                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6670                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83240                       # number of overall misses
system.l2c.overall_misses::total               165847                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1149750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       368000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    435967250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    468270999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1231000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    485141500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    483349999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1875478498                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9144593                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12320478                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21465071                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       441981                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3192363                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3634344                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4462150559                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   6003353008                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10465503567                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1149750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       368000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    435967250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4930421558                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1231000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    485141500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6486703007                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12340982065                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1149750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       368000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    435967250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4930421558                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1231000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    485141500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6486703007                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12340982065                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        22724                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4443                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         399717                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         172044                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        33212                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5802                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         614540                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         207939                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1460421                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       583128                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           583128                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6814                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5163                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           11977                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          974                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          747                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1721                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111112                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       136270                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247382                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        22724                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4443                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          399717                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          283156                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        33212                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5802                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          614540                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          344209                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1707803                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        22724                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4443                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         399717                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         283156                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        33212                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5802                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         614540                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         344209                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1707803                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015113                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036741                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010854                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030600                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017409                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.835192                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.859190                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.845537                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787474                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.788487                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.787914                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.571900                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.564152                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567632                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015113                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.246740                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010854                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.241830                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.097111                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000528                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000450                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015113                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.246740                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000482                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010854                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.241830                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.097111                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       184000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72168.059924                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74081.790698                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72734.857571                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75962.596102                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73765.132665                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1606.851696                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2777.384581                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2119.588328                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   576.246415                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5419.971138                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2680.194690                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70220.325108                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78090.365233                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74528.945372                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72168.059924                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70569.684224                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72734.857571                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77927.715125                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74411.849868                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95812.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       184000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72168.059924                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70569.684224                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76937.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72734.857571                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77927.715125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74411.849868                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66806                       # number of writebacks
system.l2c.writebacks::total                    66806                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            26                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            26                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           12                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6036                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6284                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6663                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6337                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25350                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5691                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4436                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        10127                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          767                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          589                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1356                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63545                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76877                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140422                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6036                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69829                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6663                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83214                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165772                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6036                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69829                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6663                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83214                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165772                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       343500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    359682000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    387178249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    400959000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    402487249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1552685748                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57050142                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44722851                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    101772993                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7680764                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5892086                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     13572850                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3668395937                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5048276480                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8716672417                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       343500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    359682000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4055574186                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    400959000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5450763729                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10269358165                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1001750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       343500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    359682000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4055574186                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1034000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    400959000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5450763729                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10269358165                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6890749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12335372988                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2843750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881314980                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1073382998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16528122341                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17601505339                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6890749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13408755986                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2843750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184827927806                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036526                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030475                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017358                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.835192                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.859190                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.845537                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787474                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.788487                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.787914                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.571900                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564152                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567632                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.246610                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.241754                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.097067                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000528                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000450                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015101                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.246610                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000482                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010842                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.241754                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.097067                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61613.343253                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63513.847089                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61249.930888                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.625198                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61948.689556                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       171750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        64625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61948.689556                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58718575                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2740966                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2740965                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            769183                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           769183                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           583128                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           35123                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         18657                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          53780                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           259272                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          259272                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       800244                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073141                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        13760                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        56807                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1229764                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820581                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15635                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        75586                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8085518                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25589824                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34686241                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        17772                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        90896                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39333696                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48239320                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        23208                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132848                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148113805                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148113805                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4885896                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4921313376                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1803473389                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1514355955                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9338456                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          34226949                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        2770248418                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        3257977460                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           9851958                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy          42643941                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      47398342                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322915                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322915                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8836                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          736                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2384364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32661996                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17672                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2392677                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123503205                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123503205                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4424000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               440000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2376281000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         38174483356                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6117114                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4670626                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           296157                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3842728                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2949969                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            76.767572                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 683314                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28361                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8969403                       # DTB read hits
system.cpu0.dtb.read_misses                     29343                       # DTB read misses
system.cpu0.dtb.write_hits                    5210557                       # DTB write hits
system.cpu0.dtb.write_misses                     5731                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1733                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1050                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   278                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      596                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8998746                       # DTB read accesses
system.cpu0.dtb.write_accesses                5216288                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14179960                       # DTB hits
system.cpu0.dtb.misses                          35074                       # DTB misses
system.cpu0.dtb.accesses                     14215034                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     4277605                       # ITB inst hits
system.cpu0.itb.inst_misses                      5145                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1215                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1426                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4282750                       # ITB inst accesses
system.cpu0.itb.hits                          4277605                       # DTB hits
system.cpu0.itb.misses                           5145                       # DTB misses
system.cpu0.itb.accesses                      4282750                       # DTB accesses
system.cpu0.numCycles                        70248238                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11931842                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32451975                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6117114                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3633283                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7612739                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1460869                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     60951                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              20309232                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                6063                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        46682                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1377400                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          299                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4276074                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               156796                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2089                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          42393450                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.988978                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.370199                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                34788183     82.06%     82.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  572054      1.35%     83.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  825907      1.95%     85.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  686377      1.62%     86.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  779180      1.84%     88.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  565083      1.33%     90.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  677221      1.60%     91.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  357838      0.84%     92.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3141607      7.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            42393450                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.087079                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.461961                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12487890                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             21493629                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6874468                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               552722                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                984741                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              950951                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64626                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40558878                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               212020                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                984741                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                13064503                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5883311                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      13498743                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6804692                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2157460                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              39446559                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  311                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                442642                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1180293                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             145                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39856275                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            180582545                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       163877057                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             4135                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31488132                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8368142                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            460013                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        416638                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5509006                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7758217                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5771757                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1123661                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1193308                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  37348678                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             906063                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37718806                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            82800                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6312476                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13233696                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        257258                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     42393450                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.889732                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.506737                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           27027469     63.75%     63.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5904750     13.93%     77.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3167008      7.47%     85.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2470651      5.83%     90.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2117188      4.99%     95.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             941206      2.22%     98.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             520081      1.23%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             187957      0.44%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              57140      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       42393450                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  26875      2.51%      2.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   458      0.04%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                836202     77.98%     80.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               208765     19.47%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            14551      0.04%      0.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22694630     60.17%     60.21% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               47979      0.13%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 14      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc             10      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc           12      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9430195     25.00%     85.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5530734     14.66%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37718806                       # Type of FU issued
system.cpu0.iq.rate                          0.536936                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1072300                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028429                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         119012569                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         44575137                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34852276                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8350                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4654                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3869                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38772197                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4358                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          316382                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1375838                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2694                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13105                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       538991                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2149907                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5937                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                984741                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4273547                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                99764                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           38372810                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            83727                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7758217                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5771757                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            578717                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 40350                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3282                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13105                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        151036                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       117828                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              268864                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             37337135                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9286340                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           381671                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       118069                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14769450                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4962843                       # Number of branches executed
system.cpu0.iew.exec_stores                   5483110                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.531503                       # Inst execution rate
system.cpu0.iew.wb_sent                      37142523                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34856145                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18592748                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35683758                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.496185                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.521042                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6125993                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         648805                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           232656                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     41408709                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.767702                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.726975                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     29445863     71.11%     71.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5939620     14.34%     85.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1940870      4.69%     90.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1013361      2.45%     92.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       759448      1.83%     94.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       515426      1.24%     95.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       408347      0.99%     96.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       223076      0.54%     97.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1162698      2.81%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     41408709                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            24071577                       # Number of instructions committed
system.cpu0.commit.committedOps              31789563                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11615145                       # Number of memory references committed
system.cpu0.commit.loads                      6382379                       # Number of loads committed
system.cpu0.commit.membars                     231812                       # Number of memory barriers committed
system.cpu0.commit.branches                   4351457                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 28135168                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              498959                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        20133954     63.34%     63.34% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          39784      0.13%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc          680      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        6382379     20.08%     83.54% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5232766     16.46%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         31789563                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1162698                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    77292791                       # The number of ROB reads
system.cpu0.rob.rob_writes                   76817595                       # The number of ROB writes
system.cpu0.timesIdled                         365665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27854788                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5140997105                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23990835                       # Number of Instructions Simulated
system.cpu0.committedOps                     31708821                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.928128                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.928128                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.341515                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.341515                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               174285855                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34604955                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3294                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     912                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               79299010                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                500883                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           399739                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.543627                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            3844274                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           400251                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.604658                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7097393250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.543627                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999109                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999109                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          4676219                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         4676219                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      3844274                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3844274                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3844274                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3844274                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3844274                       # number of overall hits
system.cpu0.icache.overall_hits::total        3844274                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       431668                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       431668                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       431668                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        431668                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       431668                       # number of overall misses
system.cpu0.icache.overall_misses::total       431668                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5966691765                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5966691765                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5966691765                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5966691765                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5966691765                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5966691765                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4275942                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4275942                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4275942                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4275942                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4275942                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4275942                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100953                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100953                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100953                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100953                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100953                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100953                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13822.409271                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13822.409271                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4149                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              172                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.122093                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31390                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        31390                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        31390                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        31390                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        31390                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        31390                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       400278                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       400278                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       400278                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       400278                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       400278                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       400278                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4859637603                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4859637603                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4859637603                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4859637603                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4859637603                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4859637603                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9490000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9490000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9490000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      9490000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093612                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093612                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093612                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093612                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           275002                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          479.873805                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9429051                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           275514                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            34.223491                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         43985250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.873805                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937254                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.937254                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         45805638                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        45805638                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5875796                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5875796                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3229179                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3229179                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139566                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139566                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137212                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137212                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9104975                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9104975                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9104975                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9104975                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392540                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392540                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1582550                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1582550                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8878                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8878                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7747                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7747                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1975090                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1975090                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1975090                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1975090                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5503316358                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5503316358                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  80403947306                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  80403947306                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91149731                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     91149731                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     49845761                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     49845761                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  85907263664                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  85907263664                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  85907263664                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  85907263664                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6268336                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6268336                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4811729                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4811729                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148444                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       148444                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144959                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144959                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11080065                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11080065                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11080065                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11080065                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062623                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.062623                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.328894                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.328894                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059807                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059807                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053443                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053443                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178256                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.178256                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178256                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.178256                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6434.201756                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6434.201756                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9513                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         7748                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              587                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            136                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.206133                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    56.970588                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       255347                       # number of writebacks
system.cpu0.dcache.writebacks::total           255347                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203411                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       203411                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1451593                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1451593                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          468                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          468                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1655004                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1655004                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1655004                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1655004                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189129                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       189129                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130957                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130957                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8410                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8410                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7747                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7747                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       320086                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       320086                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       320086                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       320086                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2397985131                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2397985131                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5338215866                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5338215866                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69513767                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69513767                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34349239                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34349239                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7736200997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7736200997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7736200997                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7736200997                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13434640527                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13434640527                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1206086382                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1206086382                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14640726909                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14640726909                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030172                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030172                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027216                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027216                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056654                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056654                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053443                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053443                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028888                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028888                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028888                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028888                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8265.608442                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8265.608442                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4433.876210                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4433.876210                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9293378                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7631598                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           415998                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             5889507                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5046361                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            85.683929                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 797302                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             43622                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42971422                       # DTB read hits
system.cpu1.dtb.read_misses                     37905                       # DTB read misses
system.cpu1.dtb.write_hits                    6976449                       # DTB write hits
system.cpu1.dtb.write_misses                    10883                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1918                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2893                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   296                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      686                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                43009327                       # DTB read accesses
system.cpu1.dtb.write_accesses                6987332                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49947871                       # DTB hits
system.cpu1.dtb.misses                          48788                       # DTB misses
system.cpu1.dtb.accesses                     49996659                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7719787                       # ITB inst hits
system.cpu1.itb.inst_misses                      5634                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1369                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1538                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7725421                       # ITB inst accesses
system.cpu1.itb.hits                          7719787                       # DTB hits
system.cpu1.itb.misses                           5634                       # DTB misses
system.cpu1.itb.accesses                      7725421                       # DTB accesses
system.cpu1.numCycles                       413693823                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19372544                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      61318271                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9293378                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           5843663                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13362487                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3346253                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     69736                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              80999073                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5941                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42062                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1494344                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7717920                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               551887                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2996                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         117635394                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.638004                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.959630                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               104280280     88.65%     88.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  814710      0.69%     89.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  961160      0.82%     90.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1713171      1.46%     91.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1415249      1.20%     92.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  586962      0.50%     93.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1954597      1.66%     94.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  422243      0.36%     95.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5487022      4.66%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           117635394                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022464                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.148221                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                20963679                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             81759193                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 11913295                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               809519                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2189708                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1137363                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               100954                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              71089276                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               336011                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2189708                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22156707                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               33902507                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      43325786                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11473545                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4587141                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              67137864                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  137                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                682095                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3075433                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents            1010                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           70763032                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            313108743                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       286757803                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6623                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             50416422                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                20346610                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            765987                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        705836                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  8420477                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            12843204                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8115826                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1055497                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1512633                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  61850161                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1179252                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 88896986                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93979                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       13548762                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     36246660                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        279849                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    117635394                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.755699                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.498688                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           86772303     73.76%     73.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            9298113      7.90%     81.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4175598      3.55%     85.22% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3594840      3.06%     88.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10374006      8.82%     97.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1994938      1.70%     98.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1065613      0.91%     99.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             281099      0.24%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              78884      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      117635394                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  32152      0.41%      0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   986      0.01%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7573471     95.70%     96.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               306947      3.88%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            14268      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37614404     42.31%     42.33% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               61197      0.07%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 13      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1706      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43858329     49.34%     91.74% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7347048      8.26%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              88896986                       # Type of FU issued
system.cpu1.iq.rate                          0.214886                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7913556                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.089019                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         303469985                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         76586992                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     54255274                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15534                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8108                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6874                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96788024                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   8250                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          355713                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2862172                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         4122                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17485                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1111950                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31965671                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       675853                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2189708                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               26386476                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               363440                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           63133555                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           115239                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             12843204                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8115826                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            883054                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 66097                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 4286                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17485                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        204520                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       158639                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              363159                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             87164207                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43354058                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1732779                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104142                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50636612                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7376811                       # Number of branches executed
system.cpu1.iew.exec_stores                   7282554                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.210697                       # Inst execution rate
system.cpu1.iew.wb_sent                      86400335                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     54262148                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30287291                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53873069                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131165                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.562197                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       13443206                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         899403                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           316783                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    115445686                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.426296                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.378874                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     97421932     84.39%     84.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      9594899      8.31%     92.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2172227      1.88%     94.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1301741      1.13%     95.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       988993      0.86%     96.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       587152      0.51%     97.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1008803      0.87%     97.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       534624      0.46%     98.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1835315      1.59%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    115445686                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38873610                       # Number of instructions committed
system.cpu1.commit.committedOps              49214014                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16984908                       # Number of memory references committed
system.cpu1.commit.loads                      9981032                       # Number of loads committed
system.cpu1.commit.membars                     195536                       # Number of memory barriers committed
system.cpu1.commit.branches                   6424997                       # Number of branches committed
system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 43926362                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              553376                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        32169137     65.37%     65.37% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          58263      0.12%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         1706      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        9981032     20.28%     85.77% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       7003876     14.23%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         49214014                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1835315                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   175201017                       # The number of ROB reads
system.cpu1.rob.rob_writes                  127586843                       # The number of ROB writes
system.cpu1.timesIdled                        1428644                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      296058429                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4796946974                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38803971                       # Number of Instructions Simulated
system.cpu1.committedOps                     49144375                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                             10.661121                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.661121                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.093799                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.093799                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               391634066                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56368159                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5144                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2332                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              202762353                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                723009                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           614589                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.738252                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            7056364                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           615101                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            11.471879                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      74953244500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.738252                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974098                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974098                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          8332995                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         8332995                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      7056364                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7056364                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7056364                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7056364                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7056364                       # number of overall hits
system.cpu1.icache.overall_hits::total        7056364                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       661505                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       661505                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       661505                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        661505                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       661505                       # number of overall misses
system.cpu1.icache.overall_misses::total       661505                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8964922762                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8964922762                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8964922762                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8964922762                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8964922762                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8964922762                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7717869                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7717869                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7717869                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7717869                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7717869                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7717869                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085711                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.085711                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085711                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.085711                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085711                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.085711                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13552.312926                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13552.312926                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3582                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              212                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.896226                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46379                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        46379                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        46379                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        46379                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        46379                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        46379                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       615126                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       615126                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       615126                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       615126                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       615126                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       615126                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7320744820                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7320744820                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7320744820                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7320744820                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7320744820                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7320744820                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3847250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3847250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3847250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3847250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079702                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.079702                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079702                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.079702                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           363297                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          486.117445                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           13019165                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           363645                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            35.801853                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      71011321250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.117445                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949448                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.949448                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         60291027                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        60291027                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      8513196                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8513196                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4271027                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4271027                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99804                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        99804                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97081                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        97081                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12784223                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12784223                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12784223                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12784223                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       403038                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       403038                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1566274                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1566274                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14187                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14187                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10911                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10911                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1969312                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1969312                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1969312                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1969312                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6108097691                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6108097691                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  77891341203                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  77891341203                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131130743                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    131130743                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58206088                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     58206088                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  83999438894                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  83999438894                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  83999438894                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  83999438894                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8916234                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8916234                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5837301                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5837301                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       113991                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       113991                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       107992                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       107992                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14753535                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14753535                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14753535                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14753535                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045203                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045203                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.268322                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.268322                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124457                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124457                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101035                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101035                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.133481                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.133481                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.133481                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.133481                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9243.021287                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9243.021287                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5334.624507                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5334.624507                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        29593                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        18156                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3287                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            175                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.003042                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   103.748571                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       327781                       # number of writebacks
system.cpu1.dcache.writebacks::total           327781                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171674                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       171674                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1403027                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1403027                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1467                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1467                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1574701                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1574701                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1574701                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1574701                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231364                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       231364                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163247                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       163247                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12720                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12720                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10911                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10911                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       394611                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       394611                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       394611                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       394611                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2878773157                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2878773157                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   7001686259                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   7001686259                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89753005                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89753005                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36382912                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36382912                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9880459416                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   9880459416                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9880459416                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   9880459416                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25869959988                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25869959988                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025949                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025949                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027966                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027966                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.111588                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.111588                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101035                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101035                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026747                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026747                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026747                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026747                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7056.053852                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7056.053852                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3334.516726                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3334.516726                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1735350782356                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   42636                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   50408                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------