1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.625378 # Number of seconds simulated
sim_ticks 2625378187500 # Number of ticks simulated
final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94574 # Simulator instruction rate (inst/s)
host_op_rate 114754 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2065319127 # Simulator tick rate (ticks/s)
host_mem_usage 650700 # Number of bytes of host memory used
host_seconds 1271.17 # Real time elapsed on the host
sim_insts 120220550 # Number of instructions simulated
sim_ops 145872273 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 193296 # Number of read requests accepted
system.physmem.writeReqs 175528 # Number of write requests accepted
system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12287 # Per bank write bursts
system.physmem.perBankRdBursts::1 11514 # Per bank write bursts
system.physmem.perBankRdBursts::2 12472 # Per bank write bursts
system.physmem.perBankRdBursts::3 12180 # Per bank write bursts
system.physmem.perBankRdBursts::4 14590 # Per bank write bursts
system.physmem.perBankRdBursts::5 12444 # Per bank write bursts
system.physmem.perBankRdBursts::6 12518 # Per bank write bursts
system.physmem.perBankRdBursts::7 12466 # Per bank write bursts
system.physmem.perBankRdBursts::8 11679 # Per bank write bursts
system.physmem.perBankRdBursts::9 12089 # Per bank write bursts
system.physmem.perBankRdBursts::10 11915 # Per bank write bursts
system.physmem.perBankRdBursts::11 11053 # Per bank write bursts
system.physmem.perBankRdBursts::12 11299 # Per bank write bursts
system.physmem.perBankRdBursts::13 11450 # Per bank write bursts
system.physmem.perBankRdBursts::14 11880 # Per bank write bursts
system.physmem.perBankRdBursts::15 11330 # Per bank write bursts
system.physmem.perBankWrBursts::0 9713 # Per bank write bursts
system.physmem.perBankWrBursts::1 9189 # Per bank write bursts
system.physmem.perBankWrBursts::2 10054 # Per bank write bursts
system.physmem.perBankWrBursts::3 9647 # Per bank write bursts
system.physmem.perBankWrBursts::4 9435 # Per bank write bursts
system.physmem.perBankWrBursts::5 9608 # Per bank write bursts
system.physmem.perBankWrBursts::6 10036 # Per bank write bursts
system.physmem.perBankWrBursts::7 9866 # Per bank write bursts
system.physmem.perBankWrBursts::8 9192 # Per bank write bursts
system.physmem.perBankWrBursts::9 9471 # Per bank write bursts
system.physmem.perBankWrBursts::10 9539 # Per bank write bursts
system.physmem.perBankWrBursts::11 9209 # Per bank write bursts
system.physmem.perBankWrBursts::12 9294 # Per bank write bursts
system.physmem.perBankWrBursts::13 9108 # Per bank write bursts
system.physmem.perBankWrBursts::14 9699 # Per bank write bursts
system.physmem.perBankWrBursts::15 8890 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
system.physmem.totGap 2625377925000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 550 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3082 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 189636 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 171137 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads
system.physmem.totQLat 6824061250 # Total ticks spent queuing
system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers
system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing
system.physmem.readRowHits 161531 # Number of row buffer hits during reads
system.physmem.writeRowHits 96107 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes
system.physmem.avgGap 7118240.48 # Average gap between requests
system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.508799 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states
system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.445422 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states
system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 22612465 # Number of BP lookups
system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 61748 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 16748968 # DTB read hits
system.cpu0.dtb.read_misses 52995 # DTB read misses
system.cpu0.dtb.write_hits 13907664 # DTB write hits
system.cpu0.dtb.write_misses 8753 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 16801963 # DTB read accesses
system.cpu0.dtb.write_accesses 13916417 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 30656632 # DTB hits
system.cpu0.dtb.misses 61748 # DTB misses
system.cpu0.dtb.accesses 30718380 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 9874 # Table walker walks requested
system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 35678798 # ITB inst hits
system.cpu0.itb.inst_misses 9874 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses
system.cpu0.itb.hits 35678798 # DTB hits
system.cpu0.itb.misses 9874 # DTB misses
system.cpu0.itb.accesses 35688672 # DTB accesses
system.cpu0.numCycles 121733824 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued
system.cpu0.iq.rate 0.780596 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 171145 # number of nop insts executed
system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed
system.cpu0.iew.exec_branches 15805524 # Number of branches executed
system.cpu0.iew.exec_stores 14767221 # Number of stores executed
system.cpu0.iew.exec_rate 0.772250 # Inst execution rate
system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 48393961 # num instructions producing a value
system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 74499569 # Number of instructions committed
system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 30256494 # Number of memory references committed
system.cpu0.commit.loads 15822807 # Number of loads committed
system.cpu0.commit.membars 627513 # Number of memory barriers committed
system.cpu0.commit.branches 15208996 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions.
system.cpu0.commit.function_calls 1847857 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 209187674 # The number of ROB reads
system.cpu0.rob.rob_writes 196861250 # The number of ROB writes
system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 74377875 # Number of Instructions Simulated
system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads
system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads
system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes
system.cpu0.misc_regfile_reads 233358199 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 674914 # number of replacements
system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits
system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses
system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks
system.cpu0.dcache.writebacks::total 492000 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1200530 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits
system.cpu0.icache.overall_hits::total 34431245 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses
system.cpu0.icache.overall_misses::total 1244682 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 264213 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses
system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks
system.cpu0.l2cache.writebacks::total 192333 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2542000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2076482303 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2175990950 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4263319752 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15030655008 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 535907154 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 535907154 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 687931 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 35319893 # Number of BP lookups
system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 24259 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 11166498 # DTB read hits
system.cpu1.dtb.read_misses 21069 # DTB read misses
system.cpu1.dtb.write_hits 7306223 # DTB write hits
system.cpu1.dtb.write_misses 3190 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 11187567 # DTB read accesses
system.cpu1.dtb.write_accesses 7309413 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 18472721 # DTB hits
system.cpu1.dtb.misses 24259 # DTB misses
system.cpu1.dtb.accesses 18496980 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 6817 # Table walker walks requested
system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 45723303 # ITB inst hits
system.cpu1.itb.inst_misses 6817 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses
system.cpu1.itb.hits 45723303 # DTB hits
system.cpu1.itb.misses 6817 # DTB misses
system.cpu1.itb.accesses 45730120 # DTB accesses
system.cpu1.numCycles 113567718 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued
system.cpu1.iq.rate 0.525478 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 55192 # number of nop insts executed
system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed
system.cpu1.iew.exec_branches 12866831 # Number of branches executed
system.cpu1.iew.exec_stores 7487148 # Number of stores executed
system.cpu1.iew.exec_rate 0.522399 # Inst execution rate
system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 28211344 # num instructions producing a value
system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 45875888 # Number of instructions committed
system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 18225990 # Number of memory references committed
system.cpu1.commit.loads 10888694 # Number of loads committed
system.cpu1.commit.membars 231720 # Number of memory barriers committed
system.cpu1.commit.branches 12659864 # Number of branches committed
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions.
system.cpu1.commit.function_calls 3453612 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction
system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 150434096 # The number of ROB reads
system.cpu1.rob.rob_writes 123166009 # The number of ROB writes
system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 45842675 # Number of Instructions Simulated
system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads
system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads
system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads
system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes
system.cpu1.misc_regfile_reads 220514092 # number of misc regfile reads
system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 227457 # number of replacements
system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits
system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses
system.cpu1.dcache.overall_misses::total 769440 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks
system.cpu1.dcache.writebacks::total 138868 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 671809 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits
system.cpu1.icache.overall_hits::total 45027049 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses
system.cpu1.icache.overall_misses::total 695384 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 61852 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits
system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses
system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks
system.cpu1.l2cache.writebacks::total 35144 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 628857 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31011 # Transaction distribution
system.iobus.trans_dist::ReadResp 31011 # Transaction distribution
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.trans_dist::WriteResp 23197 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 130801 # number of replacements
system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use
system.l2c.tags.total_refs 351623 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5006121 # Number of tag accesses
system.l2c.tags.data_accesses 5006121 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits
system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits
system.l2c.Writeback_hits::total 227479 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits
system.l2c.demand_hits::total 161503 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits
system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits
system.l2c.overall_hits::cpu0.data 49175 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits
system.l2c.overall_hits::cpu1.data 13201 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits
system.l2c.overall_hits::total 161503 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses
system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses
system.l2c.demand_misses::total 190066 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses
system.l2c.overall_misses::cpu0.data 18842 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses
system.l2c.overall_misses::cpu1.data 10314 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses
system.l2c.overall_misses::total 190066 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 98707 # number of writebacks
system.l2c.writebacks::total 98707 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 209523 # Transaction distribution
system.membus.trans_dist::ReadResp 209522 # Transaction distribution
system.membus.trans_dist::WriteReq 31055 # Transaction distribution
system.membus.trans_dist::WriteResp 31055 # Transaction distribution
system.membus.trans_dist::Writeback 134913 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
system.membus.trans_dist::ReadExReq 38508 # Transaction distribution
system.membus.trans_dist::ReadExResp 18805 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 125464 # Total snoops (count)
system.membus.snoop_fanout::samples 569969 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 569969 # Request fanout histogram
system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 292587 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|