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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.824341 # Number of seconds simulated
sim_ticks 2824340874000 # Number of ticks simulated
final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 96866 # Simulator instruction rate (inst/s)
host_op_rate 117519 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2277239721 # Simulator tick rate (ticks/s)
host_mem_usage 609056 # Number of bytes of host memory used
host_seconds 1240.25 # Real time elapsed on the host
sim_insts 120137719 # Number of instructions simulated
sim_ops 145752951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory
system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory
system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 218132 # Number of read requests accepted
system.physmem.writeReqs 154134 # Number of write requests accepted
system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue
system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 13731 # Per bank write bursts
system.physmem.perBankRdBursts::1 13637 # Per bank write bursts
system.physmem.perBankRdBursts::2 14382 # Per bank write bursts
system.physmem.perBankRdBursts::3 14282 # Per bank write bursts
system.physmem.perBankRdBursts::4 15946 # Per bank write bursts
system.physmem.perBankRdBursts::5 13017 # Per bank write bursts
system.physmem.perBankRdBursts::6 13909 # Per bank write bursts
system.physmem.perBankRdBursts::7 13917 # Per bank write bursts
system.physmem.perBankRdBursts::8 13612 # Per bank write bursts
system.physmem.perBankRdBursts::9 13371 # Per bank write bursts
system.physmem.perBankRdBursts::10 12787 # Per bank write bursts
system.physmem.perBankRdBursts::11 11726 # Per bank write bursts
system.physmem.perBankRdBursts::12 13349 # Per bank write bursts
system.physmem.perBankRdBursts::13 14174 # Per bank write bursts
system.physmem.perBankRdBursts::14 13344 # Per bank write bursts
system.physmem.perBankRdBursts::15 12704 # Per bank write bursts
system.physmem.perBankWrBursts::0 9692 # Per bank write bursts
system.physmem.perBankWrBursts::1 9790 # Per bank write bursts
system.physmem.perBankWrBursts::2 10299 # Per bank write bursts
system.physmem.perBankWrBursts::3 9942 # Per bank write bursts
system.physmem.perBankWrBursts::4 9060 # Per bank write bursts
system.physmem.perBankWrBursts::5 9040 # Per bank write bursts
system.physmem.perBankWrBursts::6 9465 # Per bank write bursts
system.physmem.perBankWrBursts::7 9428 # Per bank write bursts
system.physmem.perBankWrBursts::8 9418 # Per bank write bursts
system.physmem.perBankWrBursts::9 9301 # Per bank write bursts
system.physmem.perBankWrBursts::10 9150 # Per bank write bursts
system.physmem.perBankWrBursts::11 8663 # Per bank write bursts
system.physmem.perBankWrBursts::12 9463 # Per bank write bursts
system.physmem.perBankWrBursts::13 9594 # Per bank write bursts
system.physmem.perBankWrBursts::14 9165 # Per bank write bursts
system.physmem.perBankWrBursts::15 8718 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 2824339295000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 559 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3083 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 214462 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 149698 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads
system.physmem.totQLat 8907181250 # Total ticks spent queuing
system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers
system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing
system.physmem.readRowHits 185267 # Number of row buffer hits during reads
system.physmem.writeRowHits 90008 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes
system.physmem.avgGap 7586884.90 # Average gap between requests
system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states
system.physmem.memoryStateTime::REF 94310840000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ)
system.physmem.averagePower::0 669.432189 # Core power per rank (mW)
system.physmem.averagePower::1 669.368701 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 237823 # Transaction distribution
system.membus.trans_dist::ReadResp 237823 # Transaction distribution
system.membus.trans_dist::WriteReq 30977 # Transaction distribution
system.membus.trans_dist::WriteResp 30977 # Transaction distribution
system.membus.trans_dist::Writeback 113474 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution
system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution
system.membus.trans_dist::ReadExReq 31194 # Transaction distribution
system.membus.trans_dist::ReadExResp 14874 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 122973 # Total snoops (count)
system.membus.snoop_fanout::samples 500866 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 500866 # Request fanout histogram
system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 153419 # number of replacements
system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use
system.l2c.tags.total_refs 521049 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6602520 # Number of tag accesses
system.l2c.tags.data_accesses 6602520 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits
system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits
system.l2c.Writeback_hits::total 252802 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits
system.l2c.demand_hits::total 299572 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits
system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits
system.l2c.overall_hits::cpu0.data 42648 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits
system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits
system.l2c.overall_hits::cpu1.data 12782 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits
system.l2c.overall_hits::total 299572 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses
system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses
system.l2c.demand_misses::total 214569 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses
system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses
system.l2c.overall_misses::cpu0.data 16404 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu1.inst 479 # number of overall misses
system.l2c.overall_misses::cpu1.data 8598 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses
system.l2c.overall_misses::total 214569 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 47537750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 122331750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 22797831231 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 6376742 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2877882 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 9254624 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147452 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1135953 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2283405 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 711214419 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 562948982 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1274163401 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2727250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 613750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 350075996 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1472784163 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 768250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 150000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 47537750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 685280732 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 24071994632 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2727250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 613750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 350075996 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1472784163 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 768250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 150000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 47537750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 685280732 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of overall miss cycles
system.l2c.overall_miss_latency::total 24071994632 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 316 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 130 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 16292 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 47653 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346869 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 252802 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 252802 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 20556 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3555 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 24111 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 933 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1376 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 11399 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 8444 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 19843 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 316 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 130 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 16292 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 59052 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346869 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 57 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 4588 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65350 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 514141 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 316 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 130 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 16292 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 59052 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346869 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 57 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 4588 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65350 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 514141 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.061538 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.229131 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.181458 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035088 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.104403 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.106911 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.403799 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430580 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795499 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.484385 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.802787 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.874273 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.845388 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.680498 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.854453 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.754523 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.061538 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.229131 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.277789 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.035088 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.104403 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.402152 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.417335 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.061538 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.229131 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.277789 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.035088 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.104403 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.402152 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.417335 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 76718.750000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93778.729172 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88073.290621 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76825 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99243.736952 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88453.904555 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 114219.308061 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 720.454412 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1017.638614 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 792.415789 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1531.978638 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 944.266833 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1169.777152 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91686.788578 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78024.806930 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85103.085827 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 112187.662859 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 112187.662859 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 168 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 15.272727 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 113474 # number of writebacks
system.l2c.writebacks::total 113474 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 8 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 3733 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 8646 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 477 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1383 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 199573 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 8851 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 2828 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 11679 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 749 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1203 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1952 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 7757 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 7215 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 14972 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 8 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 3733 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 16403 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 477 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 8598 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 214545 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 8 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 3733 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 16403 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 477 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 8598 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 214545 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 513750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 303960496 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 654157744 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 643750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 125000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41455250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105134250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 20343291231 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89616766 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28576308 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 118193074 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7674203 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 303960496 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 643750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 291335 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31016 # Transaction distribution
system.iobus.trans_dist::ReadResp 31016 # Transaction distribution
system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.branchPred.lookups 24028098 # Number of BP lookups
system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17721911 # DTB read hits
system.cpu0.dtb.read_misses 56434 # DTB read misses
system.cpu0.dtb.write_hits 14647364 # DTB write hits
system.cpu0.dtb.write_misses 8710 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17778345 # DTB read accesses
system.cpu0.dtb.write_accesses 14656074 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 32369275 # DTB hits
system.cpu0.dtb.misses 65144 # DTB misses
system.cpu0.dtb.accesses 32434419 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 37749203 # ITB inst hits
system.cpu0.itb.inst_misses 10291 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses
system.cpu0.itb.hits 37749203 # DTB hits
system.cpu0.itb.misses 10291 # DTB misses
system.cpu0.itb.accesses 37759494 # DTB accesses
system.cpu0.numCycles 126930318 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued
system.cpu0.iq.rate 0.793096 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 174730 # number of nop insts executed
system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed
system.cpu0.iew.exec_branches 16843179 # Number of branches executed
system.cpu0.iew.exec_stores 15534759 # Number of stores executed
system.cpu0.iew.exec_rate 0.784450 # Inst execution rate
system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 51320532 # num instructions producing a value
system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 78899754 # Number of instructions committed
system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 31908645 # Number of memory references committed
system.cpu0.commit.loads 16728770 # Number of loads committed
system.cpu0.commit.membars 647107 # Number of memory barriers committed
system.cpu0.commit.branches 16205360 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions.
system.cpu0.commit.function_calls 1929507 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 221323955 # The number of ROB reads
system.cpu0.rob.rob_writes 208662740 # The number of ROB writes
system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 78777703 # Number of Instructions Simulated
system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads
system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads
system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes
system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes
system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 1263367 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits
system.cpu0.icache.overall_hits::total 36446077 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses
system.cpu0.icache.overall_misses::total 1300540 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements 397205 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses
system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2596231534 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14566249 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5056249 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 811526688 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5290786896 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 6121936082 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14566249 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5056249 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 811526688 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5290786896 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 6121936082 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54857 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12582 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1263889 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498142 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1829470 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 512971 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 512971 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43264 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 43264 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20607 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20607 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269455 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269455 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54857 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12582 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1263889 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 767597 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2098925 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54857 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12582 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1263889 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 767597 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2098925 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016214 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017268 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182295 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.061982 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645826 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645826 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896734 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896734 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195621 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195621 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016214 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017268 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186973 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.079138 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016214 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017268 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186973 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.079138 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24785.534314 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.353402 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29672.778711 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31092.514137 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17943.682724 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17943.682724 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19594.311813 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19594.311813 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49254.074747 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49254.074747 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 36855.820607 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36855.820607 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 65022 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 1467 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.323108 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 212015 # number of writebacks
system.cpu0.l2cache.writebacks::total 212015 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5576 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3180 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 8757 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8826 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 8826 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5576 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12006 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5576 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12006 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 17583 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 556 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 203 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16249 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87629 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 104637 # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 482567 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27941 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43885 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 43885 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 556 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 203 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16249 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131514 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 148522 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 556 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16249 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131514 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 631089 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3620751 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587001511 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2007365947 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2608656960 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21948496416 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481784375 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481784375 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249254743 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249254743 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 284000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 284000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315803854 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315803854 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3620751 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587001511 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3323169801 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 3924460814 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3620751 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587001511 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3323169801 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 25872957230 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053946738 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272660488 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040262957 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040262957 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094209695 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312923445 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175912 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057195 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645826 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645826 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896734 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896734 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162866 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162866 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070761 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300672 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22907.552831 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24930.540440 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45482.795997 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17242.918113 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17242.918113 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13488.540668 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13488.540668 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29982.997699 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29982.997699 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26423.430966 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40997.319285 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 712829 # number of replacements
system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits
system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses
system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks
system.cpu0.dcache.writebacks::total 512971 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 33910931 # Number of BP lookups
system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 10163466 # DTB read hits
system.cpu1.dtb.read_misses 18799 # DTB read misses
system.cpu1.dtb.write_hits 6542146 # DTB write hits
system.cpu1.dtb.write_misses 2834 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 10182265 # DTB read accesses
system.cpu1.dtb.write_accesses 6544980 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 16705612 # DTB hits
system.cpu1.dtb.misses 21633 # DTB misses
system.cpu1.dtb.accesses 16727245 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 43642051 # ITB inst hits
system.cpu1.itb.inst_misses 6989 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses
system.cpu1.itb.hits 43642051 # DTB hits
system.cpu1.itb.misses 6989 # DTB misses
system.cpu1.itb.accesses 43649040 # DTB accesses
system.cpu1.numCycles 104614253 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued
system.cpu1.iq.rate 0.515306 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 52155 # number of nop insts executed
system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed
system.cpu1.iew.exec_branches 11807834 # Number of branches executed
system.cpu1.iew.exec_stores 6687115 # Number of stores executed
system.cpu1.iew.exec_rate 0.512725 # Inst execution rate
system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 25229731 # num instructions producing a value
system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 41392870 # Number of instructions committed
system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 16524628 # Number of memory references committed
system.cpu1.commit.loads 9966511 # Number of loads committed
system.cpu1.commit.membars 209715 # Number of memory barriers committed
system.cpu1.commit.branches 11639820 # Number of branches committed
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions.
system.cpu1.commit.function_calls 3366594 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction
system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 136550879 # The number of ROB reads
system.cpu1.rob.rob_writes 111203214 # The number of ROB writes
system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 41360016 # Number of Instructions Simulated
system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads
system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads
system.cpu1.fp_regfile_writes 520 # number of floating regfile writes
system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads
system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes
system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads
system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes
system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 835314 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.icache.tags.replacements 607233 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524677 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 87890334 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 87890334 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 43016935 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 43016935 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 43016935 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 43016935 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 43016935 # number of overall hits
system.cpu1.icache.overall_hits::total 43016935 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 624358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 624358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 624358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 624358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 624358 # number of overall misses
system.cpu1.icache.overall_misses::total 624358 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5094140300 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5094140300 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5094140300 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5094140300 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5094140300 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5094140300 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641293 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 43641293 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 43641293 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 43641293 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 43641293 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 43641293 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014307 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014307 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014307 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014307 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014307 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014307 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8159.005410 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8159.005410 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8159.005410 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8159.005410 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 274240 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 36121 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.592259 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16610 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 16610 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 16610 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 16610 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 16610 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 16610 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607748 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 607748 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 607748 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 607748 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 607748 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 607748 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4102836710 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4102836710 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4102836710 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4102836710 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4102836710 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4102836710 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements 85866 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.044342 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.120039 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420191 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.952187 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9526 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits
system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 104991 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 111682 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 5943 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 104991 # number of overall misses
system.cpu1.l2cache.overall_misses::total 111682 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10433249 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5666498 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 181785702 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611031625 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1808917074 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536972883 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 536972883 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442531028 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442531028 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 437999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 437999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278690285 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1278690285 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10433249 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5666498 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 181785702 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2889721910 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3087607359 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10433249 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5666498 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 181785702 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2889721910 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3087607359 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16807 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7685 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607745 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173383 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 805620 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 117435 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 117435 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30640 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 30640 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23395 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23395 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61823 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 61823 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16807 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7685 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 607745 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 235206 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 867443 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16807 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7685 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 607745 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 235206 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 867443 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035914 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009779 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415715 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926501 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926501 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964223 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964223 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532375 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532375 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035914 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009779 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446379 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.128749 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035914 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009779 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446379 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.128749 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20530.789855 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30588.204947 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22351.225409 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22964.834821 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18915.488340 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18915.488340 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19617.476195 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.476195 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 218999.500000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218999.500000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38850.614803 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38850.614803 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27646.418931 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27646.418931 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 22060 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 480 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.958333 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 40786 # number of writebacks
system.cpu1.l2cache.writebacks::total 40786 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1367 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 1465 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1237 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 1237 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1367 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1321 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1367 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1321 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 2702 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4576 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71994 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 77304 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 109552 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28388 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28388 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22558 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22558 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31676 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 31676 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4576 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103670 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 108980 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4576 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103670 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 218532 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3660000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 123437534 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105460943 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1239685228 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3461172800 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 416881074 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 416881074 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308366284 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308366284 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 367999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 367999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944446910 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944446910 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3660000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 123437534 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2049907853 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2184132138 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3660000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 123437534 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2049907853 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 5645304938 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 191071 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits
system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses
system.cpu1.dcache.overall_misses::total 647985 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks
system.cpu1.dcache.writebacks::total 117436 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 36453 # number of replacements
system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328359 # Number of tag accesses
system.iocache.tags.data_accesses 328359 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses
system.iocache.ReadReq_misses::total 247 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses
system.iocache.demand_misses::total 247 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 247 # number of overall misses
system.iocache.overall_misses::total 247 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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