path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.621647                       # Number of seconds simulated
sim_ticks                                2621647051000                       # Number of ticks simulated
final_tick                               2621647051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  56801                       # Simulator instruction rate (inst/s)
host_op_rate                                    68443                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2377539464                       # Simulator tick rate (ticks/s)
host_mem_usage                                 411700                       # Number of bytes of host memory used
host_seconds                                  1102.67                       # Real time elapsed on the host
sim_insts                                    62632896                       # Number of instructions simulated
sim_ops                                      75470296                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           516048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          6568572                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           301968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2981560                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131479316                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       516048                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       301968                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          818016                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4189696                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       3029096                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7218832                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10590                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            102693                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4761                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             46605                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15303475                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           65464                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           757274                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               822748                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46196351                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           171                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              196841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2505513                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              115183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1137285                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50151418                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         196841                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         115183                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             312024                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1598116                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data            1155417                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2753548                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1598116                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46196351                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          171                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             196841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3660931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             115183                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1137300                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               52904966                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15303475                       # Number of read requests accepted
system.physmem.writeReqs                       822748                       # Number of write requests accepted
system.physmem.readBursts                    15303475                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     822748                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                977402304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2020096                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7239040                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131479316                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7218832                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    31564                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709609                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12033                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              956536                       # Per bank write bursts
system.physmem.perBankRdBursts::1              956505                       # Per bank write bursts
system.physmem.perBankRdBursts::2              953083                       # Per bank write bursts
system.physmem.perBankRdBursts::3              951219                       # Per bank write bursts
system.physmem.perBankRdBursts::4              959451                       # Per bank write bursts
system.physmem.perBankRdBursts::5              955886                       # Per bank write bursts
system.physmem.perBankRdBursts::6              953593                       # Per bank write bursts
system.physmem.perBankRdBursts::7              950807                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956024                       # Per bank write bursts
system.physmem.perBankRdBursts::9              956507                       # Per bank write bursts
system.physmem.perBankRdBursts::10             953309                       # Per bank write bursts
system.physmem.perBankRdBursts::11             950948                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956403                       # Per bank write bursts
system.physmem.perBankRdBursts::13             956390                       # Per bank write bursts
system.physmem.perBankRdBursts::14             954120                       # Per bank write bursts
system.physmem.perBankRdBursts::15             951130                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7301                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7301                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6635                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6826                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7245                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6961                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7187                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6869                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6823                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7301                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6956                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6738                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7232                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7102                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7378                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7255                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2621645657000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      59                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138841                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3426                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  161149                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  65464                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1118217                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    965108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    965171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1074431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    973448                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1034951                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2682221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2590422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3372339                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    127125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   110466                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   101918                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    97549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20170                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    19294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    19015                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1014826                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      970.256324                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     901.955292                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     206.811149                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24748      2.44%      2.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        20792      2.05%      4.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         9109      0.90%      5.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2441      0.24%      5.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2631      0.26%      5.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1759      0.17%      6.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9074      0.89%      6.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1088      0.11%      7.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       943184     92.94%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1014826                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6619                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2307.281009                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    96810.313262                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143         6612     99.89%     99.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::262144-524287            1      0.02%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6619                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6619                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.088684                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.037372                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.359683                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3686     55.69%     55.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 52      0.79%     56.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1827     27.60%     84.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                927     14.01%     98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 37      0.56%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 27      0.41%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 28      0.42%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 21      0.32%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 11      0.17%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6619                       # Writes before turning the bus around for reads
system.physmem.totQLat                   395207982750                       # Total ticks spent queuing
system.physmem.totMemAccLat              681556314000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76359555000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25878.10                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44628.10                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         372.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.76                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.15                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.75                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.93                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.91                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         5.85                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        27.60                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14274861                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95334                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.26                       # Row buffer hit rate for writes
system.physmem.avgGap                       162570.35                       # Average gap between requests
system.physmem.pageHitRate                      93.40                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2271344460000                       # Time in different power states
system.physmem.memoryStateTime::REF       87542520000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      262759227500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           192                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          192                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            3                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           18                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           55                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               73                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           55                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           73                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           18                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           55                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              73                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     53827614                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16353736                       # Transaction distribution
system.membus.trans_dist::ReadResp           16353736                       # Transaction distribution
system.membus.trans_dist::WriteReq             768463                       # Transaction distribution
system.membus.trans_dist::WriteResp            768463                       # Transaction distribution
system.membus.trans_dist::Writeback             65464                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            28363                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          16887                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12033                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137713                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137251                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384346                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10950                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2058                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1967095                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4364477                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34642109                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392641                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        21900                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4116                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17587620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20006477                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141117005                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141117005                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1559281500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               14500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             9763000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy             1786500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17605374000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4830238688                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37428300697                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    71035                       # number of replacements
system.l2c.tags.tagsinuse                52844.560777                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1830685                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   136207                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.440462                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37821.803984                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.739512                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000522                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5415.027395                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6377.582658                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.953654                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2390.174334                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      833.278718                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.577115                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000088                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.082627                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.097314                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.036471                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.012715                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.806344                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3098                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8323                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53527                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18484845                       # Number of tag accesses
system.l2c.tags.data_accesses                18484845                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        20873                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         5362                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             546777                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             243323                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        15709                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4324                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             434561                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             119239                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1390168                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          583269                       # number of Writeback hits
system.l2c.Writeback_hits::total               583269                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1334                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             378                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1712                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           271                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           117                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               388                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            65538                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            44550                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               110088                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         20873                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5362                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              546777                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              308861                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         15709                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4324                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              434561                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              163789                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1500256                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        20873                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5362                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             546777                       # number of overall hits
system.l2c.overall_hits::cpu0.data             308861                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        15709                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4324                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             434561                       # number of overall hits
system.l2c.overall_hits::cpu1.data             163789                       # number of overall hits
system.l2c.overall_hits::total                1500256                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7230                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             9897                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4714                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             2106                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23958                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4509                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3863                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8372                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          516                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          628                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1144                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          94130                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          45638                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139768                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7230                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            104027                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4714                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             47744                       # number of demand (read+write) misses
system.l2c.demand_misses::total                163726                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            8                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7230                       # number of overall misses
system.l2c.overall_misses::cpu0.data           104027                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4714                       # number of overall misses
system.l2c.overall_misses::cpu1.data            47744                       # number of overall misses
system.l2c.overall_misses::total               163726                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       551500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       150000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    522312750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    733828247                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    334292999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    165107999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1756326995                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     11295015                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12799954                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     24094969                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1793923                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1118952                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2912875                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6378706625                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3294603599                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9673310224                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       551500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       150000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    522312750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   7112534872                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    334292999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3459711598                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11429637219                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       551500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       150000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    522312750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   7112534872                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    334292999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3459711598                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11429637219                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        20881                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5364                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         554007                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         253220                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        15710                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         4324                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         439275                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         121345                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1414126                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       583269                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           583269                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         5843                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4241                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10084                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          787                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          745                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1532                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       159668                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        90188                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249856                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        20881                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5364                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          554007                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          412888                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        15710                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         4324                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          439275                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          211533                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1663982                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        20881                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5364                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         554007                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         412888                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        15710                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         4324                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         439275                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         211533                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1663982                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000383                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000373                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013050                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.039085                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000064                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010731                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.017355                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016942                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.771693                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.910870                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.830226                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.655654                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.842953                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.746736                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.589536                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.506032                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.559394                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000383                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000373                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013050                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.251950                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000064                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010731                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.225705                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098394                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000383                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000373                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013050                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.251950                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000064                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010731                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.225705                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098394                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68937.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72242.427386                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74146.534000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70914.934026                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78398.859924                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73308.581476                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2504.993347                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3313.475019                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2878.042164                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3476.594961                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1781.770701                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2546.219406                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67764.863752                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72189.920658                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69209.763494                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68937.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72242.427386                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 68372.007959                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 70914.934026                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72463.798551                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69809.542889                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68937.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72242.427386                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 68372.007959                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 70914.934026                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72463.798551                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69809.542889                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               65464                       # number of writebacks
system.l2c.writebacks::total                    65464                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            28                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                60                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             28                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 60                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            28                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                60                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7221                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         9869                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4704                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         2094                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23898                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4509                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3863                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8372                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          516                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          628                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1144                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        94130                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        45638                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139768                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7221                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       103999                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4704                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        47732                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           163666                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7221                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       103999                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4704                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        47732                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          163666                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       395000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    431252250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    608078747                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        71000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    274798249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    138281999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1453002245                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     45149974                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     38756824                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     83906798                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5160516                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      6295125                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     11455641                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5201483861                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2728717885                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7930201746                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       395000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    431252250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5809562608                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        71000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    274798249                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2866999884                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9383203991                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       395000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    431252250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5809562608                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        71000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    274798249                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2866999884                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9383203991                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    176335500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12626197496                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3342000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154644756250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167450631246                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  16805961075                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    475202500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17281163575                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    176335500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  29432158571                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3342000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155119958750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184731794821                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000335                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.038974                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017257                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016899                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.771693                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.910870                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.830226                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.655654                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.842953                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.746736                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.589536                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.506032                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.559394                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000335                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.251882                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.225648                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098358                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000335                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.251882                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.225648                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098358                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57331.418810                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57331.418810                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    57560286                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2682607                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2682607                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            768463                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           768463                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           583269                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           27558                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         17275                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          44833                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp            1                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           261997                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          261997                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1115277                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2956767                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        14518                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50368                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       879187                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2909426                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        12099                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        38611                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7976253                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     35510400                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     53724619                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21456                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83524                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     28114656                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     29015778                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        17296                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        62840                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          146550569                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             146550569                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4352184                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4888594820                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2503079453                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2482730980                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9171959                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          29595779                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        1980581418                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        2244583247                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           7797450                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy          22968355                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      47108999                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322906                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322906                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8814                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1034                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          736                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2384346                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32661978                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17628                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2392641                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123503169                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123503169                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4413000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               523000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               440000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2376263000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         38168032303                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                8682194                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          6490987                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           415813                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             5217710                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4131218                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            79.176842                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 908190                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             19748                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    10917771                       # DTB read hits
system.cpu0.dtb.read_misses                     23643                       # DTB read misses
system.cpu0.dtb.write_hits                    7767808                       # DTB write hits
system.cpu0.dtb.write_misses                     8146                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1721                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      163                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   270                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      598                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                10941414                       # DTB read accesses
system.cpu0.dtb.write_accesses                7775954                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         18685579                       # DTB hits
system.cpu0.dtb.misses                          31789                       # DTB misses
system.cpu0.dtb.accesses                     18717368                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    16449037                       # ITB inst hits
system.cpu0.itb.inst_misses                      5743                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1206                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     2114                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                16454780                       # ITB inst accesses
system.cpu0.itb.hits                         16449037                       # DTB hits
system.cpu0.itb.misses                           5743                       # DTB misses
system.cpu0.itb.accesses                     16454780                       # DTB accesses
system.cpu0.numCycles                       110984158                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          29010417                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      51007104                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    8682194                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5039408                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     76702951                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1090474                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     80643                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               23949                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        71996                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1961272                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 16450117                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               242573                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2510                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         108396478                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.561251                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.057421                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                80471532     74.24%     74.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 9354408      8.63%     82.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 4228353      3.90%     86.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                14342185     13.23%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           108396478                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.078229                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.459589                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                24273364                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             59696324                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 21865637                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              2148424                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                412729                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1100967                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               134603                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56048449                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              1161275                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                412729                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                26181144                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               23163659                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      11818847                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 22001270                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             24818829                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              54863842                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts               371818                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              4330145                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2622839                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               9842391                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              13156385                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           58083982                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            254404471                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        69151408                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             3820                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             54276662                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 3807314                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            540800                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        442723                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  4591136                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9492850                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            8297955                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads           506397                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          589876                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  53569882                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             859573                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 55433156                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           105167                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        2762956                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      5503873                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved         84823                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    108396478                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.511393                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       0.864824                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           74367725     68.61%     68.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           17769290     16.39%     85.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           11558620     10.66%     95.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            4256755      3.93%     99.59% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4             444079      0.41%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      108396478                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                3788078     33.87%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   172      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     33.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               3595287     32.14%     66.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3801407     33.99%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            14948      0.03%      0.03% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             35826739     64.63%     64.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               64782      0.12%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     64.77% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           722      0.00%     64.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     64.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     64.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     64.78% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            11302035     20.39%     85.16% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            8223930     14.84%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              55433156                       # Type of FU issued
system.cpu0.iq.rate                          0.499469                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11184944                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.201774                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         230540772                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         57191232                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     52885161                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12129                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4604                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3838                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              66595213                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7939                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          146965                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads       634189                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses          503                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation         3442                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       242149                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      1082260                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      1003693                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                412729                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                7302695                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              6441595                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           54523303                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9492850                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             8297955                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            524870                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 12318                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              6420937                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents          3442                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        134210                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       165432                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              299642                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             55026621                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             11133456                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           374843                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        93848                       # number of nop insts executed
system.cpu0.iew.exec_refs                    19301977                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7332190                       # Number of branches executed
system.cpu0.iew.exec_stores                   8168521                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.495806                       # Inst execution rate
system.cpu0.iew.wb_sent                      54039254                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     52888999                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 25110485                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 37735585                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.476545                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.665433                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        2480238                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         774750                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           283305                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    107840192                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.477624                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.224539                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     82912194     76.88%     76.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     14339479     13.30%     90.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      5152045      4.78%     94.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1572745      1.46%     96.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1370622      1.27%     97.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       690625      0.64%     98.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       401555      0.37%     98.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       407085      0.38%     99.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8       993842      0.92%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    107840192                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            43173906                       # Number of instructions committed
system.cpu0.commit.committedOps              51507078                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      16914467                       # Number of memory references committed
system.cpu0.commit.loads                      8858661                       # Number of loads committed
system.cpu0.commit.membars                     263890                       # Number of memory barriers committed
system.cpu0.commit.branches                   7043091                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 45505753                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              666034                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        34530023     67.04%     67.04% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          61866      0.12%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc          722      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.16% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        8858661     17.20%     84.36% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       8055806     15.64%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         51507078                       # Class of committed instruction
system.cpu0.commit.bw_lim_events               993842                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   159811836                       # The number of ROB reads
system.cpu0.rob.rob_writes                  108530018                       # The number of ROB writes
system.cpu0.timesIdled                         338876                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2587680                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5132257518                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   43093164                       # Number of Instructions Simulated
system.cpu0.committedOps                     51426336                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.575447                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.575447                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.388282                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.388282                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                67127966                       # number of integer regfile reads
system.cpu0.int_regfile_writes               33211893                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3352                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     840                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                191848471                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                22040987                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              169210728                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                593502                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           554010                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.387606                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           15866984                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           554522                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            28.613804                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      18806389250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.387606                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998804                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998804                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         17001271                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        17001271                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     15866984                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       15866984                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     15866984                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        15866984                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     15866984                       # number of overall hits
system.cpu0.icache.overall_hits::total       15866984                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       579761                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       579761                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       579761                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        579761                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       579761                       # number of overall misses
system.cpu0.icache.overall_misses::total       579761                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   8029558142                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8029558142                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   8029558142                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8029558142                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   8029558142                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8029558142                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     16446745                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     16446745                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     16446745                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     16446745                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     16446745                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     16446745                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.035251                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.035251                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.035251                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.035251                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.035251                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.035251                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13849.772824                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13849.772824                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          739                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.436364                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        25235                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        25235                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        25235                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        25235                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        25235                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        25235                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       554526                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       554526                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       554526                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       554526                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       554526                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       554526                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6629844046                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6629844046                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6629844046                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6629844046                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6629844046                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6629844046                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    226658500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    226658500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    226658500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    226658500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033716                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.033716                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.033716                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           409126                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          483.194796                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           12942599                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           409638                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            31.595211                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        271704250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.194796                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.943740                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.943740                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63030887                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63030887                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      8037454                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        8037454                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4509267                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4509267                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        46089                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        46089                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156971                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       156971                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       159079                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       159079                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12546721                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12546721                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12592810                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12592810                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       406720                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       406720                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2221250                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2221250                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        92142                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total        92142                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10979                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        10979                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7659                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7659                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2627970                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2627970                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2720112                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2720112                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5668958645                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5668958645                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 107130503686                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    114563996                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    114563996                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44413016                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     44413016                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 112799462331                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 112799462331                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8444174                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8444174                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      6730517                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6730517                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       138231                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       138231                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       167950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       167950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       166738                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       166738                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     15174691                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15174691                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     15312922                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15312922                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048166                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.048166                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330027                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.330027                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.666580                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.666580                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065371                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065371                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.045934                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.045934                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.173181                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.173181                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.177635                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.177635                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5798.800888                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5798.800888                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        14275                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             1041                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.712776                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       375988                       # number of writebacks
system.cpu0.dcache.writebacks::total           375988                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       193747                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       193747                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      2045363                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2045363                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         1054                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1054                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2239110                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2239110                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2239110                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2239110                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       212973                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       212973                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       175887                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       175887                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        54623                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        54623                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9925                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9925                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7659                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7659                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       388860                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       388860                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       443483                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       443483                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2487825853                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2487825853                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7369362883                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7369362883                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1035896777                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1035896777                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     82981003                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     82981003                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29093984                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29093984                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9857188736                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9857188736                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10893085513                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10893085513                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13737621002                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13737621002                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  26275689041                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26275689041                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  40013310043                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  40013310043                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025221                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.025221                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026133                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026133                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.395157                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.395157                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059095                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059095                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.045934                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.045934                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025626                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025626                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028961                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028961                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8360.806348                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8360.806348                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3798.666144                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3798.666144                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                5001209                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3530067                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           291977                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             3184313                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                2141032                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            67.236858                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 582225                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             13211                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    21293354                       # DTB read hits
system.cpu1.dtb.read_misses                     17527                       # DTB read misses
system.cpu1.dtb.write_hits                    4063342                       # DTB write hits
system.cpu1.dtb.write_misses                     3266                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1908                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      789                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   274                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      694                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                21310881                       # DTB read accesses
system.cpu1.dtb.write_accesses                4066608                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25356696                       # DTB hits
system.cpu1.dtb.misses                          20793                       # DTB misses
system.cpu1.dtb.accesses                     25377489                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     8626509                       # ITB inst hits
system.cpu1.itb.inst_misses                      4363                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1319                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     2055                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8630872                       # ITB inst accesses
system.cpu1.itb.hits                          8626509                       # DTB hits
system.cpu1.itb.misses                           4363                       # DTB misses
system.cpu1.itb.accesses                      8630872                       # DTB accesses
system.cpu1.numCycles                       396849081                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          18444788                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      25760845                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    5001209                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           2723257                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    375027882                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 802688                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     60706                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               28139                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        75697                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1303305                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.CacheLines                  8624270                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               181619                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   1774                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         395341861                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.079415                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            0.442124                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               380851246     96.33%     96.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 4867429      1.23%     97.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2340779      0.59%     98.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 7282407      1.84%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           395341861                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.012602                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.064913                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                15111141                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            368322319                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  9619404                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1988623                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                300374                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              680085                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               102949                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              27336312                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               828595                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                300374                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                16508550                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles              196017158                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      17889321                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  9851688                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles            154774770                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              26427025                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               243114                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents             56891125                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents              39780893                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents             150628157                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               2138867                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           27113530                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            124075273                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        31437770                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6241                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             24483458                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2630072                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            642693                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        559165                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  4862604                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             5657845                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            4330093                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           343073                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          498131                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  25260320                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             861912                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 41442639                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            78274                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1902061                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      3789747                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         92749                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    395341861                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.104827                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.383209                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          362283147     91.64%     91.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           26570133      6.72%     98.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4792582      1.21%     99.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            1496663      0.38%     99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             199327      0.05%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      395341861                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                1195141      5.96%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   685      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              16909984     84.32%     90.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1947822      9.71%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            13868      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             15563362     37.55%     37.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               33954      0.08%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1648      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     37.67% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            21553207     52.01%     89.68% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            4276600     10.32%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              41442639                       # Type of FU issued
system.cpu1.iq.rate                          0.104429                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   20053632                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.483889                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         498337881                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         28019357                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     25018416                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              21164                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7936                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6759                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              61468547                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  13856                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           72058                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       455146                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          306                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         3014                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       163146                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     15996057                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked         1487                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                300374                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               87167513                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             92299631                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           26204459                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              5657845                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             4330093                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            630570                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  9334                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents             92232105                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          3014                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         83298                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       118271                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              201569                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             41178523                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             21441390                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           243431                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        82227                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25682989                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 3899404                       # Number of branches executed
system.cpu1.iew.exec_stores                   4241599                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.103764                       # Inst execution rate
system.cpu1.iew.wb_sent                      41086324                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     25025175                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 11348419                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 16538487                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.063060                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.686182                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1702265                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         769163                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           191007                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    394940200                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.061056                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     0.422241                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    381244473     96.53%     96.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      9114140      2.31%     98.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2236589      0.57%     99.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       955406      0.24%     99.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       446570      0.11%     99.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       403381      0.10%     99.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       181575      0.05%     99.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        97100      0.02%     99.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       260966      0.07%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    394940200                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            19609371                       # Number of instructions committed
system.cpu1.commit.committedOps              24113599                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       9369646                       # Number of memory references committed
system.cpu1.commit.loads                      5202699                       # Number of loads committed
system.cpu1.commit.membars                     162322                       # Number of memory barriers committed
system.cpu1.commit.branches                   3698878                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 21204966                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              385194                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        14709151     61.00%     61.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          33154      0.14%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         1648      0.01%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.14% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        5202699     21.58%     82.72% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       4166947     17.28%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         24113599                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               260966                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   419589246                       # The number of ROB reads
system.cpu1.rob.rob_writes                   52032512                       # The number of ROB writes
system.cpu1.timesIdled                         248745                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1507220                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4845699469                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   19539732                       # Number of Instructions Simulated
system.cpu1.committedOps                     24043960                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                             20.309853                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       20.309853                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.049237                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.049237                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                45343306                       # number of integer regfile reads
system.cpu1.int_regfile_writes               15599183                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5046                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2260                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                139131439                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                 9348976                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              454367618                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                623445                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           439266                       # number of replacements
system.cpu1.icache.tags.tagsinuse          497.815366                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            8166304                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           439778                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            18.569151                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     119618152250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   497.815366                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.972296                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.972296                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          9063984                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         9063984                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      8166304                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        8166304                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      8166304                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         8166304                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      8166304                       # number of overall hits
system.cpu1.icache.overall_hits::total        8166304                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       457900                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       457900                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       457900                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        457900                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       457900                       # number of overall misses
system.cpu1.icache.overall_misses::total       457900                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6264180115                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6264180115                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6264180115                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6264180115                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6264180115                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6264180115                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8624204                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8624204                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8624204                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8624204                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8624204                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8624204                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.053095                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.053095                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.053095                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.053095                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.053095                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.053095                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13680.236111                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13680.236111                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          882                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               53                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.641509                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        18120                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        18120                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        18120                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        18120                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        18120                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        18120                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       439780                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       439780                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       439780                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       439780                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       439780                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       439780                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5188034078                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5188034078                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5188034078                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5188034078                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5188034078                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5188034078                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      4304000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      4304000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      4304000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      4304000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.050994                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.050994                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.050994                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           227040                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          492.830733                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7082160                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           227406                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            31.143242                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      99092137500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.830733                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.962560                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.962560                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          366                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          366                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.714844                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         32684037                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        32684037                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3792757                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3792757                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3094601                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3094601                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        14161                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        14161                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        75622                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        75622                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        75613                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        75613                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6887358                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6887358                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6901519                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6901519                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       187422                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       187422                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       806941                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       806941                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        41483                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        41483                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10414                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        10414                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9617                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         9617                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       994363                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        994363                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1035846                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1035846                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2444126213                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2444126213                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  27779707617                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  27779707617                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     86490246                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     86490246                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53209125                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     53209125                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data        14000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total        14000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  30223833830                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  30223833830                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  30223833830                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  30223833830                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3980179                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3980179                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3901542                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3901542                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        55644                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        55644                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86036                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        86036                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85230                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        85230                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7881721                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7881721                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7937365                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7937365                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.047089                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.047089                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.206826                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.206826                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.745507                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.745507                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121042                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121042                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112836                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112836                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.126161                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.126161                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.130503                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.130503                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8305.189745                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8305.189745                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5532.819486                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5532.819486                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs         4476                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs              723                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     6.190871                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       207281                       # number of writebacks
system.cpu1.dcache.writebacks::total           207281                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        70540                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        70540                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       693700                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       693700                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          500                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          500                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       764240                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       764240                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       764240                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       764240                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116882                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       116882                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       113241                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       113241                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23891                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23891                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9914                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9914                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9617                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         9617                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       230123                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       230123                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       254014                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       254014                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1203808322                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1203808322                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3988299754                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3988299754                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    341716536                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    341716536                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     60834504                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     60834504                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     33974875                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     33974875                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data        12000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total        12000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5192108076                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   5192108076                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5533824612                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5533824612                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    522517625                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    522517625                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029366                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029366                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.029025                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.029025                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.429354                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.429354                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.115231                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.115231                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112836                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112836                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029197                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029197                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032002                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032002                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6136.221908                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6136.221908                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3532.793491                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3532.793491                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1736665659303                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   52427                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   40685                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------