path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.825951                       # Number of seconds simulated
sim_ticks                                2825951018000                       # Number of ticks simulated
final_tick                               2825951018000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 126581                       # Simulator instruction rate (inst/s)
host_op_rate                                   153564                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2973571752                       # Simulator tick rate (ticks/s)
host_mem_usage                                 617520                       # Number of bytes of host memory used
host_seconds                                   950.36                       # Real time elapsed on the host
sim_insts                                   120297223                       # Number of instructions simulated
sim_ops                                     145940268                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         1600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1286144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1281192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8384576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           188912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           582932                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       428544                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12155436                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1286144                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       188912                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1475056                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8692480                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8710044                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           25                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             22343                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20539                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       131009                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3020                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9129                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6696                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                192785                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          135820                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               140211                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           566                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              455119                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              453367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2966993                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               66849                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              206278                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       151646                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4301361                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         455119                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          66849                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             521968                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3075949                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6201                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3082164                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3075949                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          566                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             455119                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             459568                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2966993                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              66849                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             206292                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       151646                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7383525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        192786                       # Number of read requests accepted
system.physmem.writeReqs                       140211                       # Number of write requests accepted
system.physmem.readBursts                      192786                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     140211                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12328960                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8722752                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12155500                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8710044                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11498                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11843                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12508                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12790                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14191                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11869                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11798                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11857                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12385                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12638                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11524                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10795                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11419                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12202                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11695                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11628                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8335                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8752                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9292                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9229                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7962                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8394                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8300                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8278                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8796                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9162                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8546                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8147                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8256                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8410                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8295                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8139                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
system.physmem.totGap                    2825950731000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  189120                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 135820                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     58633                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     71115                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      6243                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      5114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4480                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1398                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      907                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      653                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3577                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4774                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88838                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      236.966703                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     133.563892                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     301.532977                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          48504     54.60%     54.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17119     19.27%     73.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5692      6.41%     80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3330      3.75%     84.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2666      3.00%     87.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1452      1.63%     88.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          904      1.02%     89.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1002      1.13%     90.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8169      9.20%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88838                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6725                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.644610                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      576.008815                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6723     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6725                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6725                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.266617                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.732165                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.286650                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5583     83.02%     83.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             392      5.83%     88.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              83      1.23%     90.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              55      0.82%     90.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             273      4.06%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              27      0.40%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              22      0.33%     95.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              18      0.27%     95.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              21      0.31%     96.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.18%     96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.13%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               9      0.13%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             148      2.20%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.13%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.10%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.10%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              12      0.18%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.04%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             4      0.06%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.16%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6725                       # Writes before turning the bus around for reads
system.physmem.totQLat                     6328126220                       # Total ticks spent queuing
system.physmem.totMemAccLat                9940126220                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    963200000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32849.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51599.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.36                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.09                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.30                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.08                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.86                       # Average write queue length when enqueuing
system.physmem.readRowHits                     160949                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     79145                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.55                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.06                       # Row buffer hit rate for writes
system.physmem.avgGap                      8486414.99                       # Average gap between requests
system.physmem.pageHitRate                      72.99                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  340562880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  185823000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 767153400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                444152160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184577274960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            79601761125                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1625743658250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1891660385775                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.389284                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2704476978140                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94364660000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27109359860                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  331052400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  180633750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 735430800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                439026480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184577274960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79228268055                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1626071283750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1891562970195                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.354813                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2705022466825                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94364660000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26562494425                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          112                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          176                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          288                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             18                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           62                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              102                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           62                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          102                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               23820996                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         15588859                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           920395                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            14518297                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                9504336                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.464538                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3840995                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             33136                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        1356781                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           1203053                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          153728                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        48358                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    66654                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               66654                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25108                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18968                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        22578                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        44076                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   460.137036                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  2988.406264                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        42948     97.44%     97.44% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          855      1.94%     99.38% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          123      0.28%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767          110      0.25%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959            6      0.01%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           18      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535           13      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        44076                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        16898                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11121.375311                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9757.603879                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6791.562531                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383        15594     92.28%     92.28% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1190      7.04%     99.33% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           80      0.47%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535           11      0.07%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            8      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071           13      0.08%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-245759            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        16898                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  90055870948                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.547875                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.509370                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  89997968948     99.94%     99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     40556500      0.05%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5      7037000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4893500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      1776500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1132500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1239500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1264500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17         2000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  90055870948                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5227     78.38%     78.38% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1442     21.62%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6669                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        66654                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        66654                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6669                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6669                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        73323                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17666854                       # DTB read hits
system.cpu0.dtb.read_misses                     56136                       # DTB read misses
system.cpu0.dtb.write_hits                   14559303                       # DTB write hits
system.cpu0.dtb.write_misses                    10518                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3504                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      145                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2262                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      861                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17722990                       # DTB read accesses
system.cpu0.dtb.write_accesses               14569821                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32226157                       # DTB hits
system.cpu0.dtb.misses                          66654                       # DTB misses
system.cpu0.dtb.accesses                     32292811                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    10841                       # Table walker walks requested
system.cpu0.itb.walker.walksShort               10841                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3909                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5864                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         1068                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         9773                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean   421.927760                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  2234.177799                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095         9414     96.33%     96.33% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191          161      1.65%     97.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287          108      1.11%     99.08% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383           59      0.60%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479            8      0.08%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575           12      0.12%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767            3      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863            3      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         9773                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3645                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12199.451303                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11419.234768                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4654.618910                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          570     15.64%     15.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         2859     78.44%     94.07% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          148      4.06%     98.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           43      1.18%     99.31% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           22      0.60%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3645                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  21336382212                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.847765                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.359386                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     3249113500     15.23%     15.23% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    18086389212     84.77%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2         793000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3          86500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  21336382212                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2247     87.19%     87.19% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          330     12.81%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2577                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2577                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2577                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        13418                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    37363257                       # ITB inst hits
system.cpu0.itb.inst_misses                     10841                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2348                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1915                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                37374098                       # ITB inst accesses
system.cpu0.itb.hits                         37363257                       # DTB hits
system.cpu0.itb.misses                          10841                       # DTB misses
system.cpu0.itb.accesses                     37374098                       # DTB accesses
system.cpu0.numCycles                       130634754                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          18759180                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     111594210                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   23820996                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          14548384                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    105958075                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2723782                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    147803                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               57411                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       403538                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       420731                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles        91570                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 37362977                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               256682                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   5313                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         127200199                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.057439                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.258294                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                65301995     51.34%     51.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                21243041     16.70%     68.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 8702131      6.84%     74.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                31953032     25.12%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           127200199                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.182348                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.854246                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                19580299                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             60730761                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 40895062                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              4960019                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1034058                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             3027631                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               331959                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             109730420                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              3757258                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1034058                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                25213970                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12473804                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      37385885                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 40084231                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             11008251                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             104776923                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1005898                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1454281                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                163264                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 59868                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               6802738                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          108917617                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            478329249                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       119800886                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             9453                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             97884799                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                11032807                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1224750                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1083467                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12359769                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            18590109                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           16025944                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1692928                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2223672                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 101900058                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1687234                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                100089682                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           451563                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        8991464                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     21250511                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        118873                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    127200199                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.786867                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.029325                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           71273767     56.03%     56.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           23216726     18.25%     74.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           22358125     17.58%     91.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            9249672      7.27%     99.13% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1101855      0.87%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 54      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      127200199                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                9294441     40.55%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    68      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5565368     24.28%     64.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8061478     35.17%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             66026932     65.97%     65.97% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               92216      0.09%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8071      0.01%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            18353253     18.34%     84.41% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           15606936     15.59%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             100089682                       # Type of FU issued
system.cpu0.iq.rate                          0.766180                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   22921355                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.229008                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         350720067                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        112586232                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     98062666                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              32413                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             11362                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         9718                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             122987773                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  20991                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          362703                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1887830                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2440                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        18911                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       876012                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       109448                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       364606                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1034058                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1622257                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               187065                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          103740401                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             18590109                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            16025944                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            873149                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 28190                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               135133                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         18911                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        251727                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       397563                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              649290                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             99070135                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             17913102                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           953014                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       153109                       # number of nop insts executed
system.cpu0.iew.exec_refs                    33359413                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                16770669                       # Number of branches executed
system.cpu0.iew.exec_stores                  15446311                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.758375                       # Inst execution rate
system.cpu0.iew.wb_sent                      98522156                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     98072384                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 51087973                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 84406715                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.750737                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.605260                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts        7992419                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1568361                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           592562                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    125525573                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.754570                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.472389                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     81342054     64.80%     64.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     24610935     19.61%     84.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      8228457      6.56%     90.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3212332      2.56%     93.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      3423017      2.73%     96.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      1492381      1.19%     97.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1160319      0.92%     98.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       551485      0.44%     98.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1504593      1.20%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    125525573                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            78721743                       # Number of instructions committed
system.cpu0.commit.committedOps              94717871                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      31852210                       # Number of memory references committed
system.cpu0.commit.loads                     16702278                       # Number of loads committed
system.cpu0.commit.membars                     645830                       # Number of memory barriers committed
system.cpu0.commit.branches                  16170329                       # Number of branches committed
system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 81695650                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             1925626                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        62767692     66.27%     66.27% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          89898      0.09%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.36% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8071      0.01%     66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       16702278     17.63%     84.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      15149932     15.99%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         94717871                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1504593                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   222549197                       # The number of ROB reads
system.cpu0.rob.rob_writes                  207085893                       # The number of ROB writes
system.cpu0.timesIdled                         123342                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3434555                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5521267593                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   78599691                       # Number of Instructions Simulated
system.cpu0.committedOps                     94595819                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.662026                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.662026                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.601675                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.601675                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               110021691                       # number of integer regfile reads
system.cpu0.int_regfile_writes               59386115                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     8176                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                349047979                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                40883845                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              177564457                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1222085                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           709600                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          499.965510                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           28702051                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           710112                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            40.419048                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        278078500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   499.965510                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.976495                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.976495                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63247390                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63247390                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15498209                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15498209                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     11982969                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      11982969                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307264                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       307264                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       362251                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       362251                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360359                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       360359                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     27481178                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        27481178                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     27788442                       # number of overall hits
system.cpu0.dcache.overall_hits::total       27788442                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       646938                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       646938                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1889976                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1889976                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147980                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       147980                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25182                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        25182                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20295                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20295                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2536914                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2536914                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2684894                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2684894                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8613079000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   8613079000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29673912872                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  29673912872                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    399362500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    399362500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    493278500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    493278500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       493500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       493500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  38286991872                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  38286991872                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  38286991872                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  38286991872                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16145147                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16145147                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13872945                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13872945                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       455244                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       455244                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       380654                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       380654                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30018092                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30018092                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30473336                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30473336                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040070                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.040070                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136235                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.136235                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.325056                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.325056                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064997                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064997                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053316                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053316                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084513                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.084513                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088106                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.088106                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13313.608105                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13313.608105                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15700.682375                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15700.682375                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15859.046144                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15859.046144                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24305.420054                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24305.420054                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15091.954978                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15091.954978                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14260.150260                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14260.150260                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         1062                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      4223116                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               45                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         202030                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.600000                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    20.903410                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       709603                       # number of writebacks
system.cpu0.dcache.writebacks::total           709603                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       260771                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       260771                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1564893                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1564893                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18568                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18568                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1825664                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1825664                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1825664                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1825664                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       386167                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       386167                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325083                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       325083                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102058                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       102058                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6614                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6614                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20295                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20295                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       711250                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       711250                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       813308                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       813308                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20340                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20340                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19033                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19033                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39373                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39373                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4553087000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4553087000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6070046902                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6070046902                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1659761500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1659761500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103454000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103454000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    472996500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    472996500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       480500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       480500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10623133902                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10623133902                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12282895402                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12282895402                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4534665000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4534665000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4534665000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4534665000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023918                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023918                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023433                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023433                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224183                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224183                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017071                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017071                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053316                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053316                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023694                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023694                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026689                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026689                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11790.461122                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11790.461122                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18672.298773                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18672.298773                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16262.924024                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16262.924024                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15641.669187                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15641.669187                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23306.060606                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23306.060606                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14935.864889                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14935.864889                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15102.390979                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15102.390979                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222943.215339                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222943.215339                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115171.945242                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115171.945242                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          1244973                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.762786                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36061117                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1245485                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            28.953474                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6512698000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.762786                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999537                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999537                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         75964361                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        75964361                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     36061117                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36061117                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36061117                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36061117                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36061117                       # number of overall hits
system.cpu0.icache.overall_hits::total       36061117                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1298298                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1298298                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1298298                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1298298                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1298298                       # number of overall misses
system.cpu0.icache.overall_misses::total      1298298                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13095750432                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13095750432                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13095750432                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13095750432                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13095750432                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13095750432                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     37359415                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     37359415                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     37359415                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     37359415                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     37359415                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     37359415                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034752                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.034752                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034752                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.034752                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034752                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.034752                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10086.860206                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10086.860206                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10086.860206                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10086.860206                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10086.860206                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10086.860206                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1564537                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          822                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           111550                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.025433                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets    74.727273                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1244973                       # number of writebacks
system.cpu0.icache.writebacks::total          1244973                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        52766                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        52766                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        52766                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        52766                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        52766                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        52766                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1245532                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1245532                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1245532                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1245532                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1245532                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1245532                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11887458427                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11887458427                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11887458427                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11887458427                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11887458427                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11887458427                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    269145498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    269145498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033339                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033339                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033339                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.033339                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033339                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.033339                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9544.081105                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9544.081105                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9544.081105                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9544.081105                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9544.081105                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9544.081105                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1836444                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1838932                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         2249                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       237260                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          275777                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16077.094616                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3264993                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          291873                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           11.186348                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14642.260262                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    14.030425                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.082237                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1420.721692                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.893693                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000856                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.086714                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981268                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1015                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15073                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          314                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          375                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          282                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          477                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4659                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6956                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2859                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061951                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.919983                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        66024498                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       66024498                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        55983                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        13286                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         69269                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       482066                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       482066                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1441412                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1441412                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       221318                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       221318                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1193309                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1193309                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       398313                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       398313                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        55983                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        13286                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1193309                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       619631                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1882209                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        55983                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        13286                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1193309                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       619631                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1882209                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          409                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          145                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          554                       # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55455                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55455                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20295                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20295                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48487                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        48487                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        52186                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        52186                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        96414                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        96414                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          409                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          145                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        52186                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144901                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       197641                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          409                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          145                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        52186                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144901                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       197641                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     11428500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3458500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     14887000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    116593500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    116593500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     25461000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     25461000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       459500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       459500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2707524000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2707524000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2738746000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2738746000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2927576997                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2927576997                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     11428500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3458500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2738746000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5635100997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8388733997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     11428500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3458500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2738746000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5635100997                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8388733997                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        56392                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        13431                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        69823                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       482067                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       482067                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1441412                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1441412                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55456                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55456                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20295                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20295                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269805                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269805                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1245495                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1245495                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       494727                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       494727                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        56392                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        13431                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1245495                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       764532                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2079850                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        56392                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        13431                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1245495                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       764532                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2079850                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007253                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.010796                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.007934                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000002                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000002                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.179711                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.179711                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.041900                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.041900                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.194883                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.194883                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007253                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.010796                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.041900                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.189529                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.095027                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007253                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.010796                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.041900                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.189529                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.095027                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27942.542787                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23851.724138                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26871.841155                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2102.488504                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2102.488504                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1254.545455                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1254.545455                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55840.204591                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55840.204591                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52480.473690                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52480.473690                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30364.646182                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30364.646182                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27942.542787                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23851.724138                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52480.473690                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38889.317513                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 42444.300510                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27942.542787                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23851.724138                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52480.473690                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38889.317513                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 42444.300510                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           92                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    30.666667                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10565                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       229088                       # number of writebacks
system.cpu0.l2cache.writebacks::total          229088                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5680                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5680                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           39                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           39                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          771                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          771                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           39                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6451                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6490                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           39                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6451                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6490                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          409                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          145                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          554                       # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       255939                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       255939                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55455                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55455                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20295                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20295                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42807                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        42807                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        52147                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        52147                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        95643                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        95643                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          409                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          145                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        52147                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       138450                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       191151                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          409                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          145                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        52147                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       138450                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       255939                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       447090                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20340                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23343                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19033                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19033                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39373                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42376                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      8974500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2588500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     11563000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15061119493                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15061119493                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1081830000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1081830000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    319630999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    319630999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       381500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       381500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1771002000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1771002000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2424780500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2424780500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2310424997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2310424997                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      8974500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2588500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2424780500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4081426997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6517770497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      8974500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2588500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2424780500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4081426997                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15061119493                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21578889990                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4371667500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4618288500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4371667500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4618288500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007253                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010796                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.007934                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000002                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158659                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158659                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041868                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041868                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.193325                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.193325                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007253                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.010796                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041868                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.181091                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.091906                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007253                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.010796                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041868                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.181091                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.214963                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20871.841155                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58846.520042                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19508.249932                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19508.249932                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15749.248534                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15749.248534                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41371.784988                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41371.784988                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46498.945289                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46498.945289                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24156.760003                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24156.760003                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46498.945289                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29479.429375                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34097.496205                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46498.945289                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29479.429375                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48265.203852                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214929.572271                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197844.685773                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111032.115917                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108983.587408                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      4059553                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2049525                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31130                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       322631                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       318742                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3889                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        102054                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1891052                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19033                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19033                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       711408                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1472505                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       201922                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       326386                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87454                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42857                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       113442                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           28                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       288333                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284690                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1245532                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       576445                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3297                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3742005                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2570285                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29068                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119436                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6460794                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    159437936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98528220                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53724                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       225568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         258245448                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1026066                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3122672                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.120692                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.329569                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2749681     88.06%     88.06% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            369102     11.82%     99.88% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              3889      0.12%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3122672                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    4044815993                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114413841                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1871838919                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1215906771                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     15648976                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     63082921                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               34009026                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         11598982                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           286954                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            18822923                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                6035110                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            32.062555                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               12529712                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7339                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        9024222                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           8987643                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           36579                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        11117                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    22019                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               22019                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8988                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5922                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore         7109                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        14910                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   597.183099                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3274.563107                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095        14271     95.71%     95.71% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191          175      1.17%     96.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287          226      1.52%     98.40% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383           97      0.65%     99.05% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479           36      0.24%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575           18      0.12%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671            9      0.06%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767           63      0.42%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863            6      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959            4      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343            3      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        14910                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5586                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11231.919083                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9899.070869                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6145.006909                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1859     33.28%     33.28% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         3110     55.67%     88.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          395      7.07%     96.03% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          162      2.90%     98.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           30      0.54%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           25      0.45%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            2      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5586                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  72596800264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.178979                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.387926                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    59651088264     82.17%     82.17% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    12923549000     17.80%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2       13278500      0.02%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3        4124000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4        1159000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5         892500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6        1267000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7         399000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8         261000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9         175000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10        102500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11         47000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12        179500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13         63000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14         38500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15        176500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  72596800264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1935     74.77%     74.77% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          653     25.23%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22019                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22019                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2588                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24607                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10217146                       # DTB read hits
system.cpu1.dtb.read_misses                     19031                       # DTB read misses
system.cpu1.dtb.write_hits                    6545704                       # DTB write hits
system.cpu1.dtb.write_misses                     2988                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2034                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       49                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   375                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      389                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10236177                       # DTB read accesses
system.cpu1.dtb.write_accesses                6548692                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16762850                       # DTB hits
system.cpu1.dtb.misses                          22019                       # DTB misses
system.cpu1.dtb.accesses                     16784869                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     6065                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                6065                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2849                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2599                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          617                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         5448                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   300.018355                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  2054.443929                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095         5317     97.60%     97.60% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191           57      1.05%     98.64% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287           30      0.55%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383           22      0.40%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479            8      0.15%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575            4      0.07%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671            5      0.09%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-32767            3      0.06%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-36863            2      0.04%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         5448                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1777                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11882.104671                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10854.352895                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5876.427895                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          298     16.77%     16.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1356     76.31%     93.08% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575           64      3.60%     96.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           25      1.41%     98.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           23      1.29%     99.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            4      0.23%     99.61% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            3      0.17%     99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535            3      0.17%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1777                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  16742440916                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.881191                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.323702                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1989886764     11.89%     11.89% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    14751845152     88.11%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2         691000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3          18000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  16742440916                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          988     85.17%     85.17% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          172     14.83%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1160                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6065                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6065                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1160                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1160                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         7225                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    43720811                       # ITB inst hits
system.cpu1.itb.inst_misses                      6065                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1192                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      560                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                43726876                       # ITB inst accesses
system.cpu1.itb.hits                         43720811                       # DTB hits
system.cpu1.itb.misses                           6065                       # DTB misses
system.cpu1.itb.accesses                     43726876                       # DTB accesses
system.cpu1.numCycles                       106544770                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          10285169                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     109329590                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   34009026                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          27552465                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     93003678                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3760962                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     80448                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               30144                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       178688                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       297988                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles        23992                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 43719656                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               111494                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2187                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         105780588                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.280193                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.339076                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                48754447     46.09%     46.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                14049982     13.28%     59.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 7558912      7.15%     66.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                35417247     33.48%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           105780588                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.319199                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.026138                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                13239589                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             62906745                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 26778529                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1104926                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1750799                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              750846                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               132411                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              68206477                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              1115402                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1750799                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17653779                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2374666                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      57902702                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 23447751                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2650891                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              55293666                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               220143                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               265669                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 37332                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 18647                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1622767                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           55225885                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            261143833                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        58792741                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             1698                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             52650074                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2575811                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1881943                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1808403                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 13140602                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            10477180                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6893389                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           629902                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          660425                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  54420167                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             587049                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 54175023                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            95968                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        3662766                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      5235414                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         44205                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    105780588                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.512145                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.849831                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           72358023     68.40%     68.40% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           16614078     15.71%     84.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           13151335     12.43%     96.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3370344      3.19%     99.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             286797      0.27%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                 11      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      105780588                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2941757     45.24%     45.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   670      0.01%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1685952     25.93%     71.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1873492     28.81%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             36944686     68.20%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46486      0.09%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3329      0.01%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            10429510     19.25%     87.54% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6750946     12.46%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              54175023                       # Type of FU issued
system.cpu1.iq.rate                          0.508472                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    6501871                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.120016                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         220722500                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         58678222                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     52198206                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads               5973                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              2102                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         1789                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              60672989                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   3839                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           91219                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       444760                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          748                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        10369                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       281379                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        52226                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        78419                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1750799                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 547306                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               107318                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           55048106                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             10477180                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6893389                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            299581                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  8072                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                92519                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         10369                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         45476                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       122774                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              168250                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             53925594                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10330118                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           227431                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        40890                       # number of nop insts executed
system.cpu1.iew.exec_refs                    17028825                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                11888375                       # Number of branches executed
system.cpu1.iew.exec_stores                   6698707                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.506131                       # Inst execution rate
system.cpu1.iew.wb_sent                      53782194                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     52199995                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 25393405                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 38775074                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.489935                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.654890                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        3417074                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         542844                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           157272                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    103878319                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.494591                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.150147                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     77963106     75.05%     75.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     14542376     14.00%     89.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6113605      5.89%     94.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       710011      0.68%     95.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1999110      1.92%     97.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      1749013      1.68%     99.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       272868      0.26%     99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       126868      0.12%     99.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       401362      0.39%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    103878319                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            41730387                       # Number of instructions committed
system.cpu1.commit.committedOps              51377304                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16644430                       # Number of memory references committed
system.cpu1.commit.loads                     10032420                       # Number of loads committed
system.cpu1.commit.membars                     210881                       # Number of memory barriers committed
system.cpu1.commit.branches                  11730295                       # Number of branches committed
system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 46164743                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             3380868                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        34684147     67.51%     67.51% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          45398      0.09%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3329      0.01%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       10032420     19.53%     87.13% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       6612010     12.87%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         51377304                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               401362                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   138158228                       # The number of ROB reads
system.cpu1.rob.rob_writes                  111482281                       # The number of ROB writes
system.cpu1.timesIdled                          55620                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         764182                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5544797786                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   41697532                       # Number of Instructions Simulated
system.cpu1.committedOps                     51344449                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.555182                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.555182                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.391362                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.391362                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                56568285                       # number of integer regfile reads
system.cpu1.int_regfile_writes               35909809                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     1388                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                192177585                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                15728126                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              146901400                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                390692                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements           191412                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          467.958660                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           15830019                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           191751                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            82.555079                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      89229031500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   467.958660                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.913982                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.913982                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          339                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          338                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.662109                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         33166441                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        33166441                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      9618480                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9618480                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      5953541                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       5953541                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50151                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        50151                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79497                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        79497                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71560                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71560                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     15572021                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        15572021                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     15622172                       # number of overall hits
system.cpu1.dcache.overall_hits::total       15622172                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       219751                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       219751                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       400027                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       400027                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30362                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30362                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18466                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18466                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23631                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23631                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       619778                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        619778                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       650140                       # number of overall misses
system.cpu1.dcache.overall_misses::total       650140                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3494026000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3494026000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9769416956                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   9769416956                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    360558000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    360558000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    577732000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    577732000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       853500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       853500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  13263442956                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  13263442956                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  13263442956                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  13263442956                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9838231                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9838231                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6353568                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6353568                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80513                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        80513                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97963                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97963                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95191                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        95191                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16191799                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16191799                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16272312                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16272312                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022336                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.022336                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.062961                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.062961                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377107                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377107                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.188500                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.188500                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248248                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248248                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038277                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038277                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039954                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.039954                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15899.932196                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15899.932196                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24421.893912                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24421.893912                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19525.506336                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19525.506336                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24448.055520                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24448.055520                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21400.312622                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21400.312622                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20400.902815                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20400.902815                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          349                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1422803                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               30                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          40164                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.633333                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    35.424833                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       191413                       # number of writebacks
system.cpu1.dcache.writebacks::total           191413                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        80045                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        80045                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       309351                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       309351                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13126                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13126                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       389396                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       389396                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       389396                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       389396                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139706                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       139706                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        90676                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        90676                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28955                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        28955                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5340                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5340                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23631                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23631                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       230382                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       230382                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       259337                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       259337                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14528                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14528                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11864                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11864                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26392                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1929657000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1929657000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2407624467                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2407624467                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    488405000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    488405000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     91592000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     91592000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    554116000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    554116000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       838500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       838500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4337281467                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4337281467                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4825686467                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4825686467                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2529035000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2529035000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2529035000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2529035000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014200                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014272                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014272                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359631                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359631                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054510                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054510                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248248                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248248                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014228                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.014228                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015937                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.015937                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13812.270053                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13812.270053                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26551.948333                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26551.948333                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16867.725781                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16867.725781                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17152.059925                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17152.059925                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23448.690280                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23448.690280                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18826.477186                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18826.477186                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18607.782411                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18607.782411                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174080.052313                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174080.052313                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95825.818430                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95825.818430                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements           601488                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.448304                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           43094812                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           602000                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            71.586066                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      79058224000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.448304                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975485                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975485                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          496                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         88040802                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        88040802                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     43094812                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       43094812                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     43094812                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        43094812                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     43094812                       # number of overall hits
system.cpu1.icache.overall_hits::total       43094812                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       624586                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       624586                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       624586                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        624586                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       624586                       # number of overall misses
system.cpu1.icache.overall_misses::total       624586                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5619455793                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5619455793                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5619455793                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5619455793                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5619455793                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5619455793                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     43719398                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     43719398                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     43719398                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     43719398                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     43719398                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     43719398                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014286                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014286                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014286                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014286                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014286                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014286                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8997.088941                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8997.088941                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8997.088941                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8997.088941                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8997.088941                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8997.088941                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       497106                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            2                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            41763                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.903024                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets            2                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       601488                       # number of writebacks
system.cpu1.icache.writebacks::total           601488                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        22580                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        22580                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        22580                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        22580                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        22580                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        22580                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       602006                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       602006                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       602006                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       602006                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       602006                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       602006                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5157000587                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5157000587                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5157000587                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5157000587                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5157000587                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5157000587                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9463000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9463000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9463000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9463000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013770                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013770                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013770                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013770                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013770                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013770                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8566.360779                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8566.360779                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8566.360779                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8566.360779                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8566.360779                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8566.360779                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92774.509804                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92774.509804                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.num_hwpf_issued       196563                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       197115                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          493                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59469                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           47848                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15152.810983                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1369588                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           62482                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           21.919721                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14657.752176                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     9.247040                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.961226                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   482.850541                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.894638                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000564                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000181                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.029471                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.924854                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1015                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           31                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13588                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           15                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          873                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          127                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          454                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8865                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4269                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.061951                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001892                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.829346                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        27297276                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       27297276                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        17323                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         6382                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         23705                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       116494                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       116494                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       663845                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       663845                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27330                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27330                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       585501                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       585501                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       105069                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       105069                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        17323                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         6382                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       585501                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       132399                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         741605                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        17323                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6382                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       585501                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       132399                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        741605                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          436                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          251                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          687                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29837                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29837                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23628                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23628                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34183                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34183                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        16502                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        16502                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        68911                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        68911                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          436                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          251                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        16502                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       103094                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       120283                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          436                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          251                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        16502                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       103094                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       120283                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9535000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5307000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     14842000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65279500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     65279500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     35645500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     35645500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       815499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       815499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1382048000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1382048000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    678918000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    678918000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1543279999                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1543279999                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9535000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5307000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    678918000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2925327999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3619087999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9535000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5307000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    678918000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2925327999                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3619087999                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17759                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6633                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        24392                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       116494                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       116494                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       663845                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       663845                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29837                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29837                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23628                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23628                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61513                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61513                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       602003                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       602003                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       173980                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       173980                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17759                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6633                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       602003                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       235493                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       861888                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17759                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6633                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       602003                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       235493                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       861888                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024551                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.037841                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.028165                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555704                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555704                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027412                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027412                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.396086                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.396086                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024551                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.037841                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027412                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.437779                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.139558                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024551                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.037841                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027412                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.437779                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.139558                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21869.266055                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21143.426295                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21604.075691                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2187.870764                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2187.870764                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1508.612663                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1508.612663                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       271833                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       271833                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40430.857444                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40430.857444                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41141.558599                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41141.558599                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22395.263441                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22395.263441                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21869.266055                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21143.426295                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41141.558599                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28375.346761                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30088.108868                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21869.266055                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21143.426295                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41141.558599                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28375.346761                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30088.108868                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           77                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    25.666667                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             878                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        32705                       # number of writebacks
system.cpu1.l2cache.writebacks::total           32705                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          447                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          447                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           70                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           70                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          517                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          526                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          517                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          526                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          436                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          251                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          687                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25391                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        25391                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29837                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29837                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23628                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23628                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33736                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33736                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        16493                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        16493                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        68841                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        68841                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          436                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          251                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        16493                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       102577                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       119757                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          436                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          251                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        16493                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       102577                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25391                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       145148                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14528                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14630                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11864                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11864                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26494                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6919000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3801000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10720000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1003077137                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1003077137                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    504358500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    504358500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    376609000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    376609000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       725499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       725499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1128947000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1128947000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    579803500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    579803500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1128190999                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1128190999                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6919000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3801000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    579803500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2257137999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2847661499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6919000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3801000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    579803500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2257137999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1003077137                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3850738636                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8698000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2412762500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2421460500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8698000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2412762500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2421460500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024551                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.037841                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028165                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.548437                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.548437                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027397                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027397                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.395683                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.395683                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024551                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.037841                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027397                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.435584                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.138947                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024551                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.037841                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027397                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.435584                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.168407                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15604.075691                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39505.223780                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16903.793947                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16903.793947                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15939.097681                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15939.097681                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       241833                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       241833                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33464.162912                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33464.162912                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35154.520099                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35154.520099                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16388.358667                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16388.358667                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35154.520099                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22004.328446                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23778.664287                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35154.520099                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22004.328446                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26529.739549                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166076.713932                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165513.362953                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91420.222037                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91396.561486                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1693819                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       856333                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12567                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       183235                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       181854                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1381                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         43509                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       857970                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11864                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11864                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       150213                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       676407                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       108999                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        30864                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        72606                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41945                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86317                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           28                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        68814                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66024                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       602006                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       255355                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          206                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1805701                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       897982                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14680                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        38591                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2756954                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     77025056                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     30176714                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        26532                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        71036                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         107299338                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     403916                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1269906                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.163115                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.372403                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1064146     83.80%     83.80% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            204379     16.09%     99.89% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1381      0.11%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1269906                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1668457495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80964876                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    903243234                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    401728937                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      8056980                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     20851461                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31007                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31007                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59421                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180856                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484002                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40388000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               330000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                32000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               574500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6116000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            33795000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187654365                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84717000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36766000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36453                       # number of replacements
system.iocache.tags.tagsinuse               14.555427                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36469                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         255133996000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.555427                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.909714                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.909714                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328239                       # Number of tag accesses
system.iocache.tags.data_accesses              328239                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          247                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              247                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36471                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36471                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36471                       # number of overall misses
system.iocache.overall_misses::total            36471                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32034877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32034877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4302643488                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4302643488                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4334678365                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4334678365                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4334678365                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4334678365                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          247                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            247                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36471                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36471                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36471                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36471                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129695.858300                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129695.858300                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118778.806537                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118778.806537                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118852.742316                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118852.742316                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118852.742316                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118852.742316                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            15                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    5                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          247                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          247                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36471                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36471                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36471                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36471                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19684877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19684877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2489128459                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2489128459                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2508813336                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2508813336                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2508813336                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2508813336                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79695.858300                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79695.858300                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68714.897830                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68714.897830                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68789.266431                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68789.266431                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68789.266431                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68789.266431                       # average overall mshr miss latency
system.l2c.tags.replacements                   126939                       # number of replacements
system.l2c.tags.tagsinuse                63214.740893                       # Cycle average of tags in use
system.l2c.tags.total_refs                     439035                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   190800                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.301022                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13659.794415                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    15.383881                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.061858                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8032.623601                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2877.626716                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34705.867730                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     3.664427                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.910014                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1967.326736                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      460.362743                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1490.118772                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.208432                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000235                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.122568                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043909                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.529570                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000056                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.030019                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.007025                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.022737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.964580                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29285                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           18                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34558                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          182                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5757                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23342                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          611                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6476                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        27436                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.446854                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000275                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.527313                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6030021                       # Number of tag accesses
system.l2c.tags.data_accesses                 6030021                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       261794                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          261794                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32586                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2322                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               34908                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2057                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1031                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3088                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3923                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1723                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5646                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          188                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           73                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        32795                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        46613                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46486                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           68                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           36                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        13556                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         9028                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5103                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           153946                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           188                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            73                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               32795                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               50536                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46486                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            68                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            36                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               13556                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               10751                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5103                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  159592                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          188                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           73                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              32795                       # number of overall hits
system.l2c.overall_hits::cpu0.data              50536                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46486                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           68                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           36                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              13556                       # number of overall hits
system.l2c.overall_hits::cpu1.data              10751                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5103                       # number of overall hits
system.l2c.overall_hits::total                 159592                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9262                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3049                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12311                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          797                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1327                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2124                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11181                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8169                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19350                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           25                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19352                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9056                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131166                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            5                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2936                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          955                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6696                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         170195                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           25                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19352                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20237                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       131166                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2936                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9124                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6696                       # number of demand (read+write) misses
system.l2c.demand_misses::total                189545                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           25                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19352                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20237                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       131166                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2936                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9124                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6696                       # number of overall misses
system.l2c.overall_misses::total               189545                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     10685000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2955500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     13640500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1570500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1260500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2831000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1150734500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    687988500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1838723000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2363000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       241000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1607400500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    824224000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  14216291987                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       522500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        83500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    250906500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data     89245500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    887434795                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  17878713282                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2363000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       241000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1607400500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1974958500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14216291987                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       522500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    250906500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    777234000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    887434795                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19717436282                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2363000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       241000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1607400500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1974958500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14216291987                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       522500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    250906500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    777234000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    887434795                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19717436282                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       261794                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       261794                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41848                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5371                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           47219                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2854                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2358                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5212                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15104                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9892                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24996                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          213                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           76                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        52147                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55669                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       177652                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           73                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           37                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        16492                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         9983                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11799                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       324141                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          213                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           76                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           52147                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           70773                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       177652                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           73                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           37                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           16492                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           19875                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11799                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              349137                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          213                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           76                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          52147                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          70773                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       177652                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           73                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           37                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          16492                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          19875                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11799                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             349137                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.221325                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.567678                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.260721                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.279257                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.562765                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.407521                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.740267                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.825819                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.774124                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.117371                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.039474                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.371105                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.162676                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.068493                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.027027                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.178026                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.095663                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.525065                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.117371                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.039474                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.371105                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.285942                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.068493                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.027027                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.178026                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.459069                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.542896                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.117371                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.039474                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.371105                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.285942                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.068493                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.027027                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.178026                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.459069                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.542896                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1153.638523                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   969.334208                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1107.992852                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1970.514429                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   949.886963                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1332.862524                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102918.746087                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84219.427102                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 95024.444444                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        94520                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83061.208144                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91014.134276                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       104500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85458.617166                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93450.785340                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 105048.404959                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        94520                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 83061.208144                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 97591.466126                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       104500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85458.617166                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85185.664182                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 104025.093155                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        94520                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 83061.208144                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 97591.466126                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       104500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85458.617166                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85185.664182                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 104025.093155                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               838                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    104.750000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               99614                       # number of writebacks
system.l2c.writebacks::total                    99614                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3468                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3468                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9262                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3049                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12311                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          797                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1327                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2124                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11181                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8169                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19350                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           25                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19350                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9056                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131166                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            5                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2929                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          955                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6696                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       170186                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           25                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19350                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20237                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131166                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2929                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9124                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6696                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           189536                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           25                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19350                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20237                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131166                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2929                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9124                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6696                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          189536                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20340                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14525                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        37970                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19033                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11864                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30897                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39373                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26389                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        68867                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    221469500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     70279500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    291749000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     20549499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     32977500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     53526999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1038924500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    606298001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1645222501                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      2113000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       211000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1413871007                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    733663501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12904628993                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       472500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        73500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    221234502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     79695500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    820473798                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  16176437301                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2113000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       211000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1413871007                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1772588001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12904628993                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       472500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    221234502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    685993501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    820473798                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17821659802                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2113000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       211000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1413871007                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1772588001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12904628993                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       472500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    221234502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    685993501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    820473798                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17821659802                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4005508001                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6861000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2151256501                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6356192002                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005508001                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6861000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2151256501                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6356192002                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.221325                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.567678                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.260721                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.279257                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.562765                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.407521                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.740267                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.825819                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.774124                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.117371                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.039474                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.371066                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.162676                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.068493                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.027027                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.177601                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.095663                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.525037                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.117371                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.039474                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.371066                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.285942                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.068493                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.027027                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.177601                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.459069                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.542870                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.117371                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.039474                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.371066                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.285942                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738331                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.068493                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.027027                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.177601                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.459069                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.567506                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.542870                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23911.628158                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23050.016399                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23698.237349                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25783.562108                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24851.168048                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25201.035311                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92918.746087                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74219.366018                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 85024.418656                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        84520                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73068.269096                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81014.079174                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        94500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75532.434961                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83450.785340                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95051.515994                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        84520                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73068.269096                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87591.441469                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        94500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75532.434961                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75185.609491                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 94027.835356                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        84520                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73068.269096                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87591.441469                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        94500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75532.434961                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75185.609491                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 94027.835356                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196927.630334                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148107.160138                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167400.368765                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101732.354685                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81520.955739                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92296.629765                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        514606                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       294659                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          567                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq               37970                       # Transaction distribution
system.membus.trans_dist::ReadResp             208402                       # Transaction distribution
system.membus.trans_dist::WriteReq              30897                       # Transaction distribution
system.membus.trans_dist::WriteResp             30897                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       135820                       # Transaction distribution
system.membus.trans_dist::CleanEvict            15995                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            76425                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40810                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             38865                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19252                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170433                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107914                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13670                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       646867                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       768487                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 841426                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27340                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18547336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18737758                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21055902                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           122883                       # Total snoops (count)
system.membus.snoop_fanout::samples            431628                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.011899                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.108432                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  426492     98.81%     98.81% # Request fanout histogram
system.membus.snoop_fanout::1                    5136      1.19%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              431628                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81611500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11561000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           995379161                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1093943847                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1316877                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      1005681                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       545297                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       156423                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20020                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19070                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          950                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              37973                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            482978                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30897                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30897                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       361408                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          120637                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          111235                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43898                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         155133                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           28                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           28                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50623                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50623                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       445008                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4567                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1196695                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       348487                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1545182                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34087104                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5287070                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39374174                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          380983                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           851193                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.382254                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.488230                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 526771     61.89%     61.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 323472     38.00%     99.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    950      0.11%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             851193                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          876200249                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           348123                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         630764010                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         246030993                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2756                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------