path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.102940                       # Number of seconds simulated
sim_ticks                                1102940172000                       # Number of ticks simulated
final_tick                               1102940172000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  65652                       # Simulator instruction rate (inst/s)
host_op_rate                                    84510                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1175755462                       # Simulator tick rate (ticks/s)
host_mem_usage                                 411412                       # Number of bytes of host memory used
host_seconds                                   938.07                       # Real time elapsed on the host
sim_insts                                    61586245                       # Number of instructions simulated
sim_ops                                      79276446                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           409472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4368500                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           405632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5247536                       # Number of bytes read from this memory
system.physmem.bytes_read::total             59192100                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       409472                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       405632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          815104                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4269568                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7296912                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6094848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           11                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6398                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68330                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           17                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6338                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82019                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6257967                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66712                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823548                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        44208004                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           290                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              371255                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3960777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           986                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            58                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              367773                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4757770                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53667553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         371255                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         367773                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             739028                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3871079                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              15413                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2729381                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6615873                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3871079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       44208004                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          638                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          290                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             371255                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3976190                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          986                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           58                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             367773                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7487151                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               60283426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6257967                       # Total number of read requests seen
system.physmem.writeReqs                       823548                       # Total number of write requests seen
system.physmem.cpureqs                         242288                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    400509888                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52707072                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               59192100                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7296912                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      121                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              12562                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                391387                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                391216                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                390896                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                391623                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                391542                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                390911                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                390957                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                391661                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                391404                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                390709                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               390852                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               391233                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               391227                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               390512                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               390457                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               391259                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 51397                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 51233                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 51042                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51696                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51565                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51001                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51007                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51680                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 52040                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51354                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51500                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51879                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51844                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51252                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51165                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51893                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     2243059                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1102939019000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                     105                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6094848                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  163014                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 756836                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  66712                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    493693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    430180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    391390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1441411                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1086258                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1098726                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1064578                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     26935                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     24930                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     44513                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    63858                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    44248                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    12053                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    11796                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    17166                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     5937                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      152                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3047                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32635                       # What write queue length does an incoming req see
system.physmem.totQLat                   199192058500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              239013617250                       # Sum of mem lat for all requests
system.physmem.totBusLat                  31289230000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8532328750                       # Total cycles spent in bank access
system.physmem.avgQLat                       31830.77                       # Average queueing delay per request
system.physmem.avgBankLat                     1363.46                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  38194.23                       # Average memory access latency
system.physmem.avgRdBW                         363.13                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          47.79                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  53.67                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.62                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.21                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.22                       # Average read queue length over time
system.physmem.avgWrQLen                        12.05                       # Average write queue length over time
system.physmem.readRowHits                    6213954                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    800040                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.15                       # Row buffer hit rate for writes
system.physmem.avgGap                       155749.02                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         72718                       # number of replacements
system.l2c.tagsinuse                     53743.140165                       # Cycle average of tags in use
system.l2c.total_refs                         1840331                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        137862                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.349081                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        39373.587396                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       3.826422                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       1.187080                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4008.736100                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2822.118244                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      11.062372                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.921462                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3716.187342                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          3805.513745                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.600793                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000058                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000018                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.061168                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.043062                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000169                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.056705                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.058068                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.820055                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        22141                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4502                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             386239                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166660                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30329                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5168                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             590386                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             197820                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1403245                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          580806                       # number of Writeback hits
system.l2c.Writeback_hits::total               580806                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1235                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             743                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1978                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           201                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           145                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               346                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48231                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58599                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106830                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         22141                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              386239                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214891                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30329                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5168                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              590386                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              256419                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1510075                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        22141                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4502                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             386239                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214891                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30329                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5168                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             590386                       # number of overall hits
system.l2c.overall_hits::cpu1.data             256419                       # number of overall hits
system.l2c.overall_hits::total                1510075                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           11                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6277                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6416                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           17                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6302                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6301                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25330                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5125                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3774                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8899                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          638                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          411                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1049                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63279                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76923                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140202                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           11                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6277                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69695                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           17                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6302                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83224                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165532                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           11                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6277                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69695                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           17                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6302                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83224                       # number of overall misses
system.l2c.overall_misses::total               165532                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       728500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       324500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    347861000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    370402499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1384000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    379078500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    392453000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1492300499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8816984                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     11833500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     20650484                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       568000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2844000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3412000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3138283486                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4133582496                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7271865982                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       728500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       324500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    347861000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3508685985                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1384000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        68500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    379078500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4526035496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8764166481                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       728500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       324500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    347861000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3508685985                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1384000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        68500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    379078500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4526035496                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8764166481                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        22152                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4507                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         392516                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         173076                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30346                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5169                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         596688                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204121                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1428575                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       580806                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           580806                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6360                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4517                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10877                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          839                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          556                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1395                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111510                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135522                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247032                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        22152                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4507                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          392516                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284586                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30346                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5169                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          596688                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          339643                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1675607                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        22152                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4507                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         392516                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284586                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30346                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5169                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         596688                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         339643                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1675607                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000497                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001109                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015992                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.037070                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000560                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000193                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010562                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030869                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017731                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805818                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.835510                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.818148                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.760429                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.739209                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.751971                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.567474                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.567605                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567546                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001109                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015992                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244900                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000560                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000193                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.245034                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098789                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001109                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015992                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244900                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000560                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000193                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.245034                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098789                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        64900                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55418.352716                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 57731.062812                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60152.094573                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 62284.240597                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 58914.350533                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1720.387122                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3135.532591                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2320.539836                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   890.282132                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6919.708029                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3252.621544                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49594.391283                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53736.626185                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 51867.063109                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        64900                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55418.352716                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50343.439056                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        68500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 60152.094573                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54383.777468                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52945.451520                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        64900                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55418.352716                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50343.439056                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        68500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 60152.094573                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54383.777468                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52945.451520                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66712                       # number of writebacks
system.l2c.writebacks::total                    66712                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                72                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 72                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                72                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           11                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6273                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6379                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           17                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6295                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6277                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25258                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5125                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3774                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8899                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          638                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          411                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1049                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63279                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76923                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140202                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           11                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6273                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69658                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           17                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6295                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83200                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165460                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           11                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6273                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69658                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           17                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6295                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83200                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165460                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       262004                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    269548612                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    289309796                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1171267                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        56251                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    300356052                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    312753448                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1174048691                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51546985                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     38368705                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     89915690                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      6444113                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4119409                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10563522                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2354035161                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3171377741                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5525412902                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       262004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    269548612                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2643344957                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1171267                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        56251                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    300356052                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3484131189                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6699461593                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       262004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    269548612                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2643344957                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1171267                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        56251                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    300356052                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3484131189                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6699461593                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5299085                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12408099047                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2100282                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667429748                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167082928162                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1050132738                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  25922779804                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  26972912542                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5299085                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13458231785                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2100282                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 194055840704                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001109                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015982                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036857                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000560                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000193                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010550                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030751                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017681                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.805818                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.835510                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.818148                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.760429                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.739209                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.751971                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.567474                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.567605                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567546                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000497                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001109                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015982                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244770                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000560                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000193                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010550                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.244963                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098746                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000497                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001109                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015982                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244770                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000560                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000193                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010550                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.244963                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098746                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        56251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        56251                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40489.916554                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        56251                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40489.916554                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                5998401                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4575821                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           294349                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3757481                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2911128                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.475521                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 672992                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28616                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8907261                       # DTB read hits
system.cpu0.dtb.read_misses                     28773                       # DTB read misses
system.cpu0.dtb.write_hits                    5136781                       # DTB write hits
system.cpu0.dtb.write_misses                     5705                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1814                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1038                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   293                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      560                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8936034                       # DTB read accesses
system.cpu0.dtb.write_accesses                5142486                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14044042                       # DTB hits
system.cpu0.dtb.misses                          34478                       # DTB misses
system.cpu0.dtb.accesses                     14078520                       # DTB accesses
system.cpu0.itb.inst_hits                     4215431                       # ITB inst hits
system.cpu0.itb.inst_misses                      5154                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1347                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1523                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4220585                       # ITB inst accesses
system.cpu0.itb.hits                          4215431                       # DTB hits
system.cpu0.itb.misses                           5154                       # DTB misses
system.cpu0.itb.accesses                      4220585                       # DTB accesses
system.cpu0.numCycles                        67803924                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11747073                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32000754                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    5998401                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3584120                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7510773                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1450164                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     64498                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              20642358                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4878                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        46878                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        85526                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          225                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4213800                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               157670                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2178                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41143503                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.004869                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.385262                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                33640113     81.76%     81.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  564874      1.37%     83.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  815232      1.98%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  675522      1.64%     86.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  773200      1.88%     88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  558709      1.36%     90.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  669860      1.63%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  351529      0.85%     92.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3094464      7.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41143503                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.088467                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.471960                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12253117                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20585756                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6814381                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               512539                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                977710                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              934268                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64694                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              39987776                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               212486                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                977710                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12820427                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5742393                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      12731772                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6709970                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2161231                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38889294                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1829                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                434890                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1234500                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents              47                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39244828                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175643455                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       175609334                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34121                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30926653                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8318174                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            411256                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        370334                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5351915                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7647673                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5682766                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1124413                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1217910                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36816448                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             895564                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37227077                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            80165                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6275180                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13166441                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256842                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41143503                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.904811                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.512506                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           26013518     63.23%     63.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5726772     13.92%     77.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3163675      7.69%     84.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2471330      6.01%     90.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2096927      5.10%     95.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             946781      2.30%     98.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             487184      1.18%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             184280      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              53036      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41143503                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  25911      2.42%      2.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   452      0.04%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                841841     78.68%     81.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               201703     18.85%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52149      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22320567     59.96%     60.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46962      0.13%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              6      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           700      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9363552     25.15%     85.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5443123     14.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37227077                       # Type of FU issued
system.cpu0.iq.rate                          0.549040                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1069907                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028740                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         116773591                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         43995152                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34325365                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8374                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4656                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3873                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38240450                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4385                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          307272                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1372635                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2428                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13158                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       533443                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2192715                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5605                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                977710                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4125178                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                98819                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37830480                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            84891                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7647673                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5682766                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571414                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 40435                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 2836                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13158                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        149420                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       117102                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              266522                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             36852561                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9222790                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           374516                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       118468                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14619280                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4853073                       # Number of branches executed
system.cpu0.iew.exec_stores                   5396490                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.543517                       # Inst execution rate
system.cpu0.iew.wb_sent                      36658484                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34329238                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18277167                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35166979                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.506302                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.519725                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6089898                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         638722                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           230765                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40165793                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.778810                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.740848                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28496220     70.95%     70.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5717219     14.23%     85.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1914261      4.77%     89.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       974261      2.43%     92.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       784320      1.95%     94.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       523319      1.30%     95.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       386116      0.96%     96.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       218199      0.54%     97.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1151878      2.87%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40165793                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23678008                       # Number of instructions committed
system.cpu0.commit.committedOps              31281512                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11424361                       # Number of memory references committed
system.cpu0.commit.loads                      6275038                       # Number of loads committed
system.cpu0.commit.membars                     229662                       # Number of memory barriers committed
system.cpu0.commit.branches                   4244821                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27638419                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489334                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1151878                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    75534199                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75722713                       # The number of ROB writes
system.cpu0.timesIdled                         360446                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26660421                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2138034694                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23597266                       # Number of Instructions Simulated
system.cpu0.committedOps                     31200770                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23597266                       # Number of Instructions Simulated
system.cpu0.cpi                              2.873381                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.873381                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.348022                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.348022                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               171786019                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34080976                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3260                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     902                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               13006141                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                451094                       # number of misc regfile writes
system.cpu0.icache.replacements                392511                       # number of replacements
system.cpu0.icache.tagsinuse               511.076367                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3789958                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                393023                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.643095                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6563458000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.076367                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.998196                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.998196                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3789958                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3789958                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3789958                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3789958                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3789958                       # number of overall hits
system.cpu0.icache.overall_hits::total        3789958                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       423709                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       423709                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       423709                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        423709                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       423709                       # number of overall misses
system.cpu0.icache.overall_misses::total       423709                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5803688497                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5803688497                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5803688497                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5803688497                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5803688497                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5803688497                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4213667                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4213667                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4213667                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4213667                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4213667                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4213667                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100556                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100556                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100556                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100556                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100556                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100556                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13697.345341                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13697.345341                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2656                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              149                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.825503                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30672                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30672                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30672                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30672                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30672                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30672                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       393037                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       393037                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       393037                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       393037                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       393037                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       393037                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4746801497                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4746801497                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4746801497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4746801497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4746801497                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4746801497                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7900500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7900500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7900500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7900500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093277                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093277                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093277                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093277                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093277                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093277                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                275921                       # number of replacements
system.cpu0.dcache.tagsinuse               460.698692                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9260016                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                276433                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.498229                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43509000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   460.698692                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.899802                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.899802                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5779987                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5779987                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3159663                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3159663                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139233                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139233                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137076                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137076                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8939650                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8939650                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8939650                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8939650                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392818                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392818                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1582384                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1582384                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8769                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8769                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7464                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7464                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1975202                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1975202                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1975202                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1975202                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5481439500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5481439500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  60566359369                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  60566359369                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     87760500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     87760500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     46440000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     46440000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  66047798869                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  66047798869                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  66047798869                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  66047798869                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6172805                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6172805                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4742047                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4742047                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       148002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144540                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144540                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10914852                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10914852                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10914852                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10914852                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063637                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.063637                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333692                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.333692                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059249                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059249                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051640                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051640                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.180965                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.180965                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.180965                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.180965                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6221.864952                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6221.864952                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         8565                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         5561                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              643                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             81                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.320373                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    68.654321                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256512                       # number of writebacks
system.cpu0.dcache.writebacks::total           256512                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       204354                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       204354                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1452130                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1452130                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          476                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          476                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1656484                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1656484                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1656484                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1656484                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188464                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188464                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130254                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130254                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8293                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8293                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7464                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7464                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       318718                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       318718                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       318718                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       318718                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2378480500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2378480500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4031341491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4031341491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     65938500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     65938500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31512000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31512000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6409821991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6409821991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6409821991                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6409821991                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13514864500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13514864500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1180302878                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1180302878                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14695167378                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14695167378                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030531                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030531                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027468                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027468                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056033                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056033                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051640                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051640                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029200                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029200                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029200                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029200                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7951.103340                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7951.103340                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4221.864952                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4221.864952                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9068423                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7455270                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           408018                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             6064102                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5241151                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            86.429137                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 772299                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             42697                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42898238                       # DTB read hits
system.cpu1.dtb.read_misses                     36741                       # DTB read misses
system.cpu1.dtb.write_hits                    6823025                       # DTB write hits
system.cpu1.dtb.write_misses                    10725                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2008                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2490                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   302                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      655                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42934979                       # DTB read accesses
system.cpu1.dtb.write_accesses                6833750                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49721263                       # DTB hits
system.cpu1.dtb.misses                          47466                       # DTB misses
system.cpu1.dtb.accesses                     49768729                       # DTB accesses
system.cpu1.itb.inst_hits                     8394494                       # ITB inst hits
system.cpu1.itb.inst_misses                      5446                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1530                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1510                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8399940                       # ITB inst accesses
system.cpu1.itb.hits                          8394494                       # DTB hits
system.cpu1.itb.misses                           5446                       # DTB misses
system.cpu1.itb.accesses                      8399940                       # DTB accesses
system.cpu1.numCycles                       408755802                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19793701                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      66043012                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9068423                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6013450                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14139093                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3958938                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     65451                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              77253219                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                4575                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        41710                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       129512                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          148                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8392686                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               740378                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2825                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         114124947                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.700718                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.045131                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                99993030     87.62%     87.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  796567      0.70%     88.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  937489      0.82%     89.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1887963      1.65%     90.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1516591      1.33%     92.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  569617      0.50%     92.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2129815      1.87%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  410324      0.36%     94.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5883551      5.16%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           114124947                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022185                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.161571                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                21308374                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             76909285                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12783383                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               523008                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2600897                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1105255                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                98147                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              75181804                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               327202                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2600897                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22691617                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31944842                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      40730815                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11827860                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4328916                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              69723383                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                18766                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                668457                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3086605                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             426                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           73713482                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            321023926                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       320964994                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            58932                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49048009                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                24665473                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            444684                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        387735                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7872422                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            13201823                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8142648                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1033883                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1534096                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  63487985                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1158001                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 89118015                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            94635                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       16215431                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     45695453                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        277388                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    114124947                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.780881                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.519165                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           83732864     73.37%     73.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8404718      7.36%     80.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4298594      3.77%     84.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3768314      3.30%     87.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10582090      9.27%     97.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1967507      1.72%     98.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1024622      0.90%     99.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             272364      0.24%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              73874      0.06%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      114124947                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  29701      0.38%      0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   998      0.01%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7545557     95.86%     96.25% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               295033      3.75%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           313997      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37610156     42.20%     42.55% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59163      0.07%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  9      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1504      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43962640     49.33%     91.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7170532      8.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              89118015                       # Type of FU issued
system.cpu1.iq.rate                          0.218023                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7871289                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088324                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         300359292                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         80869896                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     53629107                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14882                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8062                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6802                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96667481                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7826                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          342650                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3449296                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3766                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17093                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1304806                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31906048                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       888017                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2600897                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               24182074                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               360611                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           64750813                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           110749                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             13201823                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8142648                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            869251                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 65576                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3534                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17093                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        201242                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       155476                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              356718                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             86688682                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43267985                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2429333                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104827                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50376799                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 6999376                       # Number of branches executed
system.cpu1.iew.exec_stores                   7108814                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.212079                       # Inst execution rate
system.cpu1.iew.wb_sent                      85711710                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     53635909                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 29908204                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53361522                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131217                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.560483                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       16119527                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         880613                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           311377                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    111524050                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.431703                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.400207                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     94787660     84.99%     84.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8229182      7.38%     92.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2114661      1.90%     94.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1254724      1.13%     95.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1244333      1.12%     96.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       567856      0.51%     97.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       997712      0.89%     97.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       503621      0.45%     98.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1824301      1.64%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    111524050                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38058618                       # Number of instructions committed
system.cpu1.commit.committedOps              48145315                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16590369                       # Number of memory references committed
system.cpu1.commit.loads                      9752527                       # Number of loads committed
system.cpu1.commit.membars                     190082                       # Number of memory barriers committed
system.cpu1.commit.branches                   5966603                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42681078                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              534481                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1824301                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   172920681                       # The number of ROB reads
system.cpu1.rob.rob_writes                  131224345                       # The number of ROB writes
system.cpu1.timesIdled                        1408365                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      294630855                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1796488086                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   37988979                       # Number of Instructions Simulated
system.cpu1.committedOps                     48075676                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             37988979                       # Number of Instructions Simulated
system.cpu1.cpi                             10.759852                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.759852                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092938                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092938                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               387889245                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56198451                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4879                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2320                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               18462900                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                405383                       # number of misc regfile writes
system.cpu1.icache.replacements                596769                       # number of replacements
system.cpu1.icache.tagsinuse               480.741673                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7750669                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                597281                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 12.976587                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74225092500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   480.741673                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.938949                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.938949                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      7750669                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7750669                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7750669                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7750669                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7750669                       # number of overall hits
system.cpu1.icache.overall_hits::total        7750669                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       641966                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       641966                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       641966                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        641966                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       641966                       # number of overall misses
system.cpu1.icache.overall_misses::total       641966                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8653423491                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8653423491                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8653423491                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8653423491                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8653423491                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8653423491                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8392635                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8392635                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8392635                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8392635                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8392635                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8392635                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.076492                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.076492                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.076492                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.076492                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.076492                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.076492                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13479.566661                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13479.566661                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         2249                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              165                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.630303                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        44655                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        44655                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        44655                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        44655                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        44655                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        44655                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       597311                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       597311                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       597311                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       597311                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       597311                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       597311                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7076959992                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7076959992                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7076959992                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7076959992                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7076959992                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7076959992                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3098500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3098500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071171                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071171                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071171                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.071171                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071171                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.071171                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                360267                       # number of replacements
system.cpu1.dcache.tagsinuse               474.654017                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                12671092                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                360637                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 35.135308                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           70354132000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   474.654017                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.927059                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.927059                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8304151                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8304151                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4137952                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4137952                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        97565                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        97565                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        94853                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        94853                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12442103                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12442103                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12442103                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12442103                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       399179                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       399179                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1556589                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1556589                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13972                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13972                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10605                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10605                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1955768                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1955768                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1955768                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1955768                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6101251500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6101251500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  61874023496                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  61874023496                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    129109000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    129109000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53792000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     53792000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  67975274996                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  67975274996                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  67975274996                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  67975274996                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8703330                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8703330                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5694541                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5694541                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       111537                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       111537                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105458                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       105458                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14397871                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14397871                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14397871                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14397871                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045865                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045865                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.273348                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.273348                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125268                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125268                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100561                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100561                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135837                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135837                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135837                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135837                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9240.552534                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9240.552534                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5072.324375                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5072.324375                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        25344                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        13325                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3330                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            157                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.610811                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    84.872611                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       324294                       # number of writebacks
system.cpu1.dcache.writebacks::total           324294                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171223                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       171223                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1395128                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1395128                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1450                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1450                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1566351                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1566351                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1566351                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1566351                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       227956                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       227956                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161461                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161461                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12522                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12522                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10600                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10600                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       389417                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       389417                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       389417                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       389417                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2851782000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2851782000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5138031205                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5138031205                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32594000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32594000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7989813205                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7989813205                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7989813205                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7989813205                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  35691035962                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  35691035962                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026192                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026192                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028354                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028354                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112268                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112268                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100514                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100514                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027047                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027047                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027047                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027047                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7042.045999                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7042.045999                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3074.905660                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3074.905660                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 540139410201                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   41727                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   48854                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------