path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.825947                       # Number of seconds simulated
sim_ticks                                2825947406000                       # Number of ticks simulated
final_tick                               2825947406000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 132633                       # Simulator instruction rate (inst/s)
host_op_rate                                   160894                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3120208803                       # Simulator tick rate (ticks/s)
host_mem_usage                                 618508                       # Number of bytes of host memory used
host_seconds                                   905.69                       # Real time elapsed on the host
sim_insts                                   120124543                       # Number of instructions simulated
sim_ops                                     145720076                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         1664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1303616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1321960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8513856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           181024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           635732                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       529024                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12488540                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1303616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       181024                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1484640                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8962368                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8979932                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           26                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             22616                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21176                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133029                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2896                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9954                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         8266                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197989                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          140037                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               144428                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           589                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              461302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              467794                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3012744                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           136                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               64058                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              224962                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       187202                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4419240                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         461302                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          64058                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             525360                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3171456                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6201                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3177671                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3171456                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          589                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             461302                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             473995                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3012744                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              64058                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             224977                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       187202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7596911                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197990                       # Number of read requests accepted
system.physmem.writeReqs                       144428                       # Number of write requests accepted
system.physmem.readBursts                      197990                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     144428                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12662400                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8960                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8992448                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12488604                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8979932                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      140                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12407                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12295                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12935                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12653                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14543                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12106                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12653                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12509                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12223                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12064                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11718                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11008                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11914                       # Per bank write bursts
system.physmem.perBankRdBursts::13              13060                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12107                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11655                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9105                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9127                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9615                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9150                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8481                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8750                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8993                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8806                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8720                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8569                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8518                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8119                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8743                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9182                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8573                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8056                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
system.physmem.totGap                    2825947136000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  194325                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 140037                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     60161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     72217                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15830                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8715                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      6523                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      5382                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4740                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      989                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      744                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      304                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92378                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      234.414947                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     132.500025                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     299.048436                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          50794     54.98%     54.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17715     19.18%     74.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5941      6.43%     80.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3366      3.64%     84.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2816      3.05%     87.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1529      1.66%     88.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          925      1.00%     89.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          990      1.07%     91.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8302      8.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92378                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6992                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.296339                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      556.591514                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6990     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6992                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6992                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.095395                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.609227                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.295574                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5854     83.72%     83.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             392      5.61%     89.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              80      1.14%     90.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              62      0.89%     91.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             277      3.96%     95.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              20      0.29%     95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              15      0.21%     95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              24      0.34%     96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              25      0.36%     96.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.17%     96.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.13%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.20%     97.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             142      2.03%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              10      0.14%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.10%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.09%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.04%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.04%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.20%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.04%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6992                       # Writes before turning the bus around for reads
system.physmem.totQLat                     6748582846                       # Total ticks spent queuing
system.physmem.totMemAccLat               10458270346                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    989250000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       34109.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  52859.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.18                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.42                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.18                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165284                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80694                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.54                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.42                       # Row buffer hit rate for writes
system.physmem.avgGap                      8252916.42                       # Average gap between requests
system.physmem.pageHitRate                      72.69                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  361058040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  197005875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 796387800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                466734960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184576766400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            79734690540                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1625622381750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1891755025365                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.424618                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2704272847388                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94364400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27304587612                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  337319640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  184053375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 746834400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                443750400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184576766400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79554512970                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1625780432250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1891623669435                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.378136                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2704538486760                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94364400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     27044516240                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          112                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          176                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          288                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             18                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           62                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              102                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           62                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          102                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               53058502                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         24374377                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           933450                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            32093175                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               13944864                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            43.451182                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               15470259                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             33206                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups       10120086                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           9964746                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          155340                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        48572                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    67164                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               67164                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25323                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        19031                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        22810                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        44354                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   458.594490                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  2953.911408                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        43233     97.47%     97.47% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          862      1.94%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          108      0.24%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767          108      0.24%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959            9      0.02%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           18      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535           14      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        44354                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        17047                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9658.702439                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6683.029230                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383        15750     92.39%     92.39% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1185      6.95%     99.34% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           75      0.44%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535           14      0.08%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.03%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687           14      0.08%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        17047                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  85757506152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.515718                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.512261                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  85699757152     99.93%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     40650000      0.05%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5      7189500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4730000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      1448500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1006500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1064000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1646000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17        14500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  85757506152                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5272     77.42%     77.42% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1538     22.58%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6810                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67164                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67164                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6810                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6810                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        73974                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23645826                       # DTB read hits
system.cpu0.dtb.read_misses                     56383                       # DTB read misses
system.cpu0.dtb.write_hits                   17571331                       # DTB write hits
system.cpu0.dtb.write_misses                    10781                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3487                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      213                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2243                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      818                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                23702209                       # DTB read accesses
system.cpu0.dtb.write_accesses               17582112                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         41217157                       # DTB hits
system.cpu0.dtb.misses                          67164                       # DTB misses
system.cpu0.dtb.accesses                     41284321                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    10883                       # Table walker walks requested
system.cpu0.itb.walker.walksShort               10883                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3898                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5925                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         1060                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         9823                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean   449.709865                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  2327.234590                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095         9434     96.04%     96.04% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191          184      1.87%     97.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287          123      1.25%     99.17% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383           44      0.45%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479            7      0.07%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575           18      0.18%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767            4      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863            3      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         9823                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3631                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4771.165368                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          614     16.91%     16.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         2801     77.14%     94.05% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          142      3.91%     97.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           43      1.18%     99.15% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           27      0.74%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            3      0.08%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3631                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  21332036712                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.795904                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.403169                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     4354826000     20.41%     20.41% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    16976239212     79.58%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2         901500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  21332036712                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2243     87.24%     87.24% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          328     12.76%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2571                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10883                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10883                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2571                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2571                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        13454                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    72708520                       # ITB inst hits
system.cpu0.itb.inst_misses                     10883                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2280                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1927                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                72719403                       # ITB inst accesses
system.cpu0.itb.hits                         72708520                       # DTB hits
system.cpu0.itb.misses                          10883                       # DTB misses
system.cpu0.itb.accesses                     72719403                       # DTB accesses
system.cpu0.numPwrStateTransitions               3678                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1839                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1481668762.034258                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23877600166.586662                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1061     57.69%     57.69% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          773     42.03%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499971949600                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1839                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   101158552619                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       202318013                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          20370009                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     195788924                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   53058502                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          39379869                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    174489676                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                5690920                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    148682                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               56911                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       412776                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       413906                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles        90774                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 72708226                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               258373                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   5359                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         198828194                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.203611                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.307839                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                93974548     47.26%     47.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                30342793     15.26%     62.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                14563641      7.32%     69.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                59947212     30.15%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           198828194                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.262253                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.967729                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                25600367                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            106949118                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 58799478                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              4963264                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               2515967                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             3058039                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               333585                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             154217934                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              3811468                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               2515967                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                34209280                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12450122                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      83570932                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 55016631                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             11065262                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             137539344                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1033397                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1452682                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                164882                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 58749                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               6858829                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          141646141                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            634543216                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       152633070                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             9368                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            130461493                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                11184637                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           2697680                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       2556046                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 22573700                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            24576087                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           19059052                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1700091                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2321608                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 134608055                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1714170                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                132746710                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           453040                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10578491                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     21717645                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        121089                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    198828194                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.667645                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       0.963186                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          122140771     61.43%     61.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           33611714     16.90%     78.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           31218891     15.70%     94.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           10730115      5.40%     99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1126646      0.57%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 57      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      198828194                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               10786366     43.89%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    65      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5629308     22.91%     66.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8160859     33.21%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             89668905     67.55%     67.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult              111084      0.08%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8099      0.01%     67.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            24336393     18.33%     85.97% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           18619956     14.03%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             132746710                       # Type of FU issued
system.cpu0.iq.rate                          0.656129                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   24576598                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.185139                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         489318685                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        146908772                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    129217545                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              32566                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             11248                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         9717                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             157299800                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  21235                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          365614                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1914996                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2485                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        19372                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       896753                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       121022                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       362352                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               2515967                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1594217                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               188418                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          136474692                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             24576087                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            19059052                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            876204                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 28441                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               136041                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         19372                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        261507                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       398935                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              660442                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            131715074                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             23894149                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           964599                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       152467                       # number of nop insts executed
system.cpu0.iew.exec_refs                    42353114                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                25555008                       # Number of branches executed
system.cpu0.iew.exec_stores                  18458965                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.651030                       # Inst execution rate
system.cpu0.iew.wb_sent                     131158694                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    129227262                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 65946343                       # num instructions producing a value
system.cpu0.iew.wb_consumers                106655009                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.638733                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.618315                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts        9548145                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1593081                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           603957                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    195669167                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.643258                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.340979                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    135298586     69.15%     69.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     33412613     17.08%     86.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     12639367      6.46%     92.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3246710      1.66%     94.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      4896676      2.50%     96.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      2794942      1.43%     98.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1306268      0.67%     98.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       556762      0.28%     99.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1517243      0.78%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    195669167                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           103932879                       # Number of instructions committed
system.cpu0.commit.committedOps             125865777                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      40823389                       # Number of memory references committed
system.cpu0.commit.loads                     22661090                       # Number of loads committed
system.cpu0.commit.membars                     647148                       # Number of memory barriers committed
system.cpu0.commit.branches                  24954311                       # Number of branches committed
system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                109885490                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             4835541                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        84925464     67.47%     67.47% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult         108825      0.09%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8099      0.01%     67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       22661090     18.00%     85.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      18162299     14.43%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        125865777                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1517243                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   306278084                       # The number of ROB reads
system.cpu0.rob.rob_writes                  273977566                       # The number of ROB writes
system.cpu0.timesIdled                         123981                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3489819                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5449576943                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  103810827                       # Number of Instructions Simulated
system.cpu0.committedOps                    125743725                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.948911                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.948911                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.513107                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.513107                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               142709258                       # number of integer regfile reads
system.cpu0.int_regfile_writes               81672792                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     8185                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                464864695                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                49723023                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              392114938                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1224736                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           709879                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          499.426037                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           37661762                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           710391                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            53.015539                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        278078500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   499.426037                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.975441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.975441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         81162963                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        81162963                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     21452365                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       21452365                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     14987011                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      14987011                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       308699                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       308699                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363086                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       363086                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361018                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361018                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     36439376                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        36439376                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     36748075                       # number of overall hits
system.cpu0.dcache.overall_hits::total       36748075                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       646473                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       646473                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1887751                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1887751                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147620                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       147620                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25081                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        25081                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20154                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20154                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2534224                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2534224                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2681844                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2681844                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8640238000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   8640238000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29904279351                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  29904279351                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    399794500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    399794500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    485945500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    485945500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       390500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       390500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  38544517351                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  38544517351                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  38544517351                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  38544517351                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     22098838                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     22098838                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     16874762                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     16874762                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456319                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       456319                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388167                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       388167                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381172                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381172                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     38973600                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     38973600                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     39429919                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     39429919                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029254                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.029254                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.111868                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.111868                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323502                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323502                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064614                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064614                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052874                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052874                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.065024                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.065024                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.068015                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.068015                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          691                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      4275244                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               43                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         201901                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.069767                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    21.174952                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       709879                       # number of writebacks
system.cpu0.dcache.writebacks::total           709879                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       258972                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       258972                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1563802                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1563802                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18565                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18565                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1822774                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1822774                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1822774                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1822774                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       387501                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       387501                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       323949                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       323949                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101413                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       101413                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6516                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6516                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20154                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20154                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       711450                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       711450                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       812863                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       812863                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31772                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31772                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28451                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28451                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60223                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60223                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4575351000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4575351000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6134433385                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6134433385                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1666291000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1666291000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103051000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103051000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    465800500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    465800500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       381500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       381500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10709784385                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10709784385                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12376075385                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12376075385                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6621057500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6621057500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6621057500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6621057500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017535                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017535                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019197                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019197                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222241                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222241                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016787                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016787                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052874                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052874                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018255                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.018255                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020615                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020615                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1252995                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.762307                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           71397425                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1253507                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            56.958138                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7880422000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.762307                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999536                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999536                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        146662859                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       146662859                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     71397425                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       71397425                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     71397425                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        71397425                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     71397425                       # number of overall hits
system.cpu0.icache.overall_hits::total       71397425                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1307231                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1307231                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1307231                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1307231                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1307231                       # number of overall misses
system.cpu0.icache.overall_misses::total      1307231                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13217921463                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13217921463                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13217921463                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13217921463                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13217921463                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13217921463                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     72704656                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     72704656                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     72704656                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     72704656                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     72704656                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     72704656                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.017980                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.017980                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.017980                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.017980                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.017980                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.017980                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10111.389236                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10111.389236                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10111.389236                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10111.389236                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10111.389236                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10111.389236                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1578280                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          443                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           112202                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.066416                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets    44.300000                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1252995                       # number of writebacks
system.cpu0.icache.writebacks::total          1252995                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53683                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        53683                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        53683                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        53683                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        53683                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        53683                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1253548                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1253548                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1253548                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1253548                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1253548                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1253548                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11993376465                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11993376465                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11993376465                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11993376465                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11993376465                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11993376465                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    269145498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    269145498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017242                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.017242                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.017242                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9567.544653                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9567.544653                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9567.544653                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1837427                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1839978                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         2305                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       236878                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          277234                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16111.552153                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3276769                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          293338                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           11.170626                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.282247                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.429995                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1405.940159                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.896844                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000689                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000026                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.085812                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983371                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1005                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15089                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           38                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          280                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          408                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          279                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          460                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4705                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7019                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2801                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061340                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920959                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        66263541                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       66263541                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        55477                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        13130                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         68607                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       482403                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       482403                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1449230                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1449230                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       221307                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       221307                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1200077                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1200077                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       398579                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       398579                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        55477                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        13130                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1200077                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       619886                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1888570                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        55477                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        13130                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1200077                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       619886                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1888570                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          420                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          151                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          571                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55011                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55011                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20153                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20153                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        47810                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        47810                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        53438                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        53438                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        96741                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        96741                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          420                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          151                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        53438                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144551                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       198560                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          420                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          151                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        53438                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144551                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       198560                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     11930500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3564500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     15495000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    109148000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    109148000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     23796000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     23796000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       365500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       365500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2790491998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2790491998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2793539000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2793539000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2953442497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2953442497                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     11930500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3564500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2793539000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5743934495                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8552968495                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     11930500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3564500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2793539000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5743934495                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8552968495                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        55897                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        13281                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        69178                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       482403                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       482403                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1449230                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1449230                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55012                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55012                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269117                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269117                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1253515                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1253515                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       495320                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       495320                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        55897                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        13281                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1253515                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       764437                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2087130                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        55897                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        13281                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1253515                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       764437                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2087130                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007514                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.011370                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.008254                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.177655                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.177655                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042631                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042631                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.195310                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.195310                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007514                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.011370                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042631                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.189095                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.095135                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007514                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.011370                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042631                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.189095                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.095135                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27136.602452                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  1984.112268                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  1984.112268                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1180.767131                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1180.767131                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       365500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       365500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58366.283163                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58366.283163                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52276.264082                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52276.264082                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30529.377379                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30529.377379                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52276.264082                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39736.387123                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 43074.982348                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52276.264082                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39736.387123                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 43074.982348                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          102                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10219                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       230013                       # number of writebacks
system.cpu0.l2cache.writebacks::total          230013                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5832                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5832                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           47                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           47                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          763                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          763                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           47                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6595                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6642                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           47                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6595                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6642                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          420                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          151                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          571                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       257265                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       257265                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55011                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55011                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20153                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20153                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41978                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41978                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        53391                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        53391                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        95978                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        95978                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          420                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          151                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        53391                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       137956                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       191918                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          420                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          151                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        53391                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       137956                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       257265                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       449183                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31772                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34775                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28451                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28451                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60223                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63226                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12069000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15460252226                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15460252226                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1068009500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1068009500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    313481500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    313481500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       311500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       311500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1799415000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1799415000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2471910000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2471910000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2337830497                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2337830497                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2471910000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4137245497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6621224497                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2471910000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4137245497                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15460252226                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  22081476723                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6366599000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6613220000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6366599000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6613220000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008254                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.155984                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.155984                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042593                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.193770                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.193770                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.180467                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.091953                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.180467                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.215216                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       311500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       311500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      4076758                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2058809                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31269                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       324106                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       319070                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         5036                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        113929                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1910818                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28451                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28451                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       712670                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1480466                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       204485                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       327834                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        86644                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42628                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112569                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           27                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       287578                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284142                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1253548                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       576173                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3244                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3766063                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2610032                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29029                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119282                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6524406                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    160464624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98586020                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53124                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       223588                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         259327356                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1029792                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18816792                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      3154811                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.120834                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.330795                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2778640     88.08%     88.08% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            371135     11.76%     99.84% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              5036      0.16%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3154811                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    4076288994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113402059                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1883892360                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1231592300                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     15761972                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     63433401                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                4691512                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2780704                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           269312                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2468444                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1570862                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            63.637741                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 878870                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7026                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups         249224                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits            213650                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           35574                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        10610                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    21486                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               21486                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8656                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5913                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore         6917                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        14569                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   593.417530                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3219.344489                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095        13924     95.57%     95.57% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191          194      1.33%     96.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287          239      1.64%     98.54% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383           88      0.60%     99.15% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479           24      0.16%     99.31% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575           16      0.11%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671            5      0.03%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767           66      0.45%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863            2      0.01%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959            7      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        14569                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5700                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9917.122912                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6183.592938                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1944     34.11%     34.11% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         3149     55.25%     89.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          398      6.98%     96.33% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          155      2.72%     99.05% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           22      0.39%     99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           24      0.42%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.09%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5700                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  72594020264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.245062                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.433850                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  72572506264     99.97%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     16659500      0.02%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5      2233500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      1798000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9       337000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11       155000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       183000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15       133000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17        15000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  72594020264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1956     73.89%     73.89% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          691     26.11%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2647                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21486                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21486                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2647                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2647                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24133                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4198525                       # DTB read hits
system.cpu1.dtb.read_misses                     18524                       # DTB read misses
system.cpu1.dtb.write_hits                    3495808                       # DTB write hits
system.cpu1.dtb.write_misses                     2962                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1985                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       48                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   390                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      375                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4217049                       # DTB read accesses
system.cpu1.dtb.write_accesses                3498770                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7694333                       # DTB hits
system.cpu1.dtb.misses                          21486                       # DTB misses
system.cpu1.dtb.accesses                      7715819                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     5992                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                5992                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2735                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2646                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          611                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         5381                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   357.461438                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  2249.604382                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047         5186     96.38%     96.38% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095           43      0.80%     97.18% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143           39      0.72%     97.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191           21      0.39%     98.29% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239           21      0.39%     98.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287           16      0.30%     98.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335           17      0.32%     99.29% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383            9      0.17%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-18431            6      0.11%     99.57% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::18432-20479            2      0.04%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527            6      0.11%     99.72% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575            3      0.06%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623            4      0.07%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671            4      0.07%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-30719            2      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::30720-32767            2      0.04%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         5381                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1781                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6875.589868                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         1655     92.93%     92.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767           93      5.22%     98.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-49151           29      1.63%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-65535            1      0.06%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-81919            1      0.06%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-147455            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1781                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  16739710416                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.877376                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.328141                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     2053443264     12.27%     12.27% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    14685521152     87.73%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2         746000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  16739710416                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          995     85.04%     85.04% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          175     14.96%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1170                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5992                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5992                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1170                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1170                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         7162                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     8257878                       # ITB inst hits
system.cpu1.itb.inst_misses                      5992                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1134                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      574                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8263870                       # ITB inst accesses
system.cpu1.itb.hits                          8257878                       # DTB hits
system.cpu1.itb.misses                           5992                       # DTB misses
system.cpu1.itb.accesses                      8263870                       # DTB accesses
system.cpu1.numPwrStateTransitions               5517                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2759                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1017941071.285973                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25840669198.429722                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1966     71.26%     71.26% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          787     28.52%     99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 959984595936                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2759                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    17447990322                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                        34896767                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           8573013                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      24834691                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    4691512                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           2663382                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     24575638                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 780918                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     78787                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               29336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       166978                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       305850                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles        23292                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8256698                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               107917                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2264                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          34143353                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.885357                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.219701                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                20247760     59.30%     59.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 4892921     14.33%     73.63% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1671892      4.90%     78.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 7330780     21.47%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            34143353                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.134440                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.711662                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 7142387                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             16886237                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  8753269                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1097578                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                263882                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              709919                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               129188                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              23442151                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              1047211                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                263882                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 8565513                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2371212                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      11834998                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8406528                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2701220                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              22274891                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               187368                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               265665                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 37047                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 14963                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1683318                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           22278743                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            103710935                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        25664622                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             1667                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             19882725                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2396018                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            407656                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        334437                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2896541                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             4450446                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            3799896                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           626454                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          628235                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  21459278                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             560382                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 21266552                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            92050                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2043308                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      4721488                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         43321                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     34143353                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.622861                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.949388                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           21621380     63.33%     63.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6152293     18.02%     81.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4252408     12.45%     93.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            1859652      5.45%     99.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             257613      0.75%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                  7      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       34143353                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                1436712     29.87%     29.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   667      0.01%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     29.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1615148     33.58%     63.46% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1757949     36.54%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             13152288     61.84%     61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               28200      0.13%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.98% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3301      0.02%     61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             4404606     20.71%     82.70% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            3678091     17.30%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              21266552                       # Type of FU issued
system.cpu1.iq.rate                          0.609413                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4810476                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.226199                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          81572724                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         24071099                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     20803651                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads               6259                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              2054                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         1789                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              26072828                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   4134                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           87634                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       411414                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          595                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        10207                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       255357                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        40430                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        77958                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                263882                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 544522                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                96828                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           22060743                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              4450446                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             3799896                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            297241                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  7639                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                82763                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         10207                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         34804                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       119058                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              153862                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             21034955                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              4309085                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           210133                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        41083                       # number of nop insts executed
system.cpu1.iew.exec_refs                     7936975                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 3061868                       # Number of branches executed
system.cpu1.iew.exec_stores                   3627890                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.602777                       # Inst execution rate
system.cpu1.iew.wb_sent                      20903580                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     20805440                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 10431521                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 16355895                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.596200                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.637784                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        1829884                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         517061                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           142735                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     33733433                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.593157                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.351929                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     24180502     71.68%     71.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      5607484     16.62%     88.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1690092      5.01%     93.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       667448      1.98%     95.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       524113      1.55%     96.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       341983      1.01%     97.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       221163      0.66%     98.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       119335      0.35%     98.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       381313      1.13%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     33733433                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            16346571                       # Number of instructions committed
system.cpu1.commit.committedOps              20009206                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       7583571                       # Number of memory references committed
system.cpu1.commit.loads                      4039032                       # Number of loads committed
system.cpu1.commit.membars                     208429                       # Number of memory barriers committed
system.cpu1.commit.branches                   2907402                       # Number of branches committed
system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 17776817                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              462681                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        12395212     61.95%     61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          27122      0.14%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     62.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3301      0.02%     62.10% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     62.10% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.10% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.10% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        4039032     20.19%     82.29% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       3544539     17.71%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         20009206                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               381313                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                    54211090                       # The number of ROB reads
system.cpu1.rob.rob_writes                   44079362                       # The number of ROB writes
system.cpu1.timesIdled                          55353                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         753414                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5616440201                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   16313716                       # Number of Instructions Simulated
system.cpu1.committedOps                     19976351                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.139106                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.139106                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.467485                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.467485                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                23597502                       # number of integer regfile reads
system.cpu1.int_regfile_writes               13487852                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     1401                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                 75515975                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                 6821727                       # number of cc regfile writes
system.cpu1.misc_regfile_reads               68877879                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                387520                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           189327                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.259638                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6803525                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           189662                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            35.871840                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     103705106000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.259638                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922382                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.922382                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          335                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          318                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.654297                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         15106665                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        15106665                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      3632818                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3632818                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2917516                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2917516                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48925                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        48925                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78194                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78194                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70603                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        70603                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6550334                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6550334                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6599259                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6599259                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       216356                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       216356                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       400081                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       400081                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30281                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30281                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18627                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18627                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23453                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23453                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       616437                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        616437                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       646718                       # number of overall misses
system.cpu1.dcache.overall_misses::total       646718                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3492190500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3492190500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10142172955                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  10142172955                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    366644000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    366644000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    571781000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    571781000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1485000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1485000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  13634363455                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  13634363455                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  13634363455                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  13634363455                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3849174                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3849174                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3317597                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3317597                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79206                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79206                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96821                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96821                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94056                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94056                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7166771                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7166771                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7245977                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7245977                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.056208                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.056208                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.120594                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.120594                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382307                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382307                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.192386                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.192386                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249351                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249351                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.086013                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.086013                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089252                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.089252                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          336                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1512378                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               30                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          40281                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.200000                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    37.545692                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       189327                       # number of writebacks
system.cpu1.dcache.writebacks::total           189327                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79455                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        79455                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       309049                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       309049                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13259                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13259                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       388504                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       388504                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       388504                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       388504                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       136901                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       136901                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91032                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91032                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28913                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        28913                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5368                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5368                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23453                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23453                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       227933                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       227933                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       256846                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       256846                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2438                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2438                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5519                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5519                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1914813500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1914813500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2474458965                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2474458965                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    498834500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    498834500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     96515500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     96515500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    548354000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    548354000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1459000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1459000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4389272465                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4389272465                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4888106965                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4888106965                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    442121000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    442121000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    442121000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    442121000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035566                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035566                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027439                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027439                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.365035                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.365035                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055443                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055443                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249351                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249351                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031804                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031804                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035447                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035447                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           586343                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.448153                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            7647462                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           586855                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            13.031263                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      79062638500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.448153                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975485                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975485                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         17099739                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        17099739                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst      7647462                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7647462                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7647462                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7647462                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7647462                       # number of overall hits
system.cpu1.icache.overall_hits::total        7647462                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       608974                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       608974                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       608974                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        608974                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       608974                       # number of overall misses
system.cpu1.icache.overall_misses::total       608974                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5478938231                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5478938231                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5478938231                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5478938231                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5478938231                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5478938231                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8256436                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8256436                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8256436                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8256436                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8256436                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8256436                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073757                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.073757                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073757                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.073757                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073757                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.073757                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8996.998609                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8996.998609                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8996.998609                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8996.998609                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8996.998609                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8996.998609                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       488402                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets           32                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            41185                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.858735                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets           32                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       586343                       # number of writebacks
system.cpu1.icache.writebacks::total           586343                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        22107                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        22107                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        22107                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        22107                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        22107                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        22107                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       586867                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       586867                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       586867                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       586867                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       586867                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       586867                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          101                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          101                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5026245111                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5026245111                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5026245111                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5026245111                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5026245111                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5026245111                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9125500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9125500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9125500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9125500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071080                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.071080                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.071080                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8564.538662                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8564.538662                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8564.538662                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       204963                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       205672                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          636                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59720                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           51812                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15242.895875                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1332238                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           66423                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           20.056878                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     9.856539                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.176183                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   447.754371                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.902289                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000602                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000133                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027329                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.930353                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          977                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13602                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          835                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          128                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          439                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8705                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4458                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059631                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001953                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.830200                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        26728427                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       26728427                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16758                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         6223                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         22981                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       115160                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       115160                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       648098                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       648098                       # number of WritebackClean hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27344                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27344                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       570840                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       570840                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       101859                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       101859                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16758                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         6223                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       570840                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       129203                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         723024                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16758                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6223                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       570840                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       129203                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        723024                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          453                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          249                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          702                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29938                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29938                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23451                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23451                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34420                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34420                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        16015                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        16015                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69307                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        69307                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          453                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          249                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        16015                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       103727                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       120444                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          453                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          249                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        16015                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       103727                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       120444                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9914500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5311000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     15225500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     63914000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     63914000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     34438500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     34438500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1420000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1420000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1452051999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1452051999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    660407500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    660407500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1570017499                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1570017499                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9914500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5311000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    660407500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3022069498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3697702498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9914500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5311000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    660407500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3022069498                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3697702498                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17211                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6472                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        23683                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       115160                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       115160                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       648098                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       648098                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29938                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29938                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23452                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23452                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61764                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61764                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       586855                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       586855                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       171166                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       171166                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17211                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6472                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       586855                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       232930                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       843468                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17211                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6472                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       586855                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       232930                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       843468                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.029642                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.557283                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.557283                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027290                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027290                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.404911                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.404911                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027290                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.445314                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.142796                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027290                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.445314                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.142796                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21688.746439                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2134.878749                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2134.878749                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1468.530127                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1468.530127                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1420000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1420000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42186.287013                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42186.287013                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41236.809241                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41236.809241                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22653.086975                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22653.086975                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41236.809241                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29134.839511                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30700.595281                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41236.809241                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29134.839511                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30700.595281                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          122                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    30.500000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             841                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        37209                       # number of writebacks
system.cpu1.l2cache.writebacks::total           37209                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          554                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          554                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           67                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           67                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            4                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          621                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          625                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            4                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          621                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          625                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          453                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          249                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          702                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        27386                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        27386                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29938                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29938                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23451                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23451                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33866                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33866                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        16011                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        16011                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69240                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69240                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          453                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          249                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        16011                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103106                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       119819                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          453                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          249                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        16011                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103106                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        27386                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       147205                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3182                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2438                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2438                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5519                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5620                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11013500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1234227220                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1234227220                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    500545000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    500545000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    372231000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    372231000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1264000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1264000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1182076500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1182076500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    564261500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    564261500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1152682499                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1152682499                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    564261500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2334758999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2910033999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    564261500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2334758999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1234227220                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4144261219                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8368000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    417428000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    425796000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8368000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    417428000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    425796000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029642                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.548313                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.548313                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027283                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.404520                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.404520                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.442648                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.142055                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.442648                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.174524                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1264000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1264000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1659506                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       839728                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12423                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       183739                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       180899                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2840                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         31691                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       827645                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2438                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2438                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       153507                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       660509                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       108712                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        33822                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        71296                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41636                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86274                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        68587                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66399                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       586867                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       252106                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          259                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1760267                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       848480                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14499                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37693                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2660939                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     75086288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29768550                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        25888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        68844                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         104949570                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     408766                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              5198376                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1235773                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.169662                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.381410                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1028949     83.26%     83.26% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            203984     16.51%     99.77% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              2840      0.23%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1235773                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1618384496                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80334899                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    880530739                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    381648033                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      8035982                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     20499963                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59421                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484042                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40384000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               112000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               328500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                31000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6095500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            33840000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187690100                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84717000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36458                       # number of replacements
system.iocache.tags.tagsinuse               14.555462                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         255127474000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.555462                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.909716                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.909716                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36476                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
system.iocache.overall_misses::total            36476                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32581877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32581877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4303830223                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4303830223                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4336412100                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4336412100                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4336412100                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4336412100                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36476                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36476                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36476                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36476                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129293.162698                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118883.981248                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118883.981248                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118883.981248                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118883.981248                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            32                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     5.333333                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36476                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36476                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36476                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36476                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19981877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19981877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2490259225                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2490259225                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2510241102                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2510241102                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2510241102                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2510241102                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68818.979658                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68818.979658                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   132786                       # number of replacements
system.l2c.tags.tagsinuse                63192.932289                       # Cycle average of tags in use
system.l2c.tags.total_refs                     445408                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   196622                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.265301                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13716.070006                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    16.287927                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.059977                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8086.686479                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2783.200527                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     4.598228                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.910717                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1777.688460                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      638.769137                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2513.055836                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.209291                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000249                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.123393                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042468                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.513529                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000070                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.027125                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009747                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.038346                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.964248                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29165                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           20                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34651                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5622                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23349                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          598                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6765                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        27255                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.445023                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.528732                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6142016                       # Number of tag accesses
system.l2c.tags.data_accesses                 6142016                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       267222                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          267222                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32477                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2702                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               35179                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2050                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           948                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              2998                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3952                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1344                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5296                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          189                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           79                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        33758                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        47203                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46059                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           69                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           37                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        13188                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         9867                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5574                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           156023                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           189                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            79                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               33758                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51155                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46059                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            69                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            37                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               13188                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               11211                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5574                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  161319                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          189                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           79                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              33758                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51155                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46059                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           69                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           37                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              13188                       # number of overall hits
system.l2c.overall_hits::cpu1.data              11211                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5574                       # number of overall hits
system.l2c.overall_hits::total                 161319                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9039                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2774                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11813                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          653                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1278                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1931                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11611                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8840                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              20451                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           26                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19633                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9253                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133186                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            6                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2822                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1110                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8266                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         174307                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           26                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19633                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20864                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133186                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2822                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9950                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         8266                       # number of demand (read+write) misses
system.l2c.demand_misses::total                194758                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           26                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19633                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20864                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133186                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2822                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9950                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         8266                       # number of overall misses
system.l2c.overall_misses::total               194758                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      9483000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2934500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     12417500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1522000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1065500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2587500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1194143500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    746705000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1940848500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2594500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       241000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1627006500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    844846000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  14630340281                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       545000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       187000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    244475000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    105182000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1113216216                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  18568633497                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2594500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       241000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1627006500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2038989500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14630340281                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       545000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       187000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    244475000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    851887000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1113216216                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     20509481997                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2594500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       241000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1627006500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2038989500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14630340281                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       545000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       187000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    244475000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    851887000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1113216216                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    20509481997                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       267222                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       267222                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41516                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5476                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           46992                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2703                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2226                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4929                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15563                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10184                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25747                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          215                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           82                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        53391                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        56456                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179245                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           75                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           39                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        16010                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        10977                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        13840                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       330330                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          215                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           82                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           53391                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           72019                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179245                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           75                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           39                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           16010                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21161                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        13840                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              356077                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          215                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           82                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          53391                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          72019                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179245                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           75                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           39                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          16010                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21161                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        13840                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             356077                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.217723                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.506574                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.251383                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.241583                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.574124                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.391763                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.746064                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.868028                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.794306                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.120930                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.036585                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.367721                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.163898                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.176265                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.101121                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.527675                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.120930                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.036585                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.367721                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.289701                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.176265                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.470205                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.546955                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.120930                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.036585                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.367721                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.289701                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.176265                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.470205                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.546955                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1049.120478                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1057.858688                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1051.172437                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2330.781011                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   833.724570                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1339.979285                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102845.878908                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84468.891403                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 94902.376412                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82871.007997                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91305.090241                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        93500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86631.821403                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94758.558559                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 106528.329310                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82871.007997                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 97727.640913                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        93500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 86631.821403                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85616.783920                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 105307.520086                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82871.007997                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 97727.640913                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        93500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 86631.821403                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85616.783920                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 105307.520086                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              103831                       # number of writebacks
system.l2c.writebacks::total                   103831                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           16                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           27                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 27                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                27                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3781                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3781                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9039                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2774                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11813                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          653                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1278                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1931                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11611                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8840                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         20451                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           26                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19623                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9253                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133186                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            6                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2806                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1109                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8266                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       174280                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           26                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19623                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20864                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133186                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2806                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9949                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8266                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           194731                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           26                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19623                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20864                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133186                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2806                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9949                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8266                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          194731                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31772                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3078                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        37954                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28451                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2438                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30889                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60223                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5516                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        68843                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    214811000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     63023000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    277834000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16846000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     31830500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     48676500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1078033001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    658304002                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1736337003                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      2334500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       211000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1430147005                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    752316000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13298476788                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       485000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker       167000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    215303006                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     94038501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1030554221                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  16824033021                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2334500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       211000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1430147005                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1830349001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  13298476788                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       485000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       167000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    215303006                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    752342503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1030554221                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  18560370024                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2334500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       211000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1430147005                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1830349001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13298476788                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       485000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       167000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    215303006                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    752342503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1030554221                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  18560370024                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5794675500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6549000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    361974000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6355765000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5794675500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6549000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    361974000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6355765000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.217723                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.506574                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.251383                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.241583                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.574124                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.391763                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.746064                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.868028                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.794306                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.163898                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.101029                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.527594                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.289701                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.470157                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.546879                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.289701                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.470157                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.546879                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23764.907623                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22719.178082                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23519.343097                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25797.856049                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24906.494523                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25207.923356                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92845.835931                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74468.778507                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 84902.303213                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81305.090241                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84795.762849                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 95312.867617                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 95312.867617                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        523570                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       298445                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          572                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               37954                       # Transaction distribution
system.membus.trans_dist::ReadResp             212485                       # Transaction distribution
system.membus.trans_dist::WriteReq              30889                       # Transaction distribution
system.membus.trans_dist::WriteResp             30889                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       140037                       # Transaction distribution
system.membus.trans_dist::CleanEvict            17084                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            74884                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40573                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40212                       # Transaction distribution
system.membus.trans_dist::ReadExResp            20363                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        174532                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107914                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13624                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       661033                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       782607                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 855556                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19150328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19340658                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21658802                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           122046                       # Total snoops (count)
system.membus.snoopTraffic                      36480                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            435271                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.011878                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.108336                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  430101     98.81%     98.81% # Request fanout histogram
system.membus.snoop_fanout::1                    5170      1.19%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              435271                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81633500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11523000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1022470046                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1120816043                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1359381                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1014149                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       548985                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       155175                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          21000                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        20112                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          888                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              37957                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            486750                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30889                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30889                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       371053                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          122899                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          109975                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43571                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         153546                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           35                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50842                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50842                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       448796                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4596                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1244094                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       315957                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1560051                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34491784                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5674154                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               40165938                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          382861                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15835212                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           859470                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.375184                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.486300                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 537899     62.58%     62.58% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 320683     37.31%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    888      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             859470                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          886309294                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           356119                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         648979933                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         232794950                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1839                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2759                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------